Robert Benson
David Hover
Jonathan Tate
Paul Niewoonder
ROBERT BENSON
Primary Goal
 Embedded Software Graphics Accelerator
 Shader Unit



Media-Centric Co-Processor
High Floating-Point Computation Performance
Graphical Computation
 Complete Software Graphics Pipeline
Hardware
 Custom Multi-FPGA Development Board
 Cyclone III FPGAs
 Outputs


VGA Port
LEDs
 Inputs


8-Directional Joysticks
JTAG Programming Port
Hardware Block Diagram
Hardware Details
 Abdomen
 Cyclone III (EP3C16Q240C8)
 DAC (ADV7123)
 Serial Programming Device (EPCS)
 JTAG Configuration Port
 Leg
 Cyclone III (EP3C25E144C7)
 DDR SDRAM (512 MBit)
 Ports for GPIO
Hardware Details
 I/O Widgets
 8 Directional Joystick
 RGB LEDs
 Communication Methods
 Memory – DDR SSTL_2
 Inter FPGA - LVDS
Hardware Power
Computer
Power Supply
3.3V
1.2V Linear
Regulators
5V
3.3V Linear
Regulator
2.5V Linear
Regulators
VCCINT
EPCS/Buffers
VCCIO/RAM
VDD
VCCD
DAC
VCCA
Clocks
12V
1.25V Linear
Regulators
VREF/VTT
LEDs
Fans
Cost Estimate
Expenses
Unit Cost
Quantity
Extended
Lobster
Leg FPGA
$
60
2
$
120
Abdomen FPGA
$
30
1
$
30
Memory
$
6
2
$
12
Discrete
$
50
1
$
50
Power
$
77
1
$
77
I/O
$
40
1
$
40
Board
$
70
1
$
70
$
399
Total
Both Revisions
$ 798
Crab
Leg FPGA
$
60
4
$
240
Abdomen FPGA
$
30
1
$
30
Memory
$
6
4
$
24
Discrete
$
70
1
$
70
Power
$
109
1
$
109
I/O
$
50
1
$
50
$
200
1
$
200
Board
Total
723
$ 723
Total Costs
$1,521
Schematics?
Layout?
DAVID HOVER
Software
 User Application Software
 Main User Interface
 Benchmarks
 Demos
 Tetrisphere Clone
 Graphics Pipeline Software
 Assembler
Main Menu
See attached 
Benchmarks & Demos
 Benchmarks
 Matrix Multiplications
 Matrix-Vector Multiplications
 Transcendental Function Calculation
 Demos
 Racecar
 Bouncing Blob
 Buffalo
 Beach
Software Implementation
 “Game Loop”
 Poll User Input
 Update “Game” State
 Redraw Environment
 OpenDC API
 Similar To OpenGL
 Smaller Subset
Example OpenDC Functions
 State Manipulation
 dcEnable()
 dcClear()
 dcFinish()
 Matrix Manipulation
 dcMatrixMode()
 dcLoadIdentity()
 Parameter Manipulation
 dcBindShader()
 dcBindTexture()
 dcUniform1f()
General Software Layout
Graphics Pipeline Software
 Hardware to
Software
Abstraction
The Assembler - Flex




Matches expressions
Literal or regular expressions
Can perform any action after a match
The main task is to turn matches into tokens for
the upcoming parser
Flex (Cont.)
Our Lexer has the following properties

Matches all valid assembly commands

Allows for comments, i.e, anything after a semicolon is
ignored

Ignores all white space

Is able to distinguish between arguments and labels.
The Assembler – Bison
 Invoked after the lexer
 Sends tokens through an annotated context-free
grammar.
 A context-free grammar, for example, has the form of:
stmts : stmt stmts
| stmt
;
 This is one of many definitions.
 This stores data as it parses
Bison (Cont.)
The parser is general, all commands are treated
equally
 Validity is checked per completed command
 After completion, the parser passes the finished data
to be converted into a bitstream
JONATHAN TATE
System Logic Design
 Prebuilt
 SOPC Builder
 Memory Controllers
 NIOS II Processor
 Custom
 Caches
 LVDS to Avalon Interconnect Bridge
 Shader Unit
Shader ALU
Shader Unit
Leg Shader Block
Shader Thread Scheduling
Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Thread 1
x
Thread 2
x
Thread 3
x
Thread 4
x
Thread 1
y
Thread 2
y
Thread 3
y
Thread 4
y
Thread 1
z
Thread 2
z
Thread 3
z
Thread 4
z
Thread 1
x
Shader Thread Scheduling
Cycle
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
0 1 2 3 4 5 6 7 8
Thread 1
x
Thread 2
x
Thread 3
x
Thread 4
x
Thread 1
y
Thread 2
y
Thread 3
y
Thread 4
y
Thread 1
z
Thread 2
z
Thread 3
z
Thread 4
z
Thread 1 w
Thread 2 w
Thread 3 w
Thread 4 w
Thread 1
x
PAUL NIEWOONDER
Arithmetic – Multiply-Add
Multiply Unit
Arithmetic – Multiply-Add
Add Unit
Arithmetic – Inverse Square Root
float InvSqrt(float x)
{
float xhalf = 0.5f * x;
int i = *(int*)&x;
i = 0x5f3759d5 - (i >> 1);
x = *(float*)&i;
x = x*(1.5f - xhalf*x*x);
return x;
}
Arithmetic – Divider
 Chained subtract and bit shift
 Requires many LUTs
 Full divide support would take up most of the available
board space
 Limited divide support (1 divide per sixteen cycles)
Case Design
 Plexiglas substrate
 Ventilation holes
 Fan mount
 Joystick control mount
 VGA output port
Schedule
Milestone Deliverables
 Milestone 1
 Revision 1 of Lobster FPGA Board
 Iteration 1 of the Software
 Milestone 2
 Lobster FPGA Board
 Iteration 3 of the Software
 All Logic
 Capstone Expo
 Crab FPGA Board
Division of Labor
 Jonathan Tate
 System Logic Design
 Shader Programs
 Graphics Pipeline
Control Software
 David Hover
 Assembler
 User Application
Software
 Robert Benson
 Board Design
 User Application
Software
 Graphics Pipeline
Control Software
 Paul Niewoonder
 Arithmetic Logic Design
 Case
QUESTIONS?