Team 3D
Erik Lorhammer
Christopher Bermel
Josh Cornelius
Electrical Computer Engineering
Electrical Engineer
Electrical Engineer
Objectives

3D Volumetric Display

System loads pictures from an SD card to
DDR SDRAM and sends pictures to a
projector in a specified order over a VGA
interface

Project images onto a screen rotating at
600rpm, the rotation of this screen
produces a 3D image

Desired image is 3D CU logo in two colors
Optical
Encoder
Power
3.3V
Buttons
Laptop
Nios II
Soft Core-F
VGA
Controller
SD Card
1GB
SDRAM
256 MB
SRAM
Frame
Buffer
Projector
Optical
Lense
Mechanical
System

Altera Cyclone II FPGA
 Development:
▪ DE2 Board with EP2C35F672C6N Cyclone II
▪ 33216 LE’s
 Implementation:
▪ Sparkfun Breakout Board with EP2C8Q208C8N Cyclone II
▪ Less Memory Available On-Chip
 SDRAM will contain all storage and program information so not a big concern.
▪ One-Fifth Logic Elements (8256 LE’s)
 Make sure that design fits within this constraint while working on DE2 board.
▪ Program via Jtag interface
▪ Elements being programmed in Verilog
 Running at 100 MHz, initial Fmax results from Quartus II show
critical path Fmax to be ~167MHz so have some headroom if
frame rate is not adequate.

SDRAM
 Micron - MT46V32M8P-6T:G TR
▪ 256MB DDR SDRAM

SRAM
 Acts as Frame Buffer
 At least 1MB to store two images
▪ One image is ~300KB, want to have two buffers in order to simultaneously put a
new image into buffer while reading the older one
 Recent Decision so part has not been selected yet

SD-Card
 Kingston 1GB Card
▪ Will allow for up to four different image sets to be on SD-Card for easy changing
of 3D image without going back to laptop
 Pre-defined software package takes care of bus interactions and all
required communications.

VGA
 640 x 480 at 8-bits Color
▪ Images are stored in frame buffer in SRAM
▪ Full image sets are stored in SDRAM
 Mega Function provided by Altera University Program.
▪ 640 x 480 at 10-bits Color (still researching 10-bits
▪ May not be adequate for our needs backup is designing our own VGA
Controller

Optical Encoder
 CUI Inc. High Resolution Encoder
▪ Keeps control board up to date on mirror location
▪ Will allow synchronization of frame output every 360 degrees (~24
frames)

Code in C / C++ using Nios II IDE (eclipse)
 Included debug tools
▪ Access to registers
▪ Stepping through program

Program LED as additional debugging tools
 LEDs light at certain points in code, after certain actions have been
completed

Quartus II Software
 Tools to get accurate timing between elements

Test Functionality at each step
 Each Component can be individually tested
▪
▪
▪
▪
SDRAM proper timing
Moving images from SD-Card to SDRAM
Outputting a single picture on VGA
Proper implementation of Frame Buffer on SRAM
Projection
Screen
Power
12V
Motor
Ball Bearing
Mirrors
Steel Turntable
 12.06” outer diameter
 6.33” inner diameter
 HDPE Ring and Polycarbonate Arches
 Bolted to steel turntable
 Holds projection screen in place
 Mirrors are mounted to the ring


Friction Drive
 Motor spins small wheel that drives large ring

Projector
 Standard DLP projector borrowed from department

Custom focusing lens
 Allows for large projection image to be focused on a
small screen at a short distance
 Designed with help from Professor McLeod

Mirrors
 Three mirrors for image transmission

Translucent Screen
 1/8” Acrylic sheet
D
N
G
D
N
G
D
N
G
F
p
0
0
7
2
0.01uF
0
6
1
4
5
S
P
T
C10
90.9K
61.9K
1
D
N
G
LED0
7
C
1
76.8k
6.8pF
2
D
7
R
3
R
Pad
Thermal
K
0
1
4
R
8
C
K
2
3
3
0.1uF
2.2uF
2.2uF
PWRGD
RT/CLK
D
N
G
6
5
VSENSE
SS/TR
7
4
6
R
2
R
4
C
5
C
6
C
COMP
N
E
8
3
D
N
G
VIN
9
2
31.6K
H
P
T
O
O
B
0
1
1
47uF/6.3V
1
6
1
4
5
S
P
T
5
R
B220A
V
2
1
1
D
9
C
0.1uF
H
u
0
1
C11
3.3V
1
L
D
N
G
D
N
G
Female
AC
Plug
D
N
G
1
6.12K
0.1pF
0.1pF
F
p
0
7
4
Reg
Volt
3
2
1
R
3
C
2
C
1
C
D
N
G
Bridge1
Vout
Vin
DFB
V
2
1
V
2
1
EP2C8Q208C8N
LVDS57n
IO,
3
0
1
4
0
1
LVDS57p
IO,
LVDS58n
IO,
2
0
1
DQ0B0/DQ1B0
LVDS58p,
IO,
1
0
1
DQ0B1/DQ1B1
LVDS59n,
IO,
9
9
DQ0B2/DQ1B2
LVDS59p,
IO,
7
9
DQ0B3/DQ1B3
IO,
6
9
LVDS60n
IO,
5
9
(DPCLK4/DQS0B)/(DPCLK4/DQS0B)
LVDS60p,
IO,
4
9
DQ0B4/DQ1B4
LVDS61n,
IO,
EP2C8Q208C8N
2
9
DQ0B5/DQ1B5
LVDS61p,
IO,
EP2C8Q208C8N
0
9
nSTATUS
VREFB4N0
IO,
1
2
1
9
8
VCCA_PLL1
nCONFIG
DQ0B6/DQ1B6
LVDS62n,
IO,
6
2
8
8
VCCD_PLL1
CONF_DONE
DQ0B7/DQ1B7
LVDS62p,
IO,
3
2
1
7
8
VCCA_PLL2
DCLK
_/DQ1B8
LVDS63n,
IO,
1
2
6
8
VCCD_PLL2
DM0B/(DM1B0/BWS#1B0)
LVDS63p,
IO,
4
8
VCCIO4
nCE
LVDS64n
IO,
2
2
2
8
VCCIO3
LVDS64p
IO,
EP2C8Q208C8N
1
8
VCCIO2
MSEL1
O
I
5
2
1
0
8
INPUT
LVDSCLK0p
CLK0,
VCCIO1
MSEL0
LVDS66n
IO,
INPUT
LVDSCLK0n
CLK1,
4
2
3
VCCINT
6
7
2
6
2
1
7
7
LVDS66p
IO,
INPUT
LVDSCLK1p
CLK2,
D
N
G
DATA0
LVDS67n
IO,
7
2
0
2
5
7
INPUT
LVDSCLK1n
CLK3,
DQ1B0/DQ1B9
LVDS67p,
IO,
8
2
U?J
4
7
INPUT
LVDSCLK2p
CLK4,
TMS
DQ1B1/DQ1B10
LVDS68n,
IO,
2
3
1
7
1
2
7
INPUT
LVDSCLK2n
CLK5,
TCK
DQ1B2/DQ1B11
LVDS68p,
IO,
1
3
1
8
1
0
7
INPUT
LVDSCLK3p
CLK6,
TDO
DQ1B3/DQ1B12
LVDS70n,
IO,
0
3
1
6
1
9
6
INPUT
LVDSCLK3n
CLK7,
TDI
DQ1B4/DQ1B13
LVDS70p,
IO,
9
2
1
9
1
8
6
VREFB4N1
IO,
U?I
U?E
7
6
LVDS74n
IO,
4
6
(DPCLK2/DQS1B)/(DPCLK2/DQS1B)
LVDS74p,
IO,
EP2C8Q208C8N
3
6
4
BANK
DQ1B5/DQ1B14
LVDS75n,
IO,
1
6
LVDS16n
IO,
DQ1B6/DQ1B15
LVDS75p,
IO,
7
0
2
8
0
(DM1T/BWS#1T)/(DM1T1/BWS#1T1)
LVDS16p,
IO,
9
5
2
0
6
DQ1B7/DQ1B16
LVDS76n,
IO,
(DEV_CLRn)
LVDS17n
IO,
DQ1B8/DQ1B17
LVDS76p,
IO,
EP2C8Q208C8N
6
0
2
8
5
DQ1T8/DQ1T17
LVDS17p,
IO,
(DM1B/BWS#1B)/(DM1B1/BWS#1B1)
LVDS77p,
IO,
5
0
2
7
5
PLL2_OUTn
IO,
DQ1T7/DQ1T16
LVDS18p,
IO,
(DEV_OE)
LVDS77n
IO,
1
5
1
2
1
0
2
5
PLL2_OUTp
IO,
DQ1T6/DQ1T15
LVDS18n,
IO,
1
3
0
2
6
5
EP2C8Q208C8N
U?D
LVDS38p
IO,
(DPCLK10/DQS1T)/(DPCLK10/DQS1T)
LVDS19p,
IO,
0
5
1
0
0
2
LVDS38n
IO,
LVDS19n
IO,
PLL1_OUTn
IO,
9
4
1
9
9
1
DQ0R0/DQ1R0
LVDS39p,
IO,
7
4
1
8
9
1
8
LVDS21p
7
4
4
IO,
PLL1_OUTp
IO,
DQ0R1/DQ1R1
LVDS39n,
IO,
LVDS21n
IO,
6
4
1
7
9
1
6
DQ1T5/DQ1T14
LVDS23p,
IO,
VREFB3N0
IO,
5
4
1
5
9
1
5
DQ1T4/DQ1T13
LVDS23n,
IO,
DQ0R2/DQ1R2
LVDS42p,
IO,
4
4
1
3
9
1
4
DQ0R3/DQ1R3
LVDS42n,
IO,
VREFB2N1
IO,
O
I
4
O
4
LVDS0p
IO,
I
4
LVDS0n
IO,
3
4
1
2
9
1
3
4
DQ0R4/DQ1R4
LVDS44p,
IO,
DQ1T3/DQ1T12
LVDS24p,
IO,
(DM1L/BWS#1L)/_
LVDS2n,
IO,
2
4
1
1
9
1
1
4
DQ0R5/DQ1R5
LVDS44n,
IO,
DQ1T2/DQ1T11
LVDS24n,
IO,
DQ1L8/_
LVDS2p,
IO,
1
4
1
9
8
1
0
4
DQ0R6/DQ1R6
LVDS45p,
IO,
DQ1T1/DQ1T10
LVDS25p,
IO,
DQ1L7/_
LVDS3n,
IO,
9
3
1
8
8
1
9
3
DQ0R7/DQ1R7
LVDS45n,
IO,
LVDS25n
IO,
VREFB1N1
IO,
8
3
1
7
8
1
7
3
_/DQ1R8
LVDS46p,
IO,
DQ1T0/DQ1T9
LVDS26p,
IO,
DQ1L6/_
LVDS5p,
IO,
7
3
1
5
8
1
5
3
DM0R/(DM1R0/BWS#1R0)
LVDS46n,
IO,
LVDS28p
IO,
DQ1L5/_
IO,
5
3
1
2
8
1
4
3
(DPCLK7/DQS0R)/(DPCLK7/DQS0R)
LVDS47p,
IO,
LVDS28n
IO,
DQ1L4/_
LVDS6n,
IO,
4
3
1
1
8
1
3
3
DQ1R0/DQ1R9
LVDS47n,
IO,
LVDS29p
IO,
LVDS7n
IO,
3
3
1
0
8
1
1
3
(DPCLK6/DQS1R)/(DPCLK6/DQS1R)
LVDS48p,
IO,
DM0T/(DM1T0/BWS#1T0)
LVDS29n,
IO,
(DPCLK1/DQS1L)/(DPCLK1/DQS1L)
LVDS7p,
IO,
8
2
1
9
7
1
0
3
DQ1R1/DQ1R10
LVDS48n,
IO,
_/DQ1T8
LVDS31p,
IO,
LVDS8n
IO,
7
2
1
6
7
1
5
1
DQ1R2/DQ1R11
IO,
DQ0T7/DQ1T7
LVDS31n,
IO,
(DPCLK0/DQS0L)/(DPCLK0/DQS0L)
LVDS8p,
IO,
8
1
1
5
7
1
4
1
VREFB3N1
IO,
DQ0T6/DQ1T6
LVDS33p,
IO,
VREFB1N0
IO,
7
1
1
3
7
1
3
1
DQ1R3/DQ1R12
LVDS51p,
IO,
DQ0T5/DQ1T5
LVDS33n,
IO,
DQ1L3/_
LVDS12n,
IO,
6
1
1
1
7
1
2
1
DQ1R4/DQ1R13
LVDS51n,
IO,
VREFB2N0
IO,
DQ1L2/_
LVDS12p,
IO,
5
1
1
0
7
1
1
1
DQ1R5/DQ1R14
LVDS52p,
IO,
(DPCLK8/DQS0T)/(DPCLK8/DQS0T)
LVDS34p,
IO,
DQ1L1/_
LVDS13n,
IO,
4
1
1
9
6
1
0
1
DQ1R6/DQ1R15
LVDS52n,
IO,
LVDS34n
IO,
DQ1L0/_
LVDS13p,
IO,
3
1
1
8
6
1
8
3
BANK
2
BANK
1
BANK
DQ1R7/DQ1R16
LVDS53p,
IO,
DQ0T4/DQ1T4
LVDS35p,
IO,
LVDS14n
IO,
2
1
1
5
6
1
6
DQ1R8/DQ1R17
LVDS53n,
IO,
DQ0T3/DQ1T3
LVDS35n,
IO,
LVDS14p
IO,
0
1
1
4
6
1
5
(nCEO)
LVDS54p
IO,
DQ0T2/DQ1T2
LVDS36p,
IO,
(CLKUSR)
LVDS15n
IO,
8
0
1
3
6
1
4
(INIT_DONE)
LVDS54n
IO,
DQ0T1/DQ1T1
LVDS36n,
IO,
(CRC_ERROR)
LVDS15p
IO,
7
0
1
2
6
1
3
(DM1R/BWS#1R)/(DM1R1/BWS#1R1)
LVDS56p,
IO,
DQ0T0/DQ1T0
LVDS37p,
IO,
(nCSO)
IO,
6
0
1
1
6
1
2
LVDS56n
IO,
LVDS37n
IO,
(ASDO)
IO,
5
0
1
0
6
1
1
U?C
U?B
U?A
SD1
3
5
3
3
4
4
3
5
3
2
3
3
3
2
3
3
3
6
3
1
3
6
3
1
3
7
3
0
3
7
3
0
3
8
2
9
3
8
2
9
3
9
2
8
3
9
2
8
4
0
2
7
4
0
2
7
4
1
2
6
4
1
2
6
4
2
2
5
4
2
2
5
4
3
2
4
4
3
2
4
4
4
2
3
4
4
2
3
4
5
2
2
4
5
2
2
4
6
2
1
4
6
2
1
4
7
2
0
4
7
2
0
4
8
1
9
4
8
1
9
4
9
1
8
4
9
1
8
5
0
1
7
5
0
1
7
5
1
1
6
5
1
1
6
5
2
1
5
5
2
1
5
5
3
1
4
5
3
1
4
5
4
1
3
5
4
1
3
5
5
1
2
5
5
1
2
5
6
1
1
5
6
1
1
5
7
1
0
5
7
1
0
5
8
9
5
8
9
5
9
8
5
9
8
6
0
7
6
0
7
6
1
6
6
1
6
6
2
5
6
2
5
6
3
4
6
3
4
6
4
3
6
4
3
6
5
2
6
5
2
6
6
1
6
6
1
MT46V64M4
EP2C8Q208C8N
nSTATUS
1
2
1
nCONFIG
D
N
G
D
N
G
6
2
VGA
HD15
CONF_DONE
3
2
1
DCLK
1
2
Vsync
Bit3
Monitor
ID
4
1
4
5
0
C
N
1
5
1
nCE
2
2
9
MSEL1
5
2
1
Hsync
3
1
3
MSEL0
6
2
1
8
Bit1
ID
Monitor
2
1
2
DATA0
0
2
7
Bit0
ID
Monitor
1
1
1
TMS
6
7
1
TCK
8
1
?
J
TDO
6
1
TDI
9
1
U1E
Out
Red
Out
Green
Out
Blue
Connector
SD
EP2C8Q208C8N
D
C
INPUT
LVDSCLK0p
CLK0,
D
C
INPUT
LVDSCLK0n
CLK1,
4
2
3
M
O
C
2
VSS
P
W
P
W
VSS
SCLK
INPUT
LVDSCLK1p
CLK2,
6
5
7
2
VSS
O
D
INPUT
LVDSCLK1n
CLK3,
3
7
8
2
I
D
INPUT
LVDSCLK2p
CLK4,
2
2
3
1
D
D
V
S
C
INPUT
LVDSCLK2n
CLK5,
4
1
1
3
1
INPUT
LVDSCLK3p
CLK6,
3.3V
1
J
0
3
1
INPUT
LVDSCLK3n
CLK7,
9
2
1
U1I
MH2
2
103
101
99
97
95
93
91
89
87
85
83
81
79
77
75
73
71
69
67
65
63
61
59
57
55
53
104
102
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
58
56
54
105
106
52
51
107
108
50
49
109
110
48
47
111
112
46
45
113
114
44
43
115
116
42
41
117
118
40
39
119
120
38
37
121
122
36
35
123
124
34
33
125
126
32
31
127
128
30
29
129
130
28
27
131
132
26
25
133
134
24
23
135
136
22
21
137
138
20
19
139
140
18
17
141
142
16
15
143
144
14
13
145
146
12
11
147
148
10
9
149
150
8
7
151
152
6
5
153
154
4
3
155
156
2
1
3
10a
1
9a
8a
16
7a
6a
5a
MH1
15
4a
5
10
14
3a
4
9
13
2a
3
8
12
1a
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
2
7
208
11
2
1
6
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
1
17
WP
COM
CD
1
2
2
1
1
2
2
1
1
8
7
2
2
2
2
2
2
2
2
1
1
1
1
1
1
6
5
4
2
1
1
1
1
2
2
3
3
2
2
2
3
2
1
4
1
3
1
2
2
1
9
11
1
2
1
1

Control Board fully realized
 All components placed in Quartus II and verification testing
beginning
▪ Testing:
▪
▪
▪
▪
SD-Card properly initialized by board
SD-Card transferring images to SDRAM
SDRAM transferring images to SRAM Frame Buffer
VGA Controller taking images from SRAM Frame Buffer and outputting to
projector
▪ Projector image clear and crisp


First PCB revision
Mechanical system built and under test
 Screen rotating at 600 RPM
 Mirror defined
 Lens ordered

Control Board finished and tested
 Fully implemented on PCB Schematics
▪ Second PCB revision ordered and delivered
 Secondary objectives in Design and Test
▪ LCD panel status screen
▪ Other “Cool Ideas” not yet thought of

Second PCB revision ordered
 Full knowledge if third revision needed
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Mechanical system only needs a few tweaks
Simple 3D image is displayed (Red Ball)

Chris
 Printed Circuit Board
 Mechanical System

Erik
 VGA Interface
 NIOS II System
 Memory Interfaces

Josh
 SD Interface
 Optics
 Image Processing