Pyxis
Aaron Martin
April Lewis
Steve Sherk
Pyxis1600
General-purpose 16-bit RISC
microprocessor
 16 16-bit registers
 24-bit address bus
 Up to 16MB of addressable memory

September 5, 2005
Pyxis1600
2
Registers


16 registers
3 special purpose
– $r0 – zero
– $r14 – stack pointer
– $r15 – return address

13 general purpose
– $r1 - $r13

Status register (sr)
– 8 bits – carry (c), overflow (o), negative (n), zero (z), interrupt
enable (i), less than (l), 2 bits unused


Program counter (pc)
Accumulator high (ah) and accumulator low (al)
– Used for multiply and divide

Page register (pr)
– Sets the high order 8 bits in the 24-bit address space
September 5, 2005
Pyxis1600
3
Instruction Formats
15
R-type
opcode
98 7
ext
43
rd
15
0
rs
0
Displacement / Immediate
B-type






15
13 12
98
opcode branch type
0
address
16-bit instructions
7-bit opcode
1 bit to indicate information in next word
rd is source and target
rs is source
Branch instructions use special format
September 5, 2005
Pyxis1600
4
Instruction Set
Category
Arithmetic
Data Transfers
September 5, 2005
Instruction
add
add immediate
subtract
subtract immediate
divide
divide immediate
multiply
multiply immediate
move from al
move from ah
load word
store word
load byte
store byte
load page register
Example
add <rd>,<rs>
add <rd>, #100
sub <rd>, <rs>
subi <rd>, #200
div <rd>, <rs>
divi <rd>, #4
mult <rd>, <rs>
multi <rd>, #6
mal <rd>
mah <rd>
lw <rd>, 100(<rs>)
sw 200(<rd>), <rs>
lb <rd>, 100(<rs>)
sb 200(<rd>), <rs>
lpr #100
Pyxis1600
Meaning
r3 = r3 + r4
r3 = r3 + 100
r3 = r3 - r4
r3 = r3 - 200
<ah, al> = r3 / r4
<ah, al> = r3 / 4
<ah, al> = r3 * r4
<ah, al> = r3 * 6
r4 = (al)
r4 = (ah)
r3 = Memory[r4 + 100]
Memory[r3 + 200] = r4
r3[7:0] = Memory[r4 + 100]
Memory[r3 + 200] = r4[7:0]
pr = 100
5
Instruction Set
Category
Logical
Conditional
Branch
Unconditional
Branch
Other
Instruction
and
andi
or
ori
nor
nori
comp
shl
shr
beq
bne
blt
bgt
jmp
jmpl
jmpr
no operation
September 5, 2005
Example
and <rd>, <rs>
andi <rd>, #4
or <rd>, <rs>
ori <rd>, #4
nor <rd>, <rs>
nori <rd>, #4
comp <rd>, <rs>
shl <rd>, #10
shr <rd>, #10
beq #100
bne #100
blt #100
bgt #100
jmp #2500
jmpl #2500
jmpr <rd>
nop
Pyxis1600
Meaning
r3 = r3 & r4
r3 = r3 & 4
r3 = r3 | r4
r3 = r3 | 4
r3 = ~(r3 | r4)
r3 = ~(r3 | 4)
set sr bits after compare
r3 = r3 << 10
r3 = r3 >> 10
if sr[z] = 1, go to PC + 100
if sr[z] = 0, go to PC + 100
if sr[l] = 1, go to PC + 100
if sr[l] = 0, go to PC + 100
go to 2500
r15 = PC + 2, go to 2500
go to r4
stall for one clock cycle
6
Addressing Modes
Register direct
 Register indirect plus displacement

– Use r0 for absolute addressing
PC-relative
 Immediate

September 5, 2005
Pyxis1600
7
Interrupts

Options for handling interrupts
– Handled by hardware
• Each interface wired to its own pin
– Handled by software
• Use interrupt vector that points to different
routines
• Have separate priority level for each interface
• All interrupts go to same routine that polls each
device to see which one caused the interrupt
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8
Block Diagram
Major Components
Control
Instruction
[15:8]
PC
Memory
Instruction
[7:4]
Read / Write
Register
Instruction
[3:0]
Read
Register
Instruction
Register
15
OpCode
September 5, 2005
ALU
Registers
8 7
4 3
Dest. Reg
Pyxis1600
0
Source Reg
9
Sub-systems

Internal to the microprocessor
– Fetch and Memory access logic
• addressing modes
– ALU
• add, sub, mult, div, memory access calculations
(PC+offset)
– Control logic
• micro instructions, control signal labels
– Register implementation

External
– Serial bus implementation
• hardware associated with serial port
September 5, 2005
Pyxis1600
10
Assembler


Converts assembly code into machine language
Uses a look-up table to find machine code for each
instruction
– Some instruction are “psudo-instructions” implemented with
other, lower level instructions

Written in Perl and implemented on a PC
– Perl is good for parsing and string manipulation

Machine code saved on EPROM and loaded onto
microprocessor
– .asm  .HEX  EPROM burning software
September 5, 2005
Pyxis1600
11
Hardware
XCV300 FPGA
- 322,970 logic gates
- 8 KB on-chip RAM
 128KB off-chip SRAM
 128KB off- chip EPROM

September 5, 2005
Pyxis1600
12
Input / Output Devices
Serial RS232 port
 Monitor / LCD
 Keyboard / Keypad
 USB port

September 5, 2005
Pyxis1600
13
Feature Priority

General-purpose processor
– Multi-cycle design
– Complete reduced instruction set
– Some test code, Game, or Benchmark Program






Assembler
On-chip hardware divider
C compiler
Floating-point unit
L1 data and instruction cache
5 stage pipeline design
September 5, 2005
Pyxis1600
14
Roles and Responsibilities

Aaron
– Logic design
– Verilog programming

April
– Assembler
– Software interfaces

Steve
– Hardware components
– Hardware interfaces

All
– Integration and Test
– Documentation
September 5, 2005
Pyxis1600
15
Schedule
ID Task Name
1 Project Definitiion
Duration
Start
1 wk Mon 8/29/05
Aug 28, '0 5
Sep 4, '05
Sep 11, '0 5
Sep 18, '0 5
Sep 25, '0 5
Oct 2, '05
Oct 9, '05
Oct 16, '0 5
Oct 23, '0 5
Oct 30, '0 5
Nov 6, '05
Nov 13, '05
Nov 20, '05
Nov 27, '05
Dec 4, '05
Finish S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F S S M T W T F
Fri 9/2/05
All
2 Preliminary Design Review
1 day
Thu 9/8/05
Thu 9/8/05
3 Function Definition
1 wk Wed 8/31/05
Tue 9/6/05
4 Hardware Definition
3 days
5
Part Selection
3 days
Thu 9/8/05 Mon 9/12/05
6 Software Definition
5 days
Thu 9/8/05 Wed 9/14/05
1 wk
Thu 9/8/05 Wed 9/14/05
7
Language Choice
8 Hardware Design
Thu 9/8/05 Mon 9/12/05
All
All
10 days Thu 9/15/05 Wed 9/28/05
9
Layout
1 wk
Thu 9/15/05 Wed 9/21/05
10
Hardware Test
1 wk
Thu 9/22/05 Wed 9/28/05
11 Software Design
15 days Thu 9/15/05 Wed 10/5/05
12
15 days Thu 9/15/05 Wed 10/5/05
Logic Design
9/8
All
Steve
Steve
13
State diagrams
1 wk
Thu 9/15/05 Wed 9/21/05
14
ALU
1 wk
Thu 9/22/05 Wed 9/28/05
April
15
Decoder
1 wk
Thu 9/22/05 Wed 9/28/05
Steve
16
Controller
2 wks
Thu 9/22/05 Wed 10/5/05
Aaron
All
17
Logic Test
1 wk
Thu 9/29/05 Wed 10/5/05
Aaron
18
Assembler
2 wks
Thu 9/22/05 Wed 10/5/05
April
1 day Thu 10/6/05 Thu 10/6/05
10/6
19 Critical Design Review
20 Integration
26 days Wed 9/21/05 Wed 10/26/05
21
Software Interfaces
1 wk Wed 10/5/05 Tue 10/11/05
April
22
Hardware Interfaces
1 wk Wed 10/5/05 Tue 10/11/05
Steve
23
SW / HW Interfaces
26 days Wed 9/21/05 Wed 10/26/05
Aaron
1 day Thu 10/27/05 Thu 10/27/05
10/27
24 Milestone 1
25 Test Programs
10 days Thu 10/27/05 Wed 11/9/05
26
Benchmark
2 wks Thu 10/27/05 Wed 11/9/05
Aaron
27
Game1
2 wks Thu 10/27/05 Wed 11/9/05
April
28
Game2
2 wks Thu 10/27/05 Wed 11/9/05
Steve
29 Milestone 2
1 day Thu 11/17/05 Thu 11/17/05
30 System Test
3 wks Thu 11/17/05 Wed 12/7/05
31 Documentation
September 5, 2005
70 days
Thu 9/1/05 Wed 12/7/05
Pyxis1600
11/17
16
All
All
Risks and Contingency Plan
Risk
Resolution
Problems in logic design
Optional features will not be
implemented
Bad Parts
Several XCV300 chips are
available, other components
are inexpensive
Problems with hardware
interfaces
Several options exist (I.e. LCD
vs. monitor, RS232 vs. USB)
Problems with software
interfaces
Validate all software interfaces
early in schedule to allow time
to correct if necessary
September 5, 2005
Pyxis1600
17
Questions