Lecture 18
OUTLINE
• The MOS Capacitor (cont’d)
– Effect of oxide charges
– VT adjustment
– Poly-Si gate depletion effect
Reading: Pierret 18.2-18.3; Hu 5.7-5.9
Oxide Charges
In real MOS devices, there is always some charge within the
oxide and at the Si/oxide interface.
• Within the oxide:
– Trapped charge Qot
• High-energy electrons and/or
holes injected into oxide
– Mobile charge QM
• Alkali-metal ions, which have
sufficient mobility to drift in oxide
under an applied electric field
• At the interface:
– Fixed charge QF
• Excess Si (?)
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 18.4
– Trapped charge QIT
• Dangling bonds
EE130/230A Fall 2013
Lecture 18, Slide 2
Effect of Oxide Charges
• In general, charges in the oxide cause a shift in the
gate voltage required to reach threshold condition:
DVT  
xo
1
 SiO
2
 x
ox
( x)dx
0
(x is defined to be 0 at metal-oxide interface)
For example, positive charge in the oxide near to the p-type Si substrate
(for an NMOS device) helps to deplete the surface of holes, so that the
gate voltage that must be applied to invert the surface (to become ntype) is reduced, i.e. VT is reduced  DVT is negative.
• In addition, oxide charge can affect the field-effect
mobility of mobile carriers (in a MOSFET) due to
Coulombic scattering.
EE130/230A Fall 2013
Lecture 18, Slide 3
Fixed Oxide Charge, QF
M
3.1 eV
O
S
qQF / Cox
Ec= EFM
|qVFB |
Ev
Ec
EFS
Ev
4.8 eV
EE130/230A Fall 2013
Lecture 18, Slide 4
VFB   MS
QF

Cox
Parameter Extraction from C-V
From a single C-V measurement, we can extract much
information about the MOS device:
• Suppose we know the gate material is heavily doped n-type
poly-Si (FM= 4.1 eV), and the gate dielectric is SiO2 (r = 3.9):
1.
From Cmax = Cox we can determine oxide thickness xo
2.
From Cmin and Cox we can determine substrate doping (by iteration)
3.
From substrate doping and Cox we can find flat-band capacitance CFB
4.
From the C-V curve, we can find VFB  VG
5.
From FM, FS, Cox, and VFB we can determine Qf
EE130/230A Fall 2013
Lecture 18, Slide 5
C  C FB
Determination of FM and QF
Measure C-V characteristics of capacitors with different oxide
thicknesses. Plot VFB as a function of xo:
VFB  MS 
xo
 SiO
2
C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-21
EE130/230A Fall 2013
Lecture 18, Slide 6
QF
Mobile Oxide Charge, QM
Bias-Temperature Stress (BTS) Measurement
Na+ located at
lower SiO2 interface
 reduces VFB
DVFB
Na+ located at
upper SiO2 interface
 no effect on VFB
Positive oxide charge shifts the flatband voltage in the negative direction:
VFB
QF
1
 MS 

Cox  SiO2
QIT (S )
0 xox ( x)dx  Cox
xo
QM  Cox DVFB
EE130/230A Fall 2013
Lecture 19, Slide 7
R. F. Pierret, Semiconductor Device Fundamentals, p. 657
Interface Trap Charge, QIT
(c)
(b)
(a)
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 18.10
“Donor-like” traps are
charge-neutral when
filled, positively charged
when empty
(a)
Positive oxide charge
causes C-V curve to
shift toward left
(more shift as VG
decreases)
(b)
Traps cause “sloppy” C-V and also
greatly degrade mobility in channel
(c)
QIT (S )
DVG  
Cox
EE130/230A Fall 2013
Lecture 18, Slide 8
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 18.12
VT Adjustment
• In modern IC fabrication processes, the threshold voltages of
MOS transistors are adjusted by adding dopants to the Si by a
process called “ion implantation”:
– A relatively small dose NI (units: ions/cm2) of dopant atoms is
implanted into the near-surface region of the semiconductor
– When the MOS device is biased in depletion or inversion, the
implanted dopants add to (or substract from) the depletion charge
near the oxide-semiconductor interface.
qN I
DVT  
Cox
EE130/230A Fall 2013
N I  0 for donor atoms
N I  0 for acceptor atoms
Lecture 18, Slide 9
Poly-Si Gate Technology
• A heavily doped film of polycrystalline silicon (poly-Si) is often
employed as the gate-electrode material in MOS devices.
NMOS
PMOS
n+ poly-Si
p+ poly-Si
p-type Si
n-type Si
– There are practical limits to the electrically active dopant
concentration (usually less than 1x1020 cm-3)
 The gate must be considered as a semiconductor, rather than a metal
EE130/230A Fall 2013
Lecture 18, Slide 10
MOS Band Diagram w/ Gate Depletion
Si biased to inversion:
WT
Ec
qVpoly
qS
EFS
Ev
Qinv  Cox (VG  V poly  VT )
qVG
Ec
Ev
VG is effectively reduced:
W poly 
2 SiV poly
qN poly
Wpoly
n+ poly-Si gate
EE130/230A Fall 2013
How can gate depletion
be minimized?
p-type Si
Lecture 18, Slide 11
Gate Depletion Effect
Gauss’s Law dictates that Wpoly = oxEox / qNpoly
xo is effectively increased:
1
n+ poly-Si
Cpoly
+ + + + + + + +
Cox
N+
- - - - - - - - -
p-type Si
 xo
 1

W poly 
1


 
C 


C

  SiO

C

ox
poly
Si


2



 SiO
2
xo  (W poly / 3)
Qinv  (VG  VT ) 
EE130/230A Fall 2013
Lecture 18, Slide 12
 SiO
2
xo  (W poly / 3)
1
Example: Gate Depletion Effect
The voltage across a 2 nm oxide is Vox = 1 V. The active dopant
concentration within the n+ poly-Si gate is Npoly = 8 1019 cm-3
and the Si substrate doping concentration NA is 1017 cm-3.
Find (a) Wpoly , (b) Vpoly , and (c) VT .
Solution:
(a) Wpoly = oxEox / qNpoly = oxVox / xoqNpoly
3.9  8.85 10 14[F/cm] 1[V])

2 10 7 [cm] 1.6 10 19[C]  8  1019[cm -3 ]
 1.3  10 7 cm
EE130/230A Fall 2013
Lecture 18, Slide 13
(b)
W poly 
2 SiV poly
qN poly
2
Vpoly  qN polyWpoly
/ 2 Si  0.11 V
(c)
VT  VFB  2F  Vox  V poly
 EG kT  N A 
  0.98 V
VFB   

ln 
 2q q  ni 
VT  0.98 V  0.84 V  1 V  0.11 V  0.97 V
EE130/230A Fall 2013
Lecture 18, Slide 14
Inversion-Layer Thickness, Tinv
The average inversion-layer location below the Si/SiO2 interface
is called the inversion-layer thickness, Tinv .
C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-24
EE130/230A Fall 2013
Lecture 18, Slide 15
Effective Oxide Thickness, Toxe
Toxe
W poly
Tinv
 xo 

3
3
(VG + VT)/Toxe can be shown to be the average electric field in the inversion layer.
Tinv of holes is larger than that of electrons due to difference in effective masses.
EE130/230A Fall 2013
Lecture 18, Slide 16
C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-25
Effective Oxide Capacitance, Coxe
Toxe
W poly
Tinv
 xo 

3
3
VG
Qinv   Coxe (V  VT )dV
VT
EE130/230A Fall 2013
Lecture 18, Slide 17
C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 5-26