inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture 29 –
Combinational Logic Blocks
2004-04-05
Lecturer PSOE Dan Garcia
www.cs.berkeley.edu/~ddgarcia
USF “Flashmob 1” 
supercomputer effort!
On Sat, organizers tried to create a
supercomputer by harnessing 500
laptops together & run Linpack, a
speed benchmark. Didn’t work.
www.nytimes.com/2004/04/05/technology/05super.html
CS 61C L29 Combinational Logic Blocks (1)
Garcia, Spring 2004 © UCB
Review
• Use this table and techniques we
learned to transform from 1 to another
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Garcia, Spring 2004 © UCB
A.
Peer Instruction Correction
B.
N-input gates can be thought of cascaded 2-input
gates. I.e.,
(a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e))
where ∆ is one of AND, OR, XOR, NAND…TRUE
Let’s verify!
CORRECT 3-input
XYZ|AND|OR|XOR|NAND
000| 0 0|0 0| 0 0| 1 1
001| 0 0|1 1| 1 1| 1 1
010| 0 0|1 1| 1 1| 1 1
011| 0 0|1 1| 0 0| 1 1
100| 0 0|1 1| 1 1| 1 0
101| 0 0|1 1| 0 0| 1 0
110| 0 0|1 1| 0 0| 1 0
111| 1 1|1 1| 1 1| 0 1
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CORRECT 2-input
YZ|AND|OR|XOR|NAND
00| 0 |0 | 0 | 1
01| 0 |1 | 1 | 1
10| 0 |1 | 1 | 1
11| 1 |1 | 0 | 0
…it’s actually FALSE
Garcia, Spring 2004 © UCB
Today
• Data Multiplexors
• Arithmetic and Logic Unit
• Adder/Subtractor
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Data Multiplexor (here 2-to-1, n-bit-wide)
“mux”
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N instances of 1-bit-wide mux
How many rows in TT?
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How do we build a 1-bit-wide mux?
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4-to-1 Multiplexor?
How many rows in TT?
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Is there any other way to do it?
Hint: NCAA tourney!
Ans: Hierarchically!
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Administrivia
• HW4 grading done; deadline in 1 week.
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Arithmetic and Logic Unit
• Most processors contain a special
logic block called “Arithmetic and
Logic Unit” (ALU)
• We’ll show you an easy one that does
ADD, SUB, bitwise AND, bitwise OR
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Our simple ALU
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Adder/Subtracter Design -- how?
• Truth-table, then
determine canonical
form, then minimize
and implement as
we’ve seen before
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• Look at breaking the
problem down into
smaller pieces that
we can cascade or
hierarchically layer
Garcia, Spring 2004 © UCB
Adder/Subtracter – One-bit adder LSB…
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Garcia, Spring 2004 © UCB
Adder/Subtracter – One-bit adder (1/2)…
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Adder/Subtracter – One-bit adder (2/2)…
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N 1-bit adders  1 N-bit adder
+
+
+
What about overflow?
Overflow = cn?
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What about overflow?
• Consider a 2-bit signed # & overflow:
•10
•11
•00
•01
= -2 + -2 or -1
= -1 + -2 only
= 0 NOTHING!
= 1 + 1 only
±
#
• Highest adder
• C1 = Carry-in = Cin, C2 = Carry-out = Cout
• No Cout or Cin  NO overflow!
What • Cin, and Cout  NO overflow!
op?
• C , but no C  A,B both > 0, overflow!
in
out
• Cout, but no Cin  A,B both < 0, overflow!
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Garcia, Spring 2004 © UCB
Lecture ended on the previous slide
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What about overflow?
• Consider a 2-bit signed # & overflow:
10
11
00
01
= -2 + -2 or -1
= -1 + -2 only
= 0 NOTHING!
= 1 + 1 only
±
#
• Overflows when…
• Cin, but no Cout  A,B both > 0, overflow!
• Cout, but no Cin  A,B both < 0, overflow!
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Extremely Clever Subtractor
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Peer Instruction
A. Truth table for mux with 4-bits of
signals is 24 rows long
B. We could cascade N 1-bit shifters
to make 1 N-bit shifter for sll, srl
C. If 1-bit adder delay is T, the N-bit
adder delay would also be T
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1:
2:
3:
4:
5:
6:
7:
8:
ABC
FFF
FFT
FTF
FTT
TFF
TFT
TTF
TTT
Garcia, Spring 2004 © UCB
“And In conclusion…”
• Use muxes to select among input
• S input bits selects 2S inputs
• Each input can be n-bits wide, indep of S
• Implement muxes hierarchically
• ALU can be implemented using a mux
• Coupled with basic block elements
• N-bit adder-subtractor done using N 1bit adders with XOR gates on input
• XOR serves as conditional inverter
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Garcia, Spring 2004 © UCB