Wireless Metrology and
Process Control for
Semiconductor Manufacturing
Kameshwar Poolla
Mechanical Engineering
Electrical Engineering & CS
University of California, Berkeley
This research was supported
by NSF, UC SMART, & gifts
from Intel, AMD, Novellus,
Applied Materials, Cypress,
Lam Research, TEL, Nikon.
April 10, 2006
semiconductor
manufacturing
background
6/27/2016
2
What is it?
• Selective deposition &
selective removal of
various materials to form ICs
• Selectivity is done by protecting
desired areas with resist
IBM Power PC750
slide 3
6/27/2016
Lithography
• Expose
Post
Start
Spin-coat
Cr
Mask
Exposure
with
aResist
Si wafer
Bake
Develop
Etch
or
Deposit
slide 4
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Process Overview
Photomask
Scanner
PEB
PAB
Etch
Resist
Develop
PDB
Track
Production
Wafer Flow
slide 5
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Critical Dimension (CD)
• Captures quality of pattern transfer
• CD Target – desired width of printed lines
• CD(x,y) – actual width of printed lines
• Depends on (x,y)
because process varies across wafer
• Measured on test wafers
using CD SEM or Scatterometry
slide 6
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CD means μ and spreads σ
• Want CD Mean at Target
• small CD means  faster switching speeds
• CD spread
Across wafer & wafer-to-wafer
• small CD spread
 can use aggressive design rules
 higher device density
 better binning yields
slide 7
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Bad
Good
slide 8
6/27/2016
Binning
11nm
Typical CD
Distribution
Target CD
6nm
Post OnWafer
Optimization
Intel P4 Prices:
Device/Fab
Economics
Bin 1
Bin 2
Bin 3
3.8 GHz - $429
$
Yield
Yield
Improved Yield & Bin Sort = $$$
slide 9
6/27/2016
3.2 GHz - $336
2.8 GHz - $279
Post Exposure Bake
•
•
•
•
Key step – greatly influences CD μ and 
Makes exposed resist diffuse
To reduce standing wave patterns
Gives better pattern transfer
• Must be very accurately controlled
• State-of-the-art
±0.3 ºC across 300 mm wafer
slide 10
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PEB reduces Standing Waves
slide 11
6/27/2016
Courtesy of CNF, Cornell University
Our Plan ~1997
• Decided to do Control of Lithography
• Feedback Control requires
Sensors & Actuators
• Available Actuation?
Plenty – exposure dose, focal plane, PEB Temp
• Available Sensors in Lithography?
Not many and pretty useless for control
slide 12
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Need in situ Sensing
wafers to
be processed
processing
equipment
finished
wafer
What was the state of the wafer during processing?
slide 13
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in situ Sensing
• Need wafer-state information
–
–
–
–
Temperature in post-exposure bake
Latent image in lithographic exposure
Etch rate of wafer in plasma etch
Deposition rate in CVD processes
• The Big Problems
– Chamber access
– Deployment cost
slide 14
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Solution: SensorWafers
In-situ sensor array
with integrated
power and
telemetry
slide 15
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The Approach
processing
equipment
SensorWafer
data
feedback
process control
wafers to be processed
slide 16
6/27/2016
base station
Temperature Sensors
• Useful for PEB, plasma etch, implant
• Objectives
Monitor wafer temperature at 4 locations
(within 1ºC)
• Design
–
–
–
–
Off-the-shelf temperature sensor modules
PIC microprocessor (with integrated 4 channel A/D)
Infrared data transfer (IrDA compliant)
Error detection (CRC-16)
slide 17
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Early attempts …
Batteries
Batteries
P
P
Ir-LED
Sensor
Sensor
Ir-LED
Problems: clearance, isolation,
contamination & they are ugly !
slide 18
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Etch Rate Sensor
• Sensor to measure polysilicon etch rate
• Based on van der Pauw probe electrical filmthickness measurement:
I
I
Poly-Si
V
slide 19
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Design # 1
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The effect of Temperature
slide 21
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Results
Problems: clearance, isolation,
contamination
slide 22
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Thermal Flux Sensors
• Plasma etch is highly sensitive to wafer temp
etch rate, selectivity, and anisotropy
• Heat delivered to the wafer has two sources
– Ion flux bombardment
Indirect measure of physical etch
– Exothermic chemical etch reactions
Indirect measure of chemical etch
• Want to resolve these heat fluxes
– Can deduce sidewall, anisotropy etc.
slide 23
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Heat flux sensor design
• Simple, layered heat flux gauge
• Not enough sensitivity
Incident heat flux
(q )
t
T  t q
slide 24
6/27/2016
Temperature
Sensors
Dielectric, thermal
conductivity 
2m

1000W2  0.001C
m
1.38 W
mK


























Make the Heat Travel Far
Incident
heat flux
Antenna
slide 25
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Antenna
Base
Membrane
T
Antenna / Membrane Structure
Membrane
Top View
T
D
Heat flow
within thin
dielectric
membrane
T  4C
b
Heat
sink
slide 26
6/27/2016





2
D
T  q
ln D
8kw b
Incident
heat
Heat flow
T
Heat
sink
Membrane
Side View





Heat Flux Resolution
• Discrimination between
physical and chemical sources
• Use two heat flux sensors:
one exposed, one covered
– Exposed sensor is heated by both sources
– Covered sensor receives only physical heating
slide 27
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Design #1
•
•
•
•
•
Membrane: Silicon nitride
Antenna: SiO2 / Aluminum
Plasma-etched material: resist (O2 plasma)
Temperature sensors: polysilicon
Tethered power and communication
PR Al
SiO2
Heat sink
Heat sink
Si
slide 28
6/27/2016
poly
Si3N4
Layout – Wheatstone Bridge
Etched Sensor
slide 29
6/27/2016
Non-Etched
Non-Etched
Layout – Full Die (20 per wafer)
Sensors
Edgeboard
Connector
slide 30
6/27/2016
Design # 2
• Antenna: Undoped polysilicon (low )
• Linewidths: increased
• Tethered power and communication
PR
poly
Heat sink
Heat sink
Si
slide 31
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poly
Si3N4
Final Design
slide 32
6/27/2016
Testing
• Test sensors on the “bench”
– Use an off-the-shelf heat flux sensor and a heating element
to compare readings:
heater
sensor
off-the-shelf sensor
Aluminum
heat sink
vacuum chamber
slide 33
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Bench-top Results
slide 34
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Going up the food chain
• Sensors become rapidly commodified
• Value is in using the data
• This is through Control, Modeling, Optimization
• Examples
– Equipment Control
– Fault Detection and Isolation
– Process Optimization
slide 35
6/27/2016
The Value of Control
•
•
•
•
•
•
PEB Example
Control spatial temperature of bake plate
Yesterday ± 0.3 °C
Today
± 0.15 °C
Result: 1 nm reduction in CD spread
Benefit: mid-sized fab in 1st year of product lifecycle
~$3/die * 200 die/wafer * 20,000 wafer/mon * 12 mon/yr
• 144 M$ per year !!
slide 36
6/27/2016