Lecture #40: Review of circuit concepts • This week we will be reviewing the material learned during the course • Today: review – passive devices – circuit concepts – Load lines – RC transients 12/6/2004 EE 42 fall 2004 lecture 40 1 BRANCHES AND NODES Circuit with several branches connected at a node: branch (circuit element) i2 i1 i3 i4 KIRCHOFF’s CURRENT LAW (Sum of currents entering node) (Sum of currents leaving node) = 0 q = charge stored at node is zero. If charge is stored, for example in a capacitor, then the capacitor is a branch and the charge is stored there NOT at the node. 12/6/2004 EE 42 fall 2004 lecture 40 2 GENERALIZATION OF KCL TO SURFACES Sum of currents entering and leaving any “black box” is zero Could be a big chunk of circuit in here, e.g., could be a “Black Box” In other words there can be lots of nodes and branches inside the box. 12/6/2004 EE 42 fall 2004 lecture 40 3 KIRCHHOFF’S CURRENT LAW USING SURFACES Example surface 5 A 2 A i entering 5 A 2 A i=? leaving Another example 50 mA i=7A i? i must be 50 mA 12/6/2004 EE 42 fall 2004 lecture 40 4 BRANCH AND NODE VOLTAGES The voltage across a circuit element is defined as the difference between the node voltages at its terminals a v1 + v2 vd va v2 + c b e d v e 0 (since it’s the select as ref. reference) “ground” Specifying node voltages: Use one node as the implicit reference (the “common” node … attach special symbol to label it) Now single subscripts can label voltages: e.g., vb means vb ve, va means va ve, etc. 12/6/2004 EE 42 fall 2004 lecture 40 5 KIRCHHOFF’S VOLTAGE LAW (KVL) The algebraic sum of the “voltage drops” around any “closed loop” is zero. Why? We must return to the same potential (conservation of energy). Voltage drop defined as the branch voltage if the + sign is encountered first; it is (-) the branch voltage if the sign is encountered first … important bookkeeping Path Path + V1 “drop” V2 + - “rise” or “step up” (negative drop) Closed loop: Path beginning and ending on the same node 12/6/2004 EE 42 fall 2004 lecture 40 6 FORMAL CIRCUIT ANALYSIS USING KCL: NODAL ANALYSIS 1 Choose a Reference Node 2 Define unknown node voltages (those not fixed by voltage sources) 3 Write KCL at each unknown node, expressing current in terms of the node voltages (using the constitutive relationships of branch elements) 4 Solve the set of equations (N equations for N unknown node voltages) 12/6/2004 EE 42 fall 2004 lecture 40 7 NODAL ANALYSIS USING KCL –Example: The Voltage Divider – i1 1 Choose reference node R1 V2 + 2 Define unknown node voltages VSS + R2 V2 i2 3 Write KCL at unknown nodes VSS V2 V2 0 R1 R2 4 Solve: 12/6/2004 R2 V2 VSS R1 R 2 This is of course the voltage divider formula and is by itself very useful. EE 42 fall 2004 lecture 40 8 GENERALIZED VOLTAGE DIVIDER (solved without Nodal Analysis) Circuit with several resistors in series I R1 VSS + + V1 ? R2 R3 R4 + V3? • We know I VSS/(R1 R 2 R 3 R 4 ) • Thus, V1 R1 VSS R1 R 2 R 3 R 4 and V3 12/6/2004 R3 VSS R1 R 2 R 3 R 4 etc.. etc.. EE 42 fall 2004 lecture 40 9 WHEN IS VOLTAGE DIVIDER FORMULA CORRECT? I I R1 R1 + R2 V SS + V2 R3 + VSS V Z R2 + X R3 R4 i 3 R5 R4 V 2 R 2 R R R R 1 2 3 4 Correct if nothing else connected to nodes V SS What is VZ? 12/6/2004 VZ R2 VSS R1 R 2 R 3 R 4 because R5 removes condition of resistors in series – i.e. i 3 I Answer: R2 VSS R1 R 2 R 5 ( R 3 R 4 ) EE 42 fall 2004 lecture 40 10 RESISTORS IN PARALLEL VX 1 Select Reference Node 2 Define unknown node voltages Note: Iss = I1 + I2, i.e., V V ISS X X R1 R 2 I2 I1 ISS R1 1 VX ISS 1 1 R1 R 2 ISS R1R 2 R1 R 2 RESULT 1 EQUIVALENT RESISTANCE: R || R1 || R 2 RESULT 2 CURRENT DIVIDER: 12/6/2004 I1 R2 R1R 2 R1 R 2 VX R2 ISS R1 R1 R 2 VX R1 I2 ISS R2 R 1 R 2 11 EE 42 fall 2004 lecture 40 IDENTIFYING SERIES AND PARALLEL COMBINATIONS Use series/parallel equivalents to simplify a circuit before starting KVL/KCL I R1 R2 R3 R eq R1 V R1 R 2 R3 R2 + R4 R5 parallel R1 R 2 10 K R 3 R 20 K 3 R6 R4 5 5 K R 6 10 K I ( R1 R 2 ) || R 3 R eq + RX ? R X (R1 R 2 ) || R 3 (R 4 R 5 ) || R 6 15 K 12/6/2004 EE 42 fall 2004 lecture 40 12 IDENTIFYING SERIES AND PARALLEL COMBINATIONS (cont.) Some circuits must be analyzed (not amenable to simple inspection) R1 and R2 are not in || R2 R1 R1 V + R3 I R4 R5 V + - R2 R3 R4 Special cases: R3 = 0 OR R3 = R5 Example: R3 = 0 R1 || R2; R4 || R5 in series; OR IF R3 = (R1 +EER425)fall || 2004 (R2 + R) lecture4 40 12/6/2004 R1 and R5 are not in series Req = R1 || R2 + R4 || R5 13 TWO-TERMINAL LINEAR RESISTIVE NETWORKS (“One Port” Circuit) Model of two-terminal linear resistive elements with only two “accessible” terminals Replace a complicated circuit with a simple model + a b 12/6/2004 EE 42 fall 2004 lecture 40 14 BASIS OF THÉVENIN THEOREM • All linear one-ports have linear I-V graph • A voltage source in series with a resistor can produce any linear I-V graph by suitably adjusting V and I THUS We define the voltage-source/resistor combination that replicates the I-V graph of a linear circuit to be the Thévenin equivalent of the circuit. The voltage source VT is called the Thévenin equivalent voltage and the resistance RT is called the Thévenin equivalent resistance. 12/6/2004 EE 42 fall 2004 lecture 40 15 I-V CHARACTERISTICS OF LINEAR TWO-TERMINAL NETWORKS i 5K What is the easy way to + + find the I-V graph? 5V v Associated Apply v, measure i, or vice versa i(mA) 1 First find open-circuit V .5 v=5V if i = 0 v(V) Now find Short-circuit I i = -1mA if v = 0 Associated (i defined in) 5 -.5 -1 12/6/2004 EE 42 fall 2004 lecture 40 16 I-V CHARACTERISTICS OF LINEAR TWO-TERMINAL NETWORKS i + 5K Consider how the graph changes with differences in V and R. + 5V v Apply v, measure i, or vice versa i(mA) 1 If V = 2.5V .5 First consider change in V, eg V= 2.5V, not 5V Now consider change in R (with V back at 5V) 5 v(V) If R = 2.5K -.5 -1 Clearly by varying V and R we can produce an arbitrary linear graph … in other words this circuit can produce any linear graph 12/6/2004 EE 42 fall 2004 lecture 40 17 Thévenin Equivalent Circuit RT + VT i i + V Any linear circuit + V This circuit is equivalent to any circuit, that is by suitably choosing VT and RT it will have the same I-V graph So how do we choose VT and RT ? 12/6/2004 EE 42 fall 2004 lecture 40 18 NORTON EQUIVALENT CIRCUIT Corollary to Thévenin: I N ISC (short - circuit current) (associated) RN is found the same way as for Thévenin equivalent i IN 12/6/2004 RN EE 42 fall 2004 lecture 40 + V - 19 EXAMPLE 1, Continued equivalent to these? In what sense is this circuit A 1K 2 K 2 K + 2V 1V A A 1 mA + - B 1K B B They have identical I-V characteristics and therefore have The same open circuit voltage The same short circuit current For any voltage, they will produce the same current And visa versa 12/6/2004 EE 42 fall 2004 lecture 40 20 Load line method We can find the currents and voltages in a simple circuit graphically. For example if we apply a voltage of 2.5V to the two resistors of our earlier example: We draw the I-V of the voltage and the I-V graph of the two resistors on the same axes. Can you guess where the solution is? At the point where the voltages of the two graphs AND the currents are equal. (Because, after all, the currents are equal, as are the voltages.) I (ma) I + 2.5V - 1K + 4 V 4K - 2 2.5V Solution: I = 0.5mA, V = 2.5V Combined 1K + 4K 5 12/6/2004 EE 42 fall 2004 lecture 40 V (Volt) 21 Another Example of the Load-Line Method Lets hook our 2K resistor + 2V source circuit up to an LED (light-emitting diode), which is a very nonlinear element with the IV graph shown below. Again we draw the I-V graph of the 2V/2K circuit on the same axes as the graph of the LED. Note that we have to get the sign of the voltage and current correct!! At the point where the two graphs intersect, the voltages and the currents are equal, in other words we have the solution. I (ma) I + 2V - LED 2K + 4 LED Solution: I = 0.7mA, V = 1.4V V - 2 5 12/6/2004 EE 42 fall 2004 lecture 40 V (Volt) 22 Simplification for time behavior of RC Circuits We call the time period during which the output changes the transient We can predict a lot about the transient behavior from the pre- and post-transient dc solutions 12/6/2004 input time voltage Long after the input change occurs things “settle down” …. Nothing is changing …. So again we have a dc circuit problem. voltage Before any input change occurs we have a dc circuit problem (that is we can use dc circuit analysis to relate the output to the input). EE 42 fall 2004 lecture 40 output time 23 RC RESPONSE Case 1 – Rising voltage. Capacitor uncharged: Apply + voltage step V1 Vin Input node Vout 0 R + Vin Output node Vout C - ground time • Vin “jumps” at t=0, but Vout cannot “jump” like Vin. Why not? 0 Because an instantaneous change in a capacitor voltage would require instantaneous increase in energy stored (1/2CV²), that is, infinite power. (Mathematically, V must be differentiable: I=CdV/dt) V does not “jump” at t=0 , i.e. V(t=0+) = V(t=0-) The dc solution before the transient tells us the capacitor voltage at the beginning of the transient. 12/6/2004 EE 42 fall 2004 lecture 40 24 RC RESPONSE Case 1 Continued – Capacitor uncharged: Apply voltage step V1 Vin Input node + Vout Vin - 0 0 time R Output node Vout C ground • Vout approaches its final value asymptotically (It never actually gets exactly to V1, but it gets arbitrarily close). Why? After the transient is over (nothing changing anymore) it means d(V)/dt = 0 ; that is all currents must be zero. From Ohm’s law, the voltage across R must be zero, i.e. Vin = Vout. That is, Vout V1 as t . (Asymptotic behavior) Again the dc solution (after the transient) tells us (the asymptotic limit of) the capacitor voltage during the transient. 12/6/2004 EE 42 fall 2004 lecture 40 25 RC RESPONSE Example – Capacitor uncharged: Apply voltage step of 5 V 5 Vin Input node Output node + Vout Vin - 0 0 R time Vout C ground • Clearly Vout starts out at 0V ( at t = 0+) and approaches 5V. • We know this because of the pre-transient dc solution (V=0) and post-transient dc solution (V=5V). So we know a lot about Vout during the transient - namely its initial value, its final value , and we know the general shape . 12/6/2004 EE 42 fall 2004 lecture 40 26 Review of simple exponentials. Rising Exponential from Zero Falling Exponential to Zero Vout = V1(1-e-t/t) Vout = V1e-t/t Vout = 0 , and at t = 0, Vout = V1 , and at t , 8 Vout V1 also at t , at t = t, Vout 0, also Vout = 0.63 V1 at t = t, Vout = 0.37 V1 8 at t = 0, Vout Vout V1 V1 .63V1 .37V1 0 0 12/6/2004 t time 0 EE 42 fall 2004 lecture 40 0 t time 27 Further Review of simple exponentials. Rising Exponential from Zero Falling Exponential to Zero Vout = V1(1-e-t/t) Vout = V1e-t/t We can add a constant (positive or negative) Vout = V1(1-e-t/t) + V2 Vout = V1e-t/t + V2 Vout Vout V1 + V2 V1 + V2 .63V1+ V2 .37V1 + V2 V2 0 V2 0 12/6/2004 t time 0 EE 42 fall 2004 lecture 40 0 t time 28 Further Review of simple exponentials. Rising Exponential Falling Exponential Vout = V1 (1-e-t/t) + V2 Vout = V1e-t/t + V2 Both equations can be written in one simple form: Vout = A + Be-t/t Initial value (t=0) : Vout = A + B. Final value (t>>t): Vout = A Thus: if B < 0, rising exponential; if B > 0, falling exponential Vout Vout A A+B Here B > 0 Here B < 0 A+B 0 A 0 12/6/2004 time 0 EE 42 fall 2004 lecture 40 0 time 29 LOGIC GATE DELAY tD Time delay tD occurs between input and output: “computation” is not instantaneous Value of input at t = 0+ determines value of output at later time t = tD F A Logic State B Capacitance to Ground Input (A and B tied together) 1 0 t 0 1 Output (Ideal delayed step-function) F 0 12/6/2004 tD Actual exponential voltage versus time. 0 EE 42 fall 2004 lecture 40 t 30 SIGNAL DELAY: TIMING DIAGRAMS Show transitions of variables vs time Oscilloscope Probe A B C D Logic state A Note B changes one gate delay after A switches Note that C changes two gate delays after A switches. 1 0 B t t t 2t t t 2t 3t t C Note that D changes three gate delays D after A switches. 12/6/2004 t 0 EE 42 fall 2004 lecture 40 31