CS 61C: Great Ideas in
Computer Architecture
Course Summary & Review
Instructor: Justin Hsia
8/06/2012
Summer 2012 -- Lecture #28
1
Agenda
•
•
•
•
Course Summary
Administrivia
What’s Next?
Acknowledgements
8/06/2012
Summer 2012 -- Lecture #28
2
Six Great Ideas in
Computer Architecture
1. Layers of Representation/Interpretation
2. Moore’s Law
3. Principle of Locality/Memory Hierarchy
4. Parallelism
5. Performance Measurement & Improvement
6. Dependability via Redundancy
8/06/2012
Summer 2012 -- Lecture #28
3
Great Idea #1: Levels of
Representation/Interpretation
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
Higher-Level Language
Program (e.g. C)
Compiler
lw
lw
sw
sw
Assembly Language
Program (e.g. MIPS)
Assembler
Machine Language
Program (MIPS)
0000
1010
1100
0101
$t0, 0($2)
$t1, 4($2)
$t1, 0($2)
$t0, 4($2)
1001
1111
0110
1000
1100
0101
1010
0000
0110
1000
1111
1001
1010
0000
0101
1100
1111
1001
1000
0110
0101
1100
0000
1010
1000
0110
1001
1111
Machine
Interpretation
Hardware Architecture Description
(e.g. block diagrams)
Architecture
Implementation
Logic Circuit Description
(Circuit Schematic Diagrams)
8/06/2012
Summer 2012 -- Lecture #28
4
Number Representation
• Anything can be represented as a number!
– With n digits in base B, can represent Bn things
• IEC (vs. SI) prefixes (210 ≈ 103)
• Signed and unsigned integers
– Addition, subtraction, overflow, sign extension
– Two’s complement (better than 1’s and sign&mag)
• Floating point (sign, biased exp, significand)
– Inf, NaN, 0, denorms
– Precision and truncation
8/06/2012
Summer 2012 -- Lecture #28
5
Higher-Level Language (HLL)
• We studied C because exposes more of
hardware (particularly memory)
– Compiled language is machine-dependent
• Arrays and strings
– Don’t run off the end or forget null terminator
• Pointers hold addresses, used to pass by ref
– Pointer arithmetic
– Array vs. pointer syntax
• Structs are padded collections of variables
8/06/2012
Summer 2012 -- Lecture #28
6
Assembly Language
• Close to the level that a machine understands
– ISA in human-readable format
– TAL vs. MAL (pseudo-instructions)
• RISC vs. CISC and effects
• MIPS Instruction Formats: R, I, J
– Meaning and limitations of the fields
– Relative (branch) vs. absolute (jump) addressing
– Register conventions (saved/volatile; caller/callee)
• Assembler: instr translation, sym/rel tables
8/06/2012
Summer 2012 -- Lecture #28
7
Machine Language
• Everything is just 0’s and 1’s!
– Usually done by assembler & linker, but can also
do manually
– At this level, just raw bits! No differentiation
between instructions and different types of data
– Alignment matters
• Executable produced by linker, run by loader
– OS creates new process (PT, swap space)
– Instructions loaded and run by processor
8/06/2012
Summer 2012 -- Lecture #28
8
Hardware Architecture Description
• Processor split into Datapath and Control
– Datapath components: I$/D$, RegFile, ALU, Extender,
MUXes
• Datapath Stages: IF, ID, EX, MEM, WB
– Controller: Use “AND” and “OR” Logic blocks to
determine control signal values for each instruction
• Can build/design components hierarchically
• Behavior of many circuits/programs can be
represented using Finite State Machines
– States, transition function, initial state
8/06/2012
Summer 2012 -- Lecture #28
9
Logic Circuit Description
• Build Synchronous Digital Systems out of
combinational and sequential logic
• Equivalence between Circuit Diagrams, Truth
Tables, and Boolean Expressions
– Can convert between all representations
• Boolean algebra allows for circuit simplification
(Karnaugh maps, too)
• FSMs built with registers and CL
• In reality, everything wires and transistors
– Voltage-controlled switches (1: high, 0: low)
8/06/2012
Summer 2012 -- Lecture #28
10
# of transistors on an integrated circuit (IC)
Great Idea #2: Moore’s Law
8/06/2012
Predicts: Transistor count
per chip doubles
every 2 years
Gordon Moore
Intel Cofounder
B.S. Cal 1950
Year:
Summer 2012 -- Lecture #28
11
Technology Trends
• Dynamic power = C × V2 × f
– Capacitance, voltage, switching frequency
• In WSC: Power Usage Effectiveness (PUE) =
Total building power / IT equipment power
• Technology growth is slowing, processors have
hit a power wall
– Everywhere: transistor density, CPU speed, disk
and memory capacity
– Performance improvements now coming from
parallelism and multicore processors
8/06/2012
Summer 2012 -- Lecture #28
12
Transition to Multicore
Sequential App
Performance
7/10/2012
Summer 2012 -- Lecture #13
13
Great Idea #3: Principle of Locality/
Memory Hierarchy
Increasing
distance from
application/user
Trade-off in
speed and cost
vs. capacity!
8/06/2012
Summer 2012 -- Lecture #28
14
Memory
• Programmer treats as one long array
– You know that this is just an illusion (VM)!
• Memory is byte-addressed
– Most data (including instructions) in words and
word-aligned, so all word addresses are multiples
of 4 (end in 0b00)
• Multicore systems use shared memory
– Synchronization/cache coherence necessary
8/06/2012
Summer 2012 -- Lecture #28
15
Memory Management
• Program’s address space
contains four regions:
~ FFFF FFFFhex
– Stack: local variables, grows
downward
– Heap: space requested for pointers
via malloc(); resizes
dynamically, grows upward
– Static Data: global and static
variables, does not grow or shrink
– Code: loaded when program
starts, does not change size
~ 0hex
7/03/2012
Summer 2012 -- Lecture #10
stack
heap
static data
code
16
Typical Memory Hierarchy
• Take advantage of the principle of locality to present the user
with as much memory as is available in the cheapest
technology at the speed offered by the fastest technology
On-Chip Components
Control
Instr Data
Cache Cache
8/06/2012
D TLB
RegFile
Speed: (cycles) ½’s
Size: (bytes) 100’s
Cost/bit:
highest
I TLB
Datapath
Second
Level
Cache
(SRAM)
Main
Memory
(DRAM)
1’s
10K’s
10’s
M’s
100’s
G’s
Summer 2012 -- Lecture #28
Secondary
Memory
(Disk
or Flash)
1,000,000’s
T’s
lowest
17
Accessing Data
1) Check TLB/PT if page is in main memory
– Page fault to load from disk (swap space) if not
2) Check cache for data
– Fetch from main memory on cache miss
– Return data to processor
hit
CPU
VA
PA Cache
TLB
miss
Page
Table
8/06/2012
hit
Summer 2012 -- Lecture #28
miss
Main
data Memory
18
Caching Details (1/2)
• Move data in contiguous blocks
– Store data in cache, closer to processor
• Cache organization
– Map data addresses to the limited number of block
locations in cache
– Set associativity: # of slots per set
• TIO breakdown
– Tag as block identifier, Index to find set in cache,
Offset to find data within block
• Also store management bits for each block
– Valid bit, (Dirty bit), Tag bits
8/06/2012
Summer 2012 -- Lecture #28
19
Caching Details (2/2)
• Cache parameters affect performance
– Block size, cache size, set associativity
– Write-back/write-through policies
– Write allocate/no-write allocate policies
– Block replacement policy (Least Recently Used)
• Source of cache misses: The 3 C’s
– Compulsory, capacity, conflict
• Multilevel caches reduce miss penalty
8/06/2012
Summer 2012 -- Lecture #28
20
Virtual Memory Details (1/3)
• Give main memory effective size of disk
without major penalty to performance
– Move data in contiguous pages from disk to main
memory
– Assumption is that memory is small compared to
both disk and virtual address space (or many
processes)
• Also provide protection for multiple processes
– Requires a lot of work by operating system
8/06/2012
Summer 2012 -- Lecture #28
21
Virtual Memory Details (2/3)
• Paging requires address translation
– Can run programs larger than main memory
– Hides variable machine configurations (RAM/HDD)
– Solves fragmentation problem
• Address mappings stored in page tables in
memory
– Additional memory access mitigated with TLB,
which is a cache for page table
– Management bits: Valid, Dirty, Ref, Access Rights
7/31/2012
Summer 2012 -- Lecture #25
22
Virtual Memory Details (3/3)
• Running multiple processes:
– Each process has its own page table and swap
space in disk
– OS can switch between by saving and loading
process states (PC, reg vals, page table address)
– On context switch, flush TLB and pipeline
7/31/2012
Summer 2012 -- Lecture #25
23
Input/Output
• Disk Latency = Seek Time + Rotation Time +
Transfer Time + Controller Overhead
• Processor must synchronize with I/O devices
before use due to difference in data rates:
– Polling works, but expensive due to repeated
queries
– Exceptions are “unexpected” events in processor
– Interrupts are asynchronous events that are often
used for interacting with I/O devices
• In SW, need special handling code
8/06/2012
Summer 2012 -- Lecture #28
24
Great Idea #4: Parallelism
Software
• Parallel Requests
Assigned to computer
e.g. search “Katz”
Hardware
Smart
Phone
Warehouse
Scale
Computer
Leverage
• Parallel Threads Parallelism &
Assigned to core
e.g. lookup, ads
Achieve High
Performance
Computer
• Parallel Instructions
Core
> 1 instruction @ one time
e.g. 5 pipelined instructions
• Parallel Data
> 1 data item @ one time
e.g. add of 4 pairs of words
Memory
6/18/2012
Input/Output
Core
Instruction Unit(s)
Functional
Unit(s)
A0+B0 A1+B1 A2+B2 A3+B3
• Hardware descriptions
All gates functioning in
parallel at same time
Core
…
Cache Memory
Summer 2012 -- Lecture #1
Logic Gates
25
Types of Parallelism (1/4)
• Request-Level Parallelism (RLP)
– Handling many requests per second
(e.g. web search)
• Data-Level Parallelism (DLP)
– Operate on many pieces of data at once
– SIMD: at the level of single instructions
– MapReduce: at the level of programs (split into
map and reduce)
8/06/2012
Summer 2012 -- Lecture #28
26
Types of Parallelism (2/4)
• Thread-Level Parallelism (TLP)
– Have many processors, run either different
programs or different parts of same program at
same time
– If same program, need to deal with shared
memory (cache coherence and synchronization
primitives to prevent data races)
– Splitting up work properly is difficult!
• Shared vs. private variables in OpenMP
• Often requires re-designing your algorithm
8/06/2012
Summer 2012 -- Lecture #28
27
Types of Parallelism (3/4)
• Thread-Level Parallelism (TLP)
– Synchronization requires hardware support
• Test-and-set mechanism
• ll and sc in MIPS
– OpenMP directives
• parallel, for, sections, single, etc.
• critical, atomic, master
8/06/2012
Summer 2012 -- Lecture #28
28
Types of Parallelism (4/4)
• Instruction Level Parallelism (ILP)
– Pipelining: increase throughput by adding
registers
• Reduce critical path, increase max frequency
• Working on multiple instructions at once introduces
hazards (structural, data, control)
• Forwarding, delay slots, code reordering
– Multiple instruction issue (superscalar)
• Register renaming, speculation, out-of-order execution
• Loop unrolling
8/06/2012
Summer 2012 -- Lecture #28
29
Great Idea #5: Performance
Measurement and Improvement
• Allows direct comparisons of architectures
and quantification of improvements
• It is all about time to finish (latency)
– Includes both setup and execution.
• Match application and hardware to exploit:
– Locality
– Parallelism
– Special hardware features, like specialized
instructions (e.g. matrix manipulation)
8/06/2012
Summer 2012 -- Lecture #28
30
Performance Measurements
• Execution time (latency) and work per time
(throughput)
– CPU Time = Instructions × CPI × Clock Cycle Time
• Memory Access:
– AMAT, CPIstall use hit time, miss rate, miss penalty
– Definitions recursive back to last level in hierarchy
• Amdahl’s Law
– Speedup = 1 / [ (1-F) + F/S ]
– Why we almost never get max possible speedup
8/06/2012
Summer 2012 -- Lecture #28
31
Performance Programming
• Key challenge: Craft parallel programs that
that scale well (weak/strong scaling)
– Scheduling, load balancing, time for
synchronization, overhead for communication
• Some techniques:
– Register/Cache Blocking
– Data Parallelism & Loop Unrolling
– Multithreading
8/06/2012
Summer 2012 -- Lecture #28
32
Dependability Measures
• Failure rates and time
– MTTF, MTTR, MTBF
• Availability = MTTF / (MTTF + MTTR)
– Use measures in # of 9s
8/06/2012
Summer 2012 -- Lecture #28
33
Great Idea #6: Dependability
via Redundancy
• Redundancy so that a failing piece doesn’t
make the whole system fail
• Applies to everything from datacenters to storage to
memory
– Redundant datacenters so that can lose 1 datacenter but
Internet service stays online
– Redundant disks so that can lose 1 disk but not lose data
(Redundant Arrays of Independent Disks/RAID)
– Redundant memory bits of so that can lose 1 bit but no
data (Error Correcting Code/ECC Memory)
8/06/2012
Summer 2012 -- Lecture #28
34
Redundant Arrays of Inexpensive Disks
• Possible to simulate behavior of single larger
disk with an array of smaller disks
•
•
•
•
•
•
– Cheaper, higher bandwidth, more resistant to
failure
RAID 0 – No redundancy
RAID 1 – Mirroring for redundancy
RAID 2 – Bit-level striping
RAID 3 – Parity disks
RAID 4 – Block-level striping with parity disk
RAID 5 – Striped parity
8/06/2012
Summer 2012 -- Lecture #28
35
Error Detection & Correction
• Even parity using XOR
• Hamming Distance
– Distance 2 can detect 1-bit error
– Distance 3 can correct 1-bit error
– Distance 4 can correct 1-bit error and detect 2-bit
error
• Hamming ECC
– Introduce extra parity bits (one per group)
– Sum of group errors indicates corrupted bit
8/06/2012
Summer 2012 -- Lecture #28
36
Agenda
•
•
•
•
Course Summary
Administrivia
What’s Next?
Acknowledgements
8/06/2012
Summer 2012 -- Lecture #28
37
Administrivia
• Last discussion today
• Lectures: Old finals problems &
“Biological Computing”
• Final Exam (Thu) @ 9am-12pm, 245 Li Ka Shing
– Two-sided handwritten cheat sheet
– Green sheet provided
• Extra OH: Justin MW 12-1pm, 411 Soda
8/06/2012
Summer 2012 -- Lecture #28
38
Project 2: sgemm-small.c
Average Speed on Small Matrices m=[32,100] by n=[32,300]
14
Mean:
7.2
Std Dev: 1.9
12
Frequency
10
8
6
4
2
0
3
8/06/2012
4
5
6
7
8
Gflops/s
9
Summer 2012 -- Lecture #28
10
11
12
13
39
Project 2: sgemm-small.c
Average Speed on 36 x 36 Matrices
15
Mean:
11.1
Std Dev: 2.2
Frequency
10
5
0
8/06/2012
4
6
8
10
12
Gflops/s
Summer 2012 -- Lecture #28
14
16
18
40
Project 2: sgemm-openmp.c
Average Speed on Large Matrices m=[1000,10000] by n=[32,100]
9
8
Mean:
51.3
Std Dev: 17.5
7
Frequency
6
5
4
3
2
1
0
8/06/2012
0
10
20
30
40
Gflops/s
50
Summer 2012 -- Lecture #28
60
70
80
41
Project 2 Fastest Submissions
• sgemm-small (small):
1) 12.4 Gflop/s
2) 11.0 Gflop/s
3) 10.4 Gflop/s
Harkiran Bolaria, Andrew Cai
Yun Jae Cho, Duc Nguyen
Shawn Park, Tananun
Songdechakraiwut
• sgemm-small (36×36):
1) 16.4 Gflop/s
2) 16.4 Gflop/s
3) 16.1 Gflop/s
8/06/2012
Luis De Pombo, Steven Roger
Bryan Cote, Myron Chen
Chris Buonocore, Ali Jishi
Summer 2012 -- Lecture #28
42
Project 2 Fastest Submissions
• sgemm-openmp:
1) 77.2 Gflop/s
2) 73.0 Gflop/s
3) 72.8 Gflop/s
8/06/2012
Chris Buonocore, Ali Jishi
Shawn Park, Tananun
Songdechakraiwut
Moshe Leon, Ashkon Soroudi
Summer 2012 -- Lecture #28
43
Agenda
•
•
•
•
Course Summary
Administrivia
What’s Next?
Acknowledgements
8/06/2012
Summer 2012 -- Lecture #28
44
What’s Next?
• Take classes from great teachers! (teacher > class)
– Distinguished Teaching Award (very hard to get)
– HKN Course evaluations (≥ 6 is very good)
– Upcoming instructors for classes: (CS / EE)
• Classes related to CS 61C
–
–
–
–
–
–
8/06/2012
CS169 Software Engineering (for SaaS, Fox/Patterson Fall 12)
CS194-15 Engineering Parallel Software
CS164 Programming Languages and Compilers
CS162 Operating Systems and Systems Programming
CS152 Computer Architecture and Engineering (Sp13)
CS150 Components and Design Techniques for Digital Systems
Summer 2012 -- Lecture #28
45
Opportunities in Teaching
• Interest in joining the CS staff?
– Applies for CS 10, 61A, 61B, 61C
– Usual path: Lab Assistant  Reader  TA
– Also: Self-Paced Center Tutor
• Requirements:
– Interest in teaching
– Stricter grade requirements based on where you want
to jump in
• Applying:
– Application form (for TA, Reader, or Lab Assistant)
– Doesn’t hurt to e-mail professor as well
8/06/2012
Summer 2012 -- Lecture #28
46
Opportunities at Cal
• Why are we a top university in the WORLD?
– Research, research, research!
– Classes are just the tip of the iceberg
– Whether you want to go to grad school or
industry, you need someone to vouch for you
– Won’t know if you like it or not until you try
• Find out what you like, do lots of web research
(read published papers), hit OH of professor,
show enthusiasm & initiative
8/06/2012
Summer 2012 -- Lecture #28
47
Agenda
•
•
•
•
Course Summary
Administrivia
What’s Next?
Acknowledgements
8/06/2012
Summer 2012 -- Lecture #28
48
Special Thanks
Professor
Randy Katz
Professor
David Patterson
Lecturer SOE
Dan Garcia
Su11
Instructor
Michael
Greenbaum
8/06/2012
Summer 2012 -- Lecture #28
49
Special Thanks to the Staff:
• TAs:
Brandon Lee
Paul Ruan
Raphael Townshend
Sung Roa Yoon
• Readers:
Allen Xiao
Linda Cai
• Lab Assistants:
Crystal Dou
Inderjit Jutla
8/06/2012
Jamie Li
Roger Gong
Hoang Nguyen
Oscar Bachtiar
Summer 2012 -- Lecture #28
50