inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture 28 –
Single Cycle CPU Control II
Lecturer PSOE Dan Garcia
www.cs.berkeley.edu/~ddgarcia
DARPA $s drying up…ouch! 
“I'm worried and depressed,”
– David Patterson, president of the ACM.
There is a significant shift of $ from “Blue
Sky” research to military contractors. This is a
significant shift, mostly for the worse.
www.nytimes.com/2005/04/02/technology/02darpa.html?
CS61C L27 Single Cycle CPU Control II (1)
Garcia © UCB
Review: Single cycle datapath
°5 steps to design a processor
• 1. Analyze instruction set => datapath requirements
• 2. Select set of datapath components & establish clock
methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
determine setting of control points that effects the
register transfer.
Processor
• 5. Assemble the control logic
Input
°Control is the hard part
°MIPS makes that easier
Control
Memory
Datapath
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates
CS61C L27 Single Cycle CPU Control II (2)
Output
Garcia © UCB
A Summary of the Control Signals (2/2)
See
Appendix A
func 10 0000 10 0010
We Don’t Care :-)
op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
add
sub
ori
lw
sw
beq
jump
RegDst
1
1
0
0
x
x
x
ALUSrc
0
0
1
1
1
0
x
MemtoReg
0
0
0
1
x
x
x
RegWrite
1
1
1
1
0
0
0
MemWrite
0
0
0
0
1
0
0
nPCsel
0
0
0
0
0
1
0
Jump
0
0
0
0
0
0
1
ExtOp
x
x
0
1
1
x
x
Add
Subtract
Or
Add
Add
Subtract
x
ALUctr<2:0>
31
26
21
16
R-type
op
rs
rt
I-type
op
rs
rt
J-type
op
CS61C L27 Single Cycle CPU Control II (3)
11
rd
6
shamt
immediate
target address
0
funct
add, sub
ori, lw, sw, beq
jump
Garcia © UCB
The Single Cycle Datapath during Jump
31
J-type
26 25
0
op
target address
jump
• New PC = { PC[31..28], target address, 00 }
Instruction<31:0>
Jump=
<0:25>
Data In32
ALUSrc =
0
32
Clk
WrEn Adr
32
Mux
32
<0:15>
1
<11:15>
16
Extender
imm16
Rs Rd Imm16 TA26
MemtoReg =
Zero MemWr =
ALU
busA
Rw Ra Rb
32
32 32-bit
Registers busB
0
32
<16:20>
5
Rt
ALUctr =
Rs Rt
5
5
Mux
32
Clk
Clk
1 Mux 0
RegWr =
busW
Rt
<21:25>
RegDst =
Rd
Instruction
Fetch Unit
nPC_sel=
1
Data
Memory
ExtOp =
CS61C L27 Single Cycle CPU Control II (4)
Garcia © UCB
The Single Cycle Datapath during Jump
31
J-type
26 25
0
op
target address
jump
• New PC = { PC[31..28], target address, 00 }
Instruction<31:0>
Jump=1
<0:25>
Data In32
ALUSrc = x
0
32
Clk
WrEn Adr
32
Mux
32
<0:15>
1
<11:15>
16
Extender
imm16
Rs Rd Imm16 TA26
MemtoReg = x
Zero MemWr = 0
ALU
busA
Rw Ra Rb
32
32 32-bit
Registers busB
0
32
<16:20>
5
Rt
ALUctr =x
Rs Rt
5
5
Mux
32
Clk
Clk
1 Mux 0
RegWr = 0
busW
Rt
<21:25>
RegDst = x
Rd
Instruction
Fetch Unit
nPC_sel=0
1
Data
Memory
ExtOp = x
CS61C L27 Single Cycle CPU Control II (5)
Garcia © UCB
Instruction Fetch Unit at the End of Jump
31
26 25
J-type
0
op
target address
jump
• New PC = { PC[31..28], target address, 00 }
Jump
Inst
Memory
nPC_sel
Instruction<31:0>
Adr
Zero
nPC_MUX_sel
Adder
0
PC
Mux
Adder
imm16
00
4
How do we modify this
to account for jumps?
1
Clk
CS61C L27 Single Cycle CPU Control II (6)
Garcia © UCB
Instruction Fetch Unit at the End of Jump
31
26 25
J-type
0
op
target address
jump
• New PC = { PC[31..28], target address, 00 }
Jump
Inst
Memory
nPC_sel
Instruction<31:0>
Adr
Zero
Mux
Adder
imm16
00
4 (MSBs)
1
CS61C L27 Single Cycle CPU Control II (7)
00
Adder
0
1
PC
4
Mux
TA26
nPC_MUX_sel
0
Clk
Query
• Can Zero still
get asserted?
• Does nPC_sel
need to be 0?
• If not, what?
Garcia © UCB
Build CL to implement Jump on paper now
Inst31
Inst30
Inst29
Inst28
Inst27
Inst26
Inst25
Jump
Inst01
Inst00
CS61C L27 Single Cycle CPU Control II (8)
Garcia © UCB
Review: Finite State Machine (FSM)
• States
represent possible
output values.
• Transitions
represent changes
between states
based on inputs.
• Implement
with CL and
clocked register
feedback.
CS61C L27 Single Cycle CPU Control II (11)
Garcia © UCB
Finite State Machines extremely useful!
• They define
• How output signals respond to input
signals and previous state.
• How we change states depending on
input signals and previous state
• The output signals could be our
familiar control signals
• Some control signals may only depend
on CL, not on state at all…
• We could implement very detailed
FSMs w/Programmable Logic Arrays
CS61C L27 Single Cycle CPU Control II (12)
Garcia © UCB
Taking advantage of sum-of-products
• Since sum-of-products is a convenient
notation and way to think about
design, offer hardware building blocks
that match that notation
• One example is
Programmable Logic Arrays (PLAs)
• Designed so that can select (program)
ands, ors, complements after you get
the chip
• Late in design process, fix errors, figure
out what to do later, …
CS61C L27 Single Cycle CPU Control II (13)
Garcia © UCB
Programmable Logic Arrays
• Pre-fabricated building block of many
AND/OR gates
• “Programmed” or “Personalized" by making or
breaking connections among gates
• Programmable array block diagram for sum of
products form
Or Programming:
• How to combine product terms?
• How many outputs?
• • •
inputs
AND
array
product
terms
And Programming:
• How many inputs?
• How to combine inputs?
• How many product terms?
CS61C L27 Single Cycle CPU Control II (14)
OR
array
outputs
• • •
Garcia © UCB
Enabling Concept
• Shared product terms among outputs
F0
F1
F2
F3
example:
=
=
=
=
A
+
A C' +
B' C' +
B' C +
1 = uncomplemented in term
0 = complemented in term
– = does not participate
personality matrix
Product
term
AB
B'C
AC'
B'C'
A
inputs
A B
1 1
– 0
1 –
– 0
1 –
C
–
1
0
0
–
outputs
F0 F1 F2
0 1 1
0 0 0
0 1 0
1 0 1
1 0 0
CS61C L27 Single Cycle CPU Control II (15)
B' C'
AB
AB
A input side: 3 inputs
F3
0
1
0
0
1
output side: 4 outputs
1 = term connected to output
0 = no connection to output
reuse of terms;
5 product terms
Garcia © UCB
Before Programming
• All possible connections available before
“programming”
CS61C L27 Single Cycle CPU Control II (16)
Garcia © UCB
After Programming
• Unwanted connections are "blown"
• Fuse (normally connected, break unwanted
ones)
• Anti-fuse (normally disconnected, make wanted
connections)
A
B
C
AB
B'C
AC'
B'C'
A
F0
CS61C L27 Single Cycle CPU Control II (17)
F1
F2
F3
Garcia © UCB
Alternate Representation
• Short-hand notation--don't have to draw all
the wires
• X Signifies a connection is present and
perpendicular signal is an input to gate
notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
A B C D
AB
A'B'
CD'
C'D
AB+A'B'
CD'+C'D
CS61C L27 Single Cycle CPU Control II (18)
Garcia © UCB
Peer Instruction
Instruction<31:0>
1
32
Clk
Imm16
MemWr
MemtoReg
0
32
Data In 32
ALUSrc
Rs Rd
WrEn Adr
32
Mux
Extender
C.
16
Rt
Zero
ALUctr
busA
Rw Ra Rb
32
32 32-bit
Registers busB
0
32
imm16
B.
Rs Rt
5
Mux
32
Clk
5
ALU
busW
5
<0:15>
RegWr
A.
Clk
1 Mux 0
<11:15>
RegDst
Rt
<21:25>
Rd
Instruction
Fetch Unit
<16:20>
nPC_sel
1
Data
Memory
1:
ExtOp
2:
MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ? 3:
4:
ALUctr=‘add’. Which 1 signal is different for
5:
all 3 of: ADD, LW, & SW? RegDst or ExtOp?
6:
7:
“Don’t Care” signals are useful because we
can simplify our PLA personality matrix. F / T? 8:
CS61C L27 Single Cycle CPU Control II (19)
ABC
SRF
SRT
SEF
SET
BRF
BRT
BEF
BET
Garcia © UCB
And in Conclusion… Single cycle control
°5 steps to design a processor
• 1. Analyze instruction set => datapath requirements
• 2. Select set of datapath components & establish clock
methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
determine setting of control points that effects the
register transfer.
Processor
• 5. Assemble the control logic
Input
°Control is the hard part
°MIPS makes that easier
Control
Memory
Datapath
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates
CS61C L27 Single Cycle CPU Control II (20)
Output
Garcia © UCB