inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture 37
VM III
2004-11-24
Lecturer PSOE Dan Garcia
www.cs.berkeley.edu/~ddgarcia
#4 Bears crush Stanford
This 230mph electric
car accelerates faster
than a Porsche 911
Turbo and goes 200
miles on a single
charge! Wow!
CS61C L37 VM III (1)
eliica.com
Garcia, Fall 2004 © UCB
Peer Instruction Correction
° A direct-mapped $ will never out-perform a 2way set-associative $ of the same size.
• I said “TRUE … increased associativity!”
• Right Answer “FALSE … consider the following”
-
0
1
2
3
4
We have 4 byte cache, block size = 1 byte. Compare a
2-way set-associative cache (2 sets using LRU
replacement) with a direct mapped cache (four rows).
0
2-way
set
associative
Empty
LRU=0,2
0
1
2
3
0
1
2
3
CS61C L37 VM III (2)
0
Miss, Load 0, Miss, Load 2
LRU=1,2
LRU=0,2
0
0
0
1
1
1
2
2
2
3
3
3
Empty
direct
mapped
2
Miss
Load 0
0
1
2
3
Miss
Load 2
0
1
2
3
4
Hit!
LRU=1,2
Miss, Load 4 Miss, Load 2
LRU=0,2
LRU=1,2
0
0
0
1
1
1
2
2
2
3
3
3
Hit!
0
1
2
3
2
Miss
Load 4
0
1
2
3
Hit
0
1
2
3
time
0
1
2
3
Garcia, Fall 2004 © UCB
Peer Instruction
ABC
1. Increasing at least one of {associativity,
1: FFF
block size} always a win
2: FFT
FTF
2. Higher DRAM bandwidth translates to a 3:
4: FTT
lower miss rate
5: TFF
3. DRAM access time improves roughly
as fast as density
CS61C L37 VM III (3)
6: TFT
7: TTF
8: TTT
Garcia, Fall 2004 © UCB
Address Translation & 3 Concept tests
Virtual Address
VPN
INDEX
Offset
TLB
...
V. P. N.
Virtual
Page
Number
V. P. N.
P. P. N.
Physical
Page
Number
P. P. N.
PPN
Data Cache
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Tag Data
Tag Data
Offset
Physical Address
TAG INDEX Offset
Garcia, Fall 2004 © UCB
Peer Instruction (1/3)
°40-bit virtual address, 16 KB page
Virtual Page Number (? bits)
Page Offset (? bits)
°36-bit physical address
Physical Page Number (? bits)
Page Offset (? bits)
°Number of bits in Virtual Page Number/ Page
offset, Physical Page Number/Page offset?
1:
2:
3:
4:
5:
22/18 (VPN/PO), 22/14 (PPN/PO)
24/16, 20/16
26/14, 22/14
26/14, 26/10
28/12, 24/12
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Peer Instruction (2/3): 40b VA, 36b PA
°2-way set-assoc. TLB, 256 “slots”, 40b VA:
TLB Tag (? bits)
TLB Index (? bits)
Page Offset (14 bits)
°TLB Entry: Valid bit, Dirty bit,
Access Control (say 2 bits),
Virtual Page Number, Physical Page Number
V D Access (2 bits)
TLB Tag (? bits)
Physical Page No. (? bits)
°Number of bits in TLB Tag / Index / Entry?
1:
2:
3:
4:
12 / 14 / 38 (TLB Tag / Index / Entry)
14 / 12 / 40
18 / 8 / 44
18 / 8 / 58
CS61C L37 VM III (8)
Garcia, Fall 2004 © UCB
Peer Instruction (3/3)
°2-way set-assoc, 64KB data cache, 64B block
Cache Tag (? bits) Cache Index (? bits)
Block Offset (? bits)
Physical Page Address (36 bits)
°Data Cache Entry: Valid bit, Dirty bit, Cache
tag + ? bits of Data
V D
Cache Tag (? bits)
Cache Data (? bits)
°Number of bits in Data cache Tag / Index /
Offset / Entry?
1:
2:
3:
4:
5:
12 / 9 / 14 / 87 (Tag/Index/Offset/Entry)
20 / 10 / 6 / 86
20 / 10 / 6 / 534
21 / 9 / 6 / 87
21 / 9 / 6 / 535
CS61C L37 VM III (10)
Garcia, Fall 2004 © UCB
4 Qs for any Memory Hierarchy
° Q1: Where can a block be placed?
• One place (direct mapped)
• A few places (set associative)
• Any place (fully associative)
° Q2: How is a block found?
•
•
•
•
Indexing (as in a direct-mapped cache)
Limited search (as in a set-associative cache)
Full search (as in a fully associative cache)
Separate lookup table (as in a page table)
° Q3: Which block is replaced on a miss?
• Least recently used (LRU)
• Random
° Q4: How are writes handled?
• Write through (Level never inconsistent w/lower)
• Write back (Could be “dirty”, must have dirty bit)
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Garcia, Fall 2004 © UCB
Q1: Where block placed in upper level?
°Block 12 placed in 8 block cache:
• Fully associative
• Direct mapped
• 2-way set associative
- Set Associative Mapping = Block # Mod # of Sets
Block
no.
01234567
Fully associative:
block 12 can go
anywhere
CS61C L37 VM III (13)
Block
no.
01234567
Direct mapped:
block 12 can go
only into block 4
(12 mod 8)
Block
no.
01234567
Set Set Set Set
0 1 2 3
Set associative:
block 12 can go
anywhere in set 0
(12 mod 4)
Garcia, Fall 2004 © UCB
Q2: How is a block found in upper level?
Block Address
Tag
Block
offset
Index
Set Select
Data Select
°Direct indexing (using index and block
offset), tag compares, or combination
°Increasing associativity shrinks index,
expands tag
CS61C L37 VM III (14)
Garcia, Fall 2004 © UCB
Q3: Which block replaced on a miss?
°Easy for Direct Mapped
°Set Associative or Fully Associative:
• Random
• LRU (Least Recently Used)
Miss Rates
Associativity:2-way
4-way
Size
LRU Ran LRU
16 KB
64 KB
8-way
Ran
LRU
Ran
5.2% 5.7%
4.7% 5.3%
4.4%
5.0%
1.9% 2.0%
1.5% 1.7%
1.4%
1.5%
256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12%
CS61C L37 VM III (15)
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Q4: What to do on a write hit?
°Write-through
• update the word in cache block and
corresponding word in memory
°Write-back
• update word in cache block
• allow memory word to be “stale”
=> add ‘dirty’ bit to each line indicating that
memory be updated when block is replaced
=> OS flushes cache before I/O !!!
°Performance trade-offs?
• WT: read misses cannot result in writes
• WB: no writes of repeated writes
CS61C L37 VM III (16)
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Three Advantages of Virtual Memory
1) Translation:
• Program can be given consistent view of
memory, even though physical memory is
scrambled
• Makes multiple processes reasonable
• Only the most important part of program
(“Working Set”) must be in physical memory
• Contiguous structures (like stacks) use only
as much physical memory as necessary yet
still grow later
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Three Advantages of Virtual Memory
2) Protection:
• Different processes protected from each other
• Different pages can be given special behavior
-
(Read Only, Invisible to user programs, etc).
• Kernel data protected from User programs
• Very important for protection from malicious
programs  Far more “viruses” under
Microsoft Windows
• Special Mode in processor (“Kernel more”)
allows processor to change page table/TLB
3) Sharing:
• Can map same physical page to multiple users
(“Shared memory”)
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Why Translation Lookaside Buffer (TLB)?
°Paging is most popular
implementation of virtual memory
(vs. base/bounds)
°Every paged virtual memory access
must be checked against
Entry of Page Table in memory to
provide protection
°Cache of Page Table Entries (TLB)
makes address translation possible
without memory access in common
case to make fast
CS61C L37 VM III (19)
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Bonus slide: Virtual Memory Overview (1/4)
°User program view of memory:
• Contiguous
• Start from some set address
• Infinitely large
• Is the only running program
°Reality:
• Non-contiguous
• Start wherever available memory is
• Finite size
• Many programs running at a time
CS61C L37 VM III (20)
Garcia, Fall 2004 © UCB
Bonus slide: Virtual Memory Overview (2/4)
°Virtual memory provides:
• illusion of contiguous memory
• all programs starting at same set
address
• illusion of ~ infinite memory
(232 or 264 bytes)
• protection
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Bonus slide: Virtual Memory Overview (3/4)
°Implementation:
• Divide memory into “chunks” (pages)
• Operating system controls page table
that maps virtual addresses into physical
addresses
• Think of memory as a cache for disk
• TLB is a cache for the page table
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Bonus slide: Virtual Memory Overview (4/4)
°Let’s say we’re fetching some data:
• Check TLB (input: VPN, output: PPN)
- hit: fetch translation
- miss: check page table (in memory)
– Page table hit: fetch translation
– Page table miss: page fault, fetch page
from disk to memory, return translation
to TLB
• Check cache (input: PPN, output: data)
- hit: return value
- miss: fetch value from memory
CS61C L37 VM III (23)
Garcia, Fall 2004 © UCB
Address Map, Mathematically
V = {0, 1, . . . , n - 1} virtual address space (n > m)
M = {0, 1, . . . , m - 1} physical address space
MAP: V --> M U {q} address mapping function
MAP(a) = a' if data at virtual address a
is present in physical address a' and a' in M
= q if data at virtual address a is not present in M
a
Name Space V
Processor
a
Addr Trans 0
Mechanism
a'
physical
address
CS61C L37 VM III (24)
page fault
OS fault
handler
Main
Memory
Disk
OS performs
this transfer
Garcia, Fall 2004 © UCB
And in Conclusion…
°Virtual memory to Physical Memory
Translation too slow?
• Add a cache of Virtual to Physical Address
Translations, called a TLB
°Spatial Locality means Working Set of
Pages is all that must be in memory for
process to run fairly well
°Virtual Memory allows protected
sharing of memory between processes
with less swapping to disk
CS61C L37 VM III (25)
Garcia, Fall 2004 © UCB