Motivation and Project Goals
• Goals:
– Propose an efficient architecture for encoding
and decoding of the LDPC codes, and prove
its feasibility by implementing it on an FPGA.
– Based on the FPGA implementation, gain
insight into the behavior of the LDPC codes at
very low error rates and propose novel
constructions void of error floors.
Low Density Parity Check
Code Representation
Parity Check Matrix
Tanner Graph
V1
1
1
H 
0

1
0 1 0 1 0 1 0
0 0 1 0 1 0 1

1 1 0 0 1 1 0

0 0 1 1 0 0 1
V1 V2 V3 V4 V5 V6 V7 V8
C1
C2
C3
C4
V2
C1
V3
C2
V4
V5
C3
V6
V7
V8
C4
Decoding via Message Passing
bits to checks
checks to bits
bits to checks
…..
v1
P(v1 )
c1
….
P(v2 )
v3
c2
P(v3 )
….
P(v4 )
v5
P(v5 )
….
P(v6 )
c4
….
P(v7 )
c2  v4 
c4  v4 
initialize
v4 HD(v4)=1if
P(v4 )
c3
P(v8 )
v2
  v c
i{1, 6,8}
 v
i{1,5,8}
i
i
2
 c2
c
j{2 , 4}
j
v4  .5
=0 else
v6
v7
v8
v4  c2  P(v4 ) c4  v4
v4  c4  P(v4 ) c2  v4
hard decision
(either all checks
satisfied or
maxIter reached)
An Example: RS-based LDPC*
Construction
1. Shorten a Reed-Solomon code (n=q1,k=q-r+1) into Cb by preserving only
the last two information symbols.
2. Construct Cb(1) as a subcode of Cb
containing all multiples of a c in Cb
whose weight is r.
3. Partition the resulting code Cb into
cosets of Cb(1) ; Cb(2), …, Cb(q).
4. For each coset Cb(j), define a matrix Aj
whose rows are symbol locators of
elements in Cb(j).
5. The resulting parity check matrix is
Properties
•
By construction, there are no
cycles of length 4 and the
minimum distance is large.
•
Each row of H has weight r.
•
Each column of H has weight c.
•
No error floors observed.
H = [A1 … Ac]t
Example: n = 240, m = 8, r = 15, c = 5
*[I. Djurdjevic, IEEE Comm. Letters, Jul. 2003]
Error Floors
• Flattening of a BER-SNR
“waterfall” curve occurs
beyond the reach of a
simulation.
• Usually due to the socalled “near-codewords”,
“trapping sets”, etc.
• Lack of an analytical tool
for describing error floors
for different channels
necessitates the FPGA
implementation.
Simulation and error floor predictions for regular (3,6) LDPC codes
From top: Margulis graph (n=2640), an n=2048 code,
an n=2640 code, and an=8096 code
[T. Richardson, Allerton 2003]
Check and Bit Node
Implementation
•
Using log-domain simplification, node implementations can be simplified.
– Check node: Look up – add – subtract (marginalize) – Look up.
– Bit node: add – subtract (marginalize).
•
Good coding performance can be achieved with arithmetic precision of 3-5
bits only.
– Lookup table can be implemented in simple combinatorial logic.
•
Iteration is terminated when a preset threshold is reached.
[E. Yeo, B. Nikolic, and V. Anantharam, IEEE Comm. Magazine, Aug. 2003]
Fully Parallel Architectures
Check nodes
Direct-mapped architecture
using an interconnect fabric
1 0 0 .. .. .. 1 0 0
0 1 0 .. .. .. 0 1 0
…..
Check
node
0 1 0 .. .. .. 0 0 1
0 0 1 .. .. .. 1 0 0
Bit
node
Interconnects can be simplified
by exploiting the structure of
the code construction
1 0 0 .. .. .. 1 0 0
0 1 0 .. .. .. 0 1 0
0 1 0 .. .. .. 0 0 1
0 0 1 .. .. .. 1 0 0
Check
node
group
…..
Bit nodes
Check node groups
…
n
…
…
n
n
…
n
…..
Bit nodes
Partially Parallel Architecture
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
1
0
1
0
Partition the H matrix into regularly
structured groups by choosing H
that consists of stacked
permutation sub-matrices
Line up check node (horizontal)
and bit node (vertical) groups
Parallel process among multiple
groups and serial process checks
inside the group
Future Research
• Code construction
– Experiment with existing code constructions and
investigate the nature of error floors.
• Architectural exploration
– Flexible and efficient architecture which allows for fast
prototyping of different code constructions.
• Error floor simulation
– Real-time hardware emulation of codes to verify BER
performance.