CALIFORNIA STATE UNIVERSITY NORTHRIDGE

CALIFORNIA STATE UNIVERSITY NORTHRIDGE Testing Framework of Virtex-4 FPGA Burn In board A graduate project submitted in partial fulfillment ofthe requirements Forthe degree of Masters of Science In Electrical Engineering By Parth Patel December 2012 The graduate project of Parth Patel is approved: Dr. Ali Amini Date Dr. Kourosh Sedghisigarchi Date Dr. Ramin Roosta, Chair Date California State University, Northridge ii Acknowledgement It was almost impossible without incredible help and constant encouragement from ECE (Electrical & Computer Engineering Department) faculty members, family and friends. My special thanks to Dr. Ramin Roosta for giving me an opportunity to work under his excellent guidance while giving me an exposure to real world challenges. This experience will lead me to further success in future. Thanks to Dr. Ali Amini and Dr. Kourosh Sedghisigarchi for their guidance and expert advices for making my project work successful. Finally I dedicate this project to my parents Bharat Patel &Varsha Patel and my sister Anna Patel for their endless help to make my graduation successful. I could not expect any better than this. iii Table of Contents Signature Page.....................................................................................................................ii Acknowledgement .............................................................................................................iii List of Figures .....................................................................................................................v Abstract...............................................................................................................................vi CHAPTER 1: Introduction……………………………………………………………….1 CHAPTER 2: History of Burn in Test ………………………………………………...…5 CHAPTER 3: Testing framework ………………………………………………………..7 CHAPTER 4: ML403 evaluation board features…………………………………………9 CHAPTER 5: Testing Chamber Setup…………………………………………………..11 CHAPTER 6: Xilinx Design tools…………………………………………….………...14 CHAPTER 7: HTML Code for testing framwork………………………………………16 CHAPTER 8: Summary and Conclusion………………………………………………..29 REFERENCES………………………………..….…………………………………….30 iv List of Figures Figure1.1 “The Bathtub Curve” [10]………………………………………………...……1 Figure1.2 “Infant Mortality Curve - Failure Rate vs. Time” [10]………………………...2 Figure1.3 Design Overview………………………………………………………….……3 Figure1.4 Design flow……………………………………………………………….……4 Figure2.1 “Virtex 2 FPGA Burn In test Hardware” [1]………………………….……….5 Figure3.1 Testing Framework template…………………………………………………..6 Figure4.1 “ML-403 Xilinx Virtex 4 Evaluation board”……………………………….….9 Figure 5.1 heating oven/chamber………………………………………………………...11 Figure5.2 heating oven/chamber testing space……………………………………….….12 Figure6.1 Xilinx platform studio design settings…………………………………….….14 Figure6.2 Xilinx platform studio component address for mapping ………………….….15 Figure7.1 CMD console ping test to board IP address……………………………….….16 Figure7.2 Testing framework homepage………………………………………………...17 Figure7.3 Testing framework component testing page……………………………….…19 Figure7.4 Testing setting for RAM………………………………………….………..…23 Figure7.5 Testing setting for SRAM………………………………………………….…25 Figure7.6 Testing setting Block RAM…………………………………………………..27 v Abstract Testing Framework of Virtex-4 FPGA Burn In board By Parth Patel Master of Science in Electrical Engineering Virtex-4 PFGA Burn In test is one of the most important tests which determine the overall reliability of FPGA (Field Programmable Gateway Array). The main purpose of the Burn In board is to test Virtex-4 FPGA chip at 125 Degree Celsius, by doing this test we would be determining the performance grade of the FPGA to be successfully usable in Space and Military applications. In order to make test successful it was absolutely necessary to have a framework or a reliable method of getting the test done efficiently. To do so it shall serve a GUI (Graphical User Interface), in overview a GUI in form of a webpage where you can send test vectors and receive it back while burn in board is inside the chamber. This webpage shall be access by any browser and it can be accessed anywhere since it will be internet based. Also this enhances possibilities of future Virtex Series FPGA’s burn in test. vi CHAPTER 1: Introduction Burn in Test Burn in test is the process of determining whether the component will work properly before putting them in service. In this test components are tested at higher temperature to see their ultimate working capabilities. This test will determine which of the system will not work under those higher temperature situations and fail under “bathtub curve” which will be determining chip or any system reliability. [9][10] “Bath Tub Curve” “Bath tub Curve” is being used to determining any products life span or life cycle. It has three major components as per below. 1) “Infant Mortality” 2) “Normal Life (Useful Life)” 3) “End of Life Wear-Out” As shown in figure 1.1 “Bath tub curve” has above mentioned components and how it affects the whole product life cycle or product reliability. [9] [10] Figure 1.1: “The Bathtub Curve” [10] 1 “Infant Mortality” [10] It’s a common problem being occurred in manufacturing of products due to Defect in manufacturing process. It means when product is supplied to customer it is “Dead on arrival”. This problem is totally unaccepted due to leading down customer Satisfaction. In order to resolve this issue following steps should be taken. 1234- Well test product before launching in to market Do stress testing of product to know it’s limit High temperature stress test or “Burn in test” might help knowing product limit Making product to fail at extreme situations will determine product life So by following above stepsproduct manufacturing and test over time should have data as represented in figure 1.2 [10]. Figure 1.2: “Infant Mortality Curve - Failure Rate vs. Time” [10] 2 Burn in test typical setup Burn In test is an environmental test for FPGA chips, to determine the overall redundancy. In burn in test FPGA chips shall be tested at higher temperature ranges around 125 Degree Celsius. While the FPGA is being tested at higher temperature sending test vectors and receiving it back and forth for several hours or sometimes several consecutive days determines that the particular FPGA has passed the burn in test and it’s ready for military and aerospace applications. Figure1.3Design Overview 3 Embedded system Design flow Figure 1.4 represents design flow for any typical embedded system development process. For ease of understating it has been divided in to 4 stages. 1) 2) 3) 4) Design stage Circuit & PCB design stage Software design stage Testing stage All of the above mentioned stages have same importance. Starting from the design stage as you can see the figure 1.4 the application has to be laid out with all necessary peripherals. If it’s an embedded system we decide which microprocessor or microcontroller will be used. All following stages has its own importance in embedded system design process flow as described in figure 1.4. Figure1.4Design flow 4 CHAPTER 2: History of Burn in Test In “California State University Northridge (CSUN)” Burn in test for FPGA series is running from a long time. Around year 2006 some of the Electrical Engineering students started to working on “Burn in test for Virtex 2 FPGA” [1]. The goal was to test FPGA at 125 degree Celsius in an oven for at least 12 hours. At the time of testing a FPGA chip is putted under high stress temperature to verify the overall reliability by sending and receiving test vectors. Any simple circuit like RAM or SRAM can be implemented with VHDL or Verilog code. These circuits should be able to communicate with some kind of communication protocol to be able to record the test vectors and results since it’s a long test and failure could happen any time. Figure 2.1: “Virtex 2 FPGA Burn In test Hardware” [1] Figure 2.1 is a setup of for Virtex 2 FPFA Burn In test explained by “Shant Moses” a previous CSUN(California State University Northridge) student in 2006. [1] Communication with main board and computer should be efficient enough since burn in board circuit will be inside the oven at 125 degree Celsius. Only wires can be pulled out from the heating chamber to send and receive test vectors, to get data about internal and external board temperature using some kind of framework. In the earlier version of the Virtex 2 FPGA testing was successfully done using serial protocol communication with some limitations. Those limitations were testing station has to locally connected, limitation due to length of serial communication for example DB-9 cable cannot be extended more than its standard length, from computer end user has to write a C or C# programming script on top of the developed hardware. Serial communication can be established by UART (Universal Asynchronous Receive and 5 Transmit) protocol or using SPI (Serial Peripheral Interface). Virtex 2 testing was done by UART programing and writing a C# script to have a GUI (Graphical User Interface) [4]. For Virtex 4 series FPGA from Xilinx is the next generation chips, 2 years ago numbers of students started to working on Burn in board with different parts to be implemented. Since circuits will be different than Virtex 2 FPGA Burn in board it was easy to change the testing platform to make it more efficient than the previous generation chips[2] [3] [4] [5]. Instead of Serial peripheral interface I recommended to have an Ethernet Protocol which can be easily replaced on the existing circuit. By adding Ethernet port Virtex 4 Burn in board does not need DB-9 pin port or communication since Ethernet protocol has up to 10GB data transfer receive and sending capacity. Another advantage of Ethernet protocol is once the board is connected through CAT-5 cable to any computer it can be server and any authorized user from anywhere who has internet access will be able to run test and be able to see results, which makes this test enhances mobility and eliminated the local testing set up issue. Furthermore Virtex 4 Burn in board has been designed and verified using PCB and Circuit design Software available in lab,the board is in its final assembly state. We are in the process of getting quotes for assembly and PCB design. When board will become available for testing my framework will be able to test the whole design in the heating oven. The goal of the Virtex 4 burn in board testing is to be able to determine will the FPGA chip survive at 125 degree Celsius so can be used in Aero Space and Military applications without any temperature outage issues [7]. 6 CHAPTER 3: Testing framework Testing framework is an advance way of testing any embedded systems. It provides an automated way of testing platform which is subjected to change in the future. Having testing framework shall help any long term projects to be tested for long time which eliminates human dependencies. For example a platform needs to be tested for continues 60 hours, test vectors and results needs to be stores every few minutes. At this time automated testing framework help makes test very efficient and accurate. Figure3.1 Testing Framework template Figure 3.1 shows basic components of any automated testing framework. The basic component of testing framework is an “Eclipse environment” which can combine hardware components and software components on the same platform. On the top of the “eclipse environment”you need an engine to communicate with external peripherals and logic units. As shown in the figure 3.1to access object repository “eclipse environment” needs to be connects threw the concurrent interface. Once it is connected it can send and receive data in test vector according to the communication protocols. 7 The benefits of having a testing framework are as per below 1) Easily modifiable 2) Automated way of testing any embedded systems 3) Less hardware dependencies 4) Error correction algorithm can save failure of test 5) No human error involved at the time of testing 6) Changing a hardware platform will not affect testing framework 7) Same framework works with other hardware platform with minor changes. Test vectors for this project shall be any small FPGA components for example, 1. SRAM (Serial Random Access Memory) 2. BRAM (Block of Random Access Memory) 3. RAM (Random Access Memory) 8 CHAPTER 4: ML403 evaluation board features This project has been developed on “Xilinx ML403 Evaluation platform” as shown in the figure. It has so many peripherals and features shall be developed for making different applications. Out of all available features this project needs Ethernet port, Serial DB-9 port, JTAGdebugging port, SD card Slot, Expansion headers. Figure4.1 “ML-403 Xilinx Virtex 4 Evaluation board” [6] 1. Ethernet port 2. VIRTEX 4 FPGA 3. Serial port DB-25 4. Serial port DB-9 5. USB A 9 6. JTAG connector 7. SD card slot 8. System selector switch 9. Flash or ACE selector switch 10. Power on /off switch 11. Expansion headers 12. Reset switch 10 CHAPTER 5: Testing Chamber Setup The burn in test will be performed in the oven/chamber shown in the figure below. California State University Northridge has this chamber in FPGA/ASIC lab located in Jacaranda Building. This Chamber has never been operated before so I had an opportunity to make it ready for the test whenever the hardware becomes available. Figure 5.1 heating oven/chamber Figure 5.1 shows oven/chamber has an operating capacity up to 300 degree Celsius,which is more than enough for our purpose since we are testing this for military and aerospace application operating range. The Standard military and aerospace operating range is125 degree Celsius. This chamber has been designed for high temperature stress test so it has upper and back holes to transport the wires through it. As you can see in theFigure 5.1 11 has upper hole which can be sealed with sliding mechanism. We will need to have an Ethernet CAT 5cableto pass through that whole to be attached to the computer. Figure 5.2 heating oven/chamber testing space Figure 5.2 shows space inside the chamber where actual burn in board will be tested. This chamber has automatic timer setting and temperature rising falling with respect to time features. As you can see in the right hand side corner of the chamber a touch screen LCD has been attached to control this oven as per test requirement. 12 In order to be prepared to get ready for final burn in test I run this chamber for short period of this to make sure everything is working and chamber is heating up to required temperature. Also this testing chamber has a GPIB (General Purpose interface bus) connection which can be connected to the computer to automate the operation. Instead of entering manually a lab view code can be written to make the whole testing automated. Lab view automation provides reliable means of testing framework with some extended features. 13 CHAPTER 6: Xilinx Design tools “Xilinx design tools 13.1” or later version is required for this project to work. This design is based on“PowerPC 405 Processor” which is Virtex-4 FPGA Embedded Processor.[8] Figure 6.1 Xilinx platform studio design settings 14 Figure 6.2 Xilinx platform studio component address for mapping 15 CHAPTER 7: HTML Code for testing framwork Figure 7.1 CMD console ping test to board IP address Figure 7.1 is a screen shot of CMD console shows ping test to Virtex 4 Evaluation platform. If you get reply back from the IP address that means Ethernet port and connection has been successfully established. If you get an error message or destination host unreachable message that means connection problem or error. Note: Board IP address shall be assigned as per user’s requirement. 16 Figure 7.2 Testing framework homepage <body bgcolor="silver">     <title></title> <h1 style="text-align: center;"> Testing Framework of Virtex-4 FPGA Burn In Board</h1> 17 Californa State University, Northridge ECE DEPARTMENT By: Parth Patel ID: 103652755 Guided By: Dr. Ramin Roosta     <a href="parth project/PAGE 2.htm">START TEST</a> </body> 18 Figure 7.3 Testing framework component testing page <body bgcolor="silver">         19 <title></title> <h1 style="text-align: center;"> Testing Framework of Virtex-4 FPGA Burn In Board</h1> SAMPLE TESTING COMPONENTS Choose Test Components <table align="center" border="1" cellpadding="1" cellspacing="1" style="width: 750px;"> <tbody> <tr> <td style="text-align: center;"> Component 1</td> <td style="text-align: center;"> Component 2</td> <td style="text-align: center;"> Component 3</td> </tr> <tr> 20 <td style="text-align: center;"> RAM </td> <td style="text-align: center;"> SRAM</td> <td style="text-align: center;"> BLOCK RAM</td> </tr> <tr> <td style="text-align: center;">   <input name="TEST 1" type="button" value="TEST 1" /> </td> <td style="text-align: center;">   21 <input name="TEST 2" type="button" value="TEST 2" /> </td> <td style="text-align: center;">   <input name="TEST 3" type="button" value="TEST 3" /> </td> </tr> </tbody> </table>   </body> 22 Figure 7.4 Testing setting for RAM <body bgcolor="silver">         23 <title></title> <h1 style="text-align: center;"> Testing Framework of Virtex-4 FPGA Burn In Board</h1> Testing Settings For RAM Set time: <input name="RESULT1" type="text" value="" />           Temperature: <input name="RESULT1" type="text" value="" />   <input name="Send Test Vector" type="button" value="Send Test Vector" />   </body> 24 Figure 7.5 Testing setting for SRAM <body bgcolor="silver">         25 <title></title> <h1 style="text-align: center;"> Testing Framework of Virtex-4 FPGA Burn In Board</h1> Testing Settings For SRAM Set time: <input name="RESULT1" type="text" value="" />           Temperature: <input name="RESULT1" type="text" value="" />   <input name="Send Test Vector" type="button" value="Send Test Vector" />   </body> 26 Figure 7.6 Testing setting Block RAM <body bgcolor="silver">         27 <title></title> <h1 style="text-align: center;"> Testing Framework of Virtex-4 FPGA Burn In Board</h1> Testing Settings For BLOCK RAM Set time: <input name="RESULT1" type="text" value="" />           Temperature: <input name="RESULT1" type="text" value="" />   <input name="Send Test Vector" type="button" value="Send Test Vector" />   </body> 28 CHAPTER 8: Summary and Conclusion In conclusion testing framework will be very useful at the time of actual testing stage since it has all necessary components implemented for testing needs. Replacing the UART (Universal Asynchronous Receiver and Transmit) framework to Ethernet 10/100 GB transmission protocolhas made the testing very handy and easy. It will be very easy for user to access the framework or getting testing results anywhere any time since it can be access online using particular IP address. Testing results can be stored in a word or excel file format and can be imported to any platform or software since they are standard formats. When working on this testing framework at the time of testing, it had not been provided enough security while accessing on line or over the network. It is recommended that network IP address should be only provided to limited know users. It can obviously affect the testing result and may damage the running hardware platform. Another solution shall be to prevent the security and privacy of test it is recommend adding some network level security framework then it will have no issues or possible threat of misuse. 29 REFERENCES [1] Moses, S (2006). An automated high temperature stress testing of FPGAs using a Dynamic burn-in platform Retrieved March 2012 from DR. RaminRoosta [2] Bermudez, J Design and Implementation of a Burn in Board for Xilinx Virtex-4 FPGA Retrieved March 2012 from DR. RaminRoosta [3] Ponce, R Virtex 4 LX200 Automated Temperature Stress Test Serial Interface and Test Control Logic Design Implementation Retrieved March 2012 from DR. RaminRoosta [4] Savra, R. Dynamic Burn-in Test of Xilinx Virtex-4 FPGA Software Application Retrieved March 2012 from DR. RaminRoosta [5] AliteaLaya Ramos, Bram & DSP Design Configuration for Burn-In Test of Virtex-4 FPGA Retrieved March 2012 from DR. RaminRoosta [6] http://www.xilinx.com/support/documentation/boards_and_kits/ug080.pdf Retrieved March 2012 [7] http://www.landandmaritime.dla.mil/downloads/milspec/docs/mil-std883/std883.pdf Retrieved April 2012 [8] http://www.xilinx.com/support/documentation/application_notes/xapp434.pdf Retrieved April 2012 30 [9] http://en.wikipedia.org/wiki/Burn-in Retrieved Nov 2012 [10] Dennis J. Wilkins, ―The Bathtub Curve And Product Failure Behavior Part One—The Bathtub Curve, Infant Mortality And Burn-In,‖ ReliabilityHotwire, Issue 21, November 2002.http://www.weibull.com/hotwire/issue21/hottopics21.html Retrieved Nov 2012 31

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