CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
HARDWARE ACCELERATION OF SOLAR IMAGE PROCESSING ON FPGA
A graduate project submitted in partial fulfillment of the requirements for the degree of
Master of Science in Electrical Engineering
By
Akhila Hegde
December 2015
SIGNATURE PAGE
The graduate project of Akhila Hegde is approved:
_____________________________________
___________________
Dr. George Law
Date
_____________________________________
___________________
Dr. Ramin Roosta
Date
_____________________________________
___________________
Dr. Shahnam Mirzaei, Chair
Date
California State University, Northridge
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ACKNOWLEDGEMENTS
I would like to express my gratitude to Dr. Shahnam Mirzaei for being my graduate advisor at
California State University, Northridge. His encouragement and invaluable inputs were helpful
in successful completion of the project. I would like to thank Dr. George Law and Dr. Ramin
Roosta for their extended support and scholarly advice during the course which was very helpful
for this project. My thanks extend to Peter Littlewood for his advice during the course of this
project.
Lastly, to my husband and to my family, for their encouragement and support.
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TABLE OF CONTENTS
SIGNATURE PAGE
ii
ACKNOWLEDGEMENTS
iii
LIST OF FIGURES
vi
viii
ABSTRACT
1
2
3
1.1
Background
1
1.2
Existing method of processing data
1
1.3
Objective
4
5
DESIGN DESCRIPTION
2.1
Design Flow and High Level Design
5
2.2
Image Processing
6
2.2.1
Cross Correlation
7
2.2.2
Auto Correlation
9
11
SYSTEM RESOURCES
3.1
Zynq7
11
3.2
Clock
13
3.3
Processor System Reset
13
3.4
Memory Units
13
3.4.1
DDR
14
3.4.2
Quad SPI Flash
15
3.4.3
BRAM
16
3.5
4
1
INTRODUCTION
18
AXI Interfaces
3.5.1
Working of AXI
18
3.5.2
AXI BRAM Controller
19
3.6
DMA Controller
20
3.7
Interrupts
22
3.8
Timer
23
3.9
UART
25
3.10
Hardware
28
3.11
Software Tools
29
IMPLEMENTATION OF THE DESIGN ON FPGA
iv
31
5
6
4.1
Project Settings
31
4.2
Block Design
31
4.3
Hardware Setup
35
37
RESULTS AND ANALYSIS
5.1
Reading image data from Host PC to FPGA
37
5.2
Spansion Quad SPI Flash Read/Write
38
5.3
Data Transfer between Flash (PS) and BRAM (PL)
39
5.4
Comparison between DMA and Processor data transfers
41
5.5
Integration of Custom IP
42
5.6
Processing Time
43
45
CONCLUSION
REFERENCES
46
APPENDIX A
47
APPENDIX B
50
v
LIST OF FIGURES
Figure 1-1 Group of Sunspots (Image captured by NASA in July 2010)
Figure 1-2 Sunspot image using IDL
Figure 1-3: Intensity vs. Wavelength waveform
Figure 1-4: Data vector of 255 values
Figure 2-1: Design Flow
Figure 2-2: High Level Design of System
Figure 2-3: Data curve compared with reference curves
Figure 2-4: Sample data curve and reference curve
Figure 2-5: Cross correlation of sample data curve and reference curve
Figure 2-6: Auto Correlation of reference curve
Figure 3-1: DQS-Clock Delay Settings
Figure 3-2: Board Delay Settings
Figure 3-3: Block Diagram of True Dual Port BRAM
Figure 3-4: Channel Architecture for read
Figure 3-5: Channel architecture for write
Figure 3-6: AXI BRAM Controller Module
Figure 3-7: Block Diagram of DMA Controller
Figure 3-8: Block diagram of Interrupt system
Figure 3-9: System view of all timers
Figure 3-10: Block diagram of UART module
Figure 3-11: Transmitted data stream
Figure 3-12: Receiver data stream
Figure 3-13: Re synchronized received data
Figure 3-14: USB-UART Bridge Interface on Zed Board
Figure 3-15: Block Diagram of Zed Board
Figure 4-1: Project Settings
Figure 4-2: Implemented Block Design
Figure 4-3: Zynq Block Design
Figure 4-4: Configuration of AXI BRAM Controller
Figure 4-5: Configuration of BRAM Memory Generator
Figure 4-6: Hardware Setup using Zed Board
Figure 5-1: Serial port connection with FPGA (USB-UART)
Figure 5-2: Data file read from Host PC and stored in FPGA Flash
Figure 5-3: Xilinx Library to use Spansion Flash
Figure 5-4: Flash Memory Settings for Zed Board
Figure 5-5: Flash write operation
Figure 5-6: Flash read operation
Figure 5-7: Flash data copied to DDR Memory
Figure 5-8: Data transfer from DDR to BRAM using Processor
Figure 5-9: Data transfer from DDR to BRAM using DMA
Figure 5-10: Comparison of DMA and Processor data transfers
Figure 5-11: Data read from Custom IP block
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43
LIST OF TABLES
Table 3-1: Features of Z7020 SoC
Table 3-2: DDR3 Pin Connections
Table 3-3: Quad SPI Pin Connections
Table 3-4: USB-UART Bridge Interface Connections
Table 3-5: Software Listing
Table 3-6: IP CORE Listing
vii
13
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30
ABSTRACT
Hardware Acceleration of Solar Image Processing on FPGA
By
Akhila Hegde
Master of Science in Electrical Engineering
The images of sunspots on the surface of the sun were captured and processed using software.
This processed data, based on pre-obtained reference values, was used to forecast the weather
conditions. The image processing done using software only was very slow. The aim of this
project was to accelerate solar image processing using available FPGA resources. A proof of
concept is provided here by implementing a System on chip design on FPGA. This system reads
the image data (in the form of intensity vector with 255 values) from the PC, stores the data in
the memory, and processes it using the available DSP resources for fast computations. The
model provided here can be further extended to achieve processing of solar images of large
number of pixels in real time.
viii
1
1.1
INTRODUCTION
Background
Sunspots are the small dark spots seen around the surface of the sun. These spots are due to the
phenomena of the photosphere that change invariably in time. They are concentrations of flux
(magnetic field) and have lesser surface temperature compared to other regions of photosphere
[1]
. The emergence and decay of sunspots vary based on the solar cycle. Lifetime of a sunspot
may vary from days to months and they decay eventually. Sunspots (shown in Figure 1-1) can
be observed using land based telescopes and earth orbiting telescopes.
Figure 1-1 Group of Sunspots (Image captured by NASA in July 2010)
As the sunspot occurrence is linked to solar activity, this phenomenon is useful in predicting
space weather, ionosphere state, satellite communications, etc. So these sunspots are observed
for a longer time period and useful data is collected for further applications [2].
1.2
Existing method of processing data
The images of sunspot are observed and captured using telescopes and cameras in the
observatory. Each image is of dimension 280 x 229. This image of 280 x 229 is mapped to be a
data cube with each point in the image representing a vector of 255 data values in the data cube
as shown in Figure 1-2. These values are plotted to get intensity vs. wavelength curve
corresponding to each vector. A software named IDL is used to get this vector in the form of
waveform which is a plot of intensity versus waveform.
Image file in .sav format is input to the program which is executed using IDL.exe. This program
“Read_IntensityVector.pro” given in APPENDIX A, decodes the values present in the .sav file
and opens the corresponding sunspot image as shown in Figure 1-3 IDL0 window. When the
.sav file is read from the IDL, 64,120 blocks are written to the text file. Each block has 255
values.
Figure 1-2 Sunspot image using IDL
In Figure 1-2, the cube has 3 dimensions. Two dimensions of the cube are the 2-D coordinates of
the 280 x 229 image. The third dimension is the projection through that 2D point in terms of
wavelength. The red dot highlighted in the image is projected as the red vector in the data cube.
So this point in the image is the vector equivalent in the data cube.
Once the IDL0 window is open, to obtain the intensity vector for a particular spot, click on that
spot on the sunspot image. The selected point on the image is circled in red in Figure 1-3.
2
Corresponding Intensity versus wavelength waveform obtained for the red point in IDL0 is also
shown in Figure 1-3. Thus the curve can be obtained for any point on the image.
Corresponding waveform
Figure 1-3: Intensity vs. Wavelength waveform
Sample data vector obtained from the IDL software is shown in Figure 1-4. It is a vector of 255
integer values. Data vector to be processed is written to a text file and given input to the image
processing program.
Figure 1-4: Data vector of 255 values
A set of reference vectors (17,000 approx.) are stored in the system initially. Each reference
element used is a vector of 255 values. A data curve is read from the program and some
3
calculations are performed using software instructions. The result is compared with these set of
reference values to find the closest match. The current calculation is,
∑
)
))
where D is the data curve and R is the reference curve with 255 values each. X is the result.
This calculation is carried out for 17000 reference values. Each data curve is compared with all
the reference curves from the reference library. The minimal value, Min_Value (X) is found
which the best match is. The corresponding reference value is used for further applications
related to forecasting the weather conditions, satellite communications, etc.
1.3
Objective
The existing method of image processing explained in Section 1.3 uses only software
instructions for processing the images. Hence, the process is slow. It takes approximately 7 hours
to process an image of 229 x 228 with 64,120 blocks of data vectors. The objective was to speed
up this process of processing the image data.
The proposal is presented here to speed up image processing that
exploits the hardware
characteristics of Avnet Zed board (Zynq Evaluation and Development board) which has a
hardcore dual Cortex ARM 9 processor on the Processing System side and DSP resources on the
Programmable logic side. The image data is read from the PC and processed using DSP
resources. Cross correlation and Auto correlation techniques are used to find the best match.
Proof of concept is provided for a small data set that can be further extended for large set of data
values. With this implementation, the speed of calculation for a 280 x 229 image was reduced to
3 hours.
4
2
2.1
DESIGN DESCRIPTION
Design Flow and High Level Design
The system comprises of several blocks that perform different operations to achieve the objective
of speeding up the image processing. The design flow of the system consists of following steps:
 The data vector which is read from the IDL software is stored in a text file.
 These values are read from the PC and stored in the memory.
 The reference vectors are stored in the Flash Memory as they are constants and are used
every time the image processing is performed.
 The data curve (255 bytes long) and the reference curve (255 bytes long) are processed
and the closest match is found. This reference vector which matches the data vector is
displayed.
This design flow of the system is shown in Figure 2-1 below:
Figure 2-1: Design Flow
5
High level design of the system is shown in Figure 2-2. It consists of various modules in the PS
and PL sides of the Zed Board. The Image data is read from the Host PC through UART module.
Since reference vectors are constants, they are stored in Flash Memory. The data vectors are
stored in on chip memory on the PS side. The reference and data vectors are transferred to PL
side by AXI Interconnect block. Data is buffered in Block RAM memory for further processing.
The image processor block reads the data from the BRAM module and processes it. The result is
written to the BRAM module which is sent to PS side through AXI Interconnect. From the PS, it
is sent to the Host PC through UART module.
Figure 2-2: High Level Design of System
2.2
Image Processing
The data curve has to be compared with all the reference curves in the library. Closest match is
found among all the reference vectors and the result is returned to the user application. This idea
is shown in Figure 2-3. The data curve represents a point on the solar image of dimensions 280 x
229. Each point on the image is compared with every reference values present in the library. The
reference vector which is the closest match is found.
The data curve from solar image shown in Figure 2-3 is simulated using Matlab 7.8.0. The data
vectors are read from the .sav file using the squeeze function and the waveform is plotted for an
arbitrary vector with the x and y coordinates being [100, 100]. The values from 1:255 are plotted
for this particular point in the image. Similarly, the waveform can be obtained for any arbitrary
6
point on the image. This data curve is compared with reference curves Ref 1 to Ref n where n is
17000 vectors approximately.
Figure 2-3: Data curve compared with reference curves
To find the closest match few techniques of Digital Signal Processing are used. Cross
Correlation and Auto Correlation are applied on the data curve and reference curve. Signal
processing is done in the time domain. A comparator is used to compare all the values obtained
as a result of this processing and a maximum value is found. This is the minimal distance of the
data vector to the reference vector and hence the respective reference vector is selected as the
closest match [3].
2.2.1 Cross Correlation
Cross correlation is a digital signal processing technique used to estimate the degree of
correlation between any two signals. It is a measure of how closely two given signals are related.
Cross correlation is also referred to as sliding dot product. It measures the similarity between two
signals as a function of lag of one signal relative to the other signal. It is similar in nature to
convolution of two signals. Cross correlation between two signals x[n] and y[n] is given as:
)
∑
)
)
7
)
∑
)
)
where r(x, y) is the result of cross correlation and l is the delay.
In this design it is used in the image processing to find the closest match of the data vector with a
reference vector. A plot of sample of a data curve and a reference curve is as seen in Figure 2-4.
The x coordinate and y coordinate of data vector are [100, 100] and another data vector with x
and y coordinates [10, 10] is considered to be a reference vector. Both the curves are plotted
using Matlab 7.8.0. The curve with green dotted lines represents the reference curve. The curve
with blue line is the data curve.
Figure 2-4: Sample data curve and reference curve
The two signals shown in Figure 2-4 are cross correlated and the result is shown in Figure 2-5.
The maxima which is seen at 280, is a useful factor to be considered for the design here. Since
we have to find the highest correlated reference vector, the maxima is stored for further
processing.
8
Figure 2-5: Cross correlation of sample data curve and reference curve
2.2.2 Auto Correlation
Auto Correlation is another technique in digital signal processing defined as the cross correlation
of the signal with itself. The maximum value is obtained when the signal is at zero lag with itself.
And the size of the peak will be the signal power. The auto correlation of a signal x[n] is given
as:
)
∑
)
∑
)
)
)
)
where r(x, x) is the result of auto correlation and l is the delay.
The auto correlation of a reference cube with x and y coordinates [10, 10] was simulated using
Matlab. The result is shown in Figure 2-6. The peak value of auto correlation of reference vector
is subtracted from the peak value of the cross correlation of data curve and reference curve. This
operation is done for each reference vector. The maximum value found is the closest match. The
corresponding reference vector is the result we are looking for. Also, these auto correlation
results of all the reference vectors can be stored in the memory along with the reference vectors
as they are constants and do not change for any value of data vector.
9
Figure 2-6: Auto Correlation of reference curve
The result of auto correlation of reference vector is subtracted from the maximal value of the
cross correlation result of data curve and reference curve for normalization. The minimal of the
differences is considered to be the closest match [4].
10
3
3.1
SYSTEM RESOURCES
Zynq7
Zynq7 comprises of Processing System (PS) with two processor cores of ARM Cortex A9 [5] and
Xilinx programmable logic (PL), which is has features of low power consumption and high
performance. It also has high metal gate process technology. It has both on-chip and external
memory and consists of several on-board peripherals. Various devices in Zynq7 family help
designer to develop a cost effective and high performance applications. During booting, the
processors are booted first and then the PL system is booted and configured. This allows a
software centric approach. The PL can either be configured during boot process or configured in
future. It can be reconfigured completely or used with partial reconfiguration and dynamic
reconfiguration. We can configure a portion of PL by using partial reconfiguration (PR). The PL
configuration data is referred to as bit stream. The PS side and PL side are operated by different
power domains which enable the user of Zynq7 family devices to shut down the PL side only if
required for power management. The Zynq-7000 AP contains several blocks which perform
major functionalities: Processing System (PS), Interconnect, Programmable Logic (PL),
Application processor unit (APU), I/O peripherals (IOP), Memory interface.
Processing System (PS) Features [6]:
 Application Processor Unit (APU): it provides very high performance feature.
 Dual Core CPUs; ARM Cortex-A9 MP Core
Programmable Logic (PL) is from the Xilinx 7 series FPGA technology. To meet the custom
configurations and requirements we use the PL.
PL resources are:
 Configurable Logic Block (CLBs)
 Block RAM (BRAM) (port and widths can be configured)
 DSP slices with 25x18 multiplier
 48-bit pre-adder and Accumulator
 Analog to digital convertor (XADC)
 Clock management tile (CMT)
11
The PS and PL are coupled together using various sources if required. The PS I/O uses
multiplexed I/O pins. I/O’s from PL domain can be accessed from PS side using extended
multiplexed input/output interface known as EMIO. Zynq-7000 AP device has this capability.
The system includes high level of security, debugging and testing features. Elements of the board
are described with respect to the Processing System. For instance, a general purpose master
interface means the PS is the master and slave resides in the PL and the vice versa.
Memory Interfaces: Zynq 7000 family includes various memory technologies.
 DDR Controller
 DDR Controller Core and Transaction Scheduler
 Quad-SPI Controller
 Static Memory Controller (SMC)
I/O Peripherals
 GPIO
 Gigabit Ethernet Controllers (Two)
 Two USB Controllers (Host, Device or On The Go)
 SD/SDIO Controllers (Two)
 SPI Master and Slave Controllers
 Two CAN Controllers
 UART0 and UART1 Controllers
 I2C Controllers (two)
 PS MIO I/Os
It also has PS-PL interfaces and the AXI Data path switch interconnects.
The PS and PL features of Z7020 device used for the project are listed in Table 3-1.
12
Table 3-1: Features of Z7020 SoC
3.2
Clock
The Zed Board Z7020 embedded processing platform (EPP) device PS subsystem uses a
dedicated 33.3333 MHz clock source (IC18 Fox oscillator 767- 33.333333-12) with series
termination. Four PLL-based clocks can be generated in the PS, which can be used by PL
system. PL subsystem clock input (bank 13, pin Y9) is supplied by an on-board 100 MHz
oscillator (IC17 Fox 767-100-136).
3.3
Processor System Reset
Power-on reset (PS_RST/BTN7) is designed so as to erase all the configurations of debugging
sessions. The functional logic can be reset without effecting the debug environment using
external system reset. System reset erases all memory content (including on-chip memory) due to
security concerns. PL section is also reset in system reset. Boot mode strapping pins are not resampled by system reset.
3.4
Memory Units
Zynq contains a memory interface unit which is hardened to the Zed board. This unit consists of
static memory interface modules and the dynamic memory controller. The memory units present
13
on the PS side are the DDR memory and the Flash memory. Block RAM can be used to buffer
the data on the PL side.
3.4.1 DDR
Zed Board has two Micron MT41K128M16HA-15E:D DDR3 memory modules. This creates an
interface of 32-bit. This DDR3 memory component and the hard memory controller module are
connected in the Processor System. The DDR memory controller (multi-protocol) is configured
such that a 32-bit wide access is provided to a 512 MB address space. Processor System consists
of the DDR controller and its associated PHY. It also includes its own set of dedicated I/O pins.
The speeds up to 533 MHz/1066 Mbs are supported for DDR3 memory interface. It uses 1.5V
SSTL compatible inputs. Zed Board also utilizes DDR3 termination. The EPP module and
DDR3 module are placed close enough to keep traces short and matched.
The Settings for DQS to clock delay and DDR3 board delay are shown in Figure 3-1 and Figure
3-2 respectively.
Figure 3-1: DQS-Clock Delay Settings
Figure 3-2: Board Delay Settings
The pin connections for DDR3 module is shown in the Table 3-2.
14
Table 3-2: DDR3 Pin Connections
3.4.2 Quad SPI Flash
The 4-bit SPI (Quad SPI) Spansion S25FL256S module available on the Zed Board is used for
the design implemented here. The Multi-I/O Flash memory provides a non-volatile storage of
data and code. It can also be used to configure the PS and PL sections of the Zed Board during
booting. The Spansion provides file system which is Spansion Flash File System [7].
The SPI Flash has following features:
 Total memory of 256Mbit
 It supports x4, x2, and x1
 It can speed up to 104 MHz. This enables Zynq7 to configure at the rate of 100 MHz
 It is powered from 3.3V source
 Vivado Design Suite 14.x and later versions can be used for indirect Flash Programming
Boot Mode jumpers share the Quad SPI data and clock pins. The connections of Quad SPI Flash
are shown in the Table 3-3.
15
Table 3-3: Quad SPI Pin Connections
3.4.3 BRAM
Every design needs memory for storage of buffering data, coefficients, and many other use cases.
Complex system needs small, medium and large memory arrays to meet all their requirements,
with the concern of power consumption from memory units. Hence FPGA is a primary choice.
Various application uses variety of memory units and of different sizes of Xilinx FPGAs to have
flexibility and low cost. Xilinx 7 series FPGA is facilitated to create Block RAM that can either
made by combining blocks together to make large array or divide to make smaller memory
arrays. Xilinx 7 series FPGA uses 6 input look up table (LUT) as small memory arrays and
provides the user the most flexible resources to form various size of memory arrays [8].
Different types of configurations of BRAMs are possible in the FPGA of the Zed Board. Every 7
series FPGA has 135 to 1889 dual port block RAMs, each capable of storing 36Kb. 32 Kb is
allocated to store data and 4Kb is allocated to parity bits. There are two independent ports in
block RAM that share the stored data. Each port can be configured as 32Kx1, 16Kx2, 8Kx4,
4Kx9, 2Kx18, 1Kx36 and 512x72.
Each block RAM can be divide into two 18Kb block RAMS. It is formed from splitting 36Kb
block RAM into two. Each of the two 18Kb block RAM work exactly like 36Kb block RAM. If
user requires larger memory block then two 36Kb blocks can combine to form 64Kx1 dual port
RAM without requiring to use additional logic. In Xilinx 7 series FPGA block RAM components
can be configured three ways:
 Single-Port Block RAM
o Single read/write port
o 36K bit configurations (32Kx1, 16Kx2, 8Kx4, 4Kx9, 2Kx18, 1Kx36)
16
o 18K bit configurations (16Kx1, 8Kx2, 4Kx4, 2Kx9, 1Kx18, 512x36)
o Configurable write mode

WRITE_FIRST: data written on DIA is available on DOA

READ_FIRST: old contents of RAM at ADDRA is presented on DOA

NO_CHANGE: the DOA holds its previous value
 Dual-Port Block RAM
o Two separate read/write ports, with different write modes
o Two ports can have different widths
o No contention avoidance when both the ports access the same address, except
when clocked by the same clock and write port being READ_FIRST, the read
port gets the old data value
 Simple Dual-Port block RAM
o One read and one write port
For the purpose of this design, true dual port Block Ram is used. This Block RAM operates in
BRAM Controller Mode. Based on the sized configured, Block RAM are assigned from the pool
of BRAM FPGA resources.
Figure 3-3: Block Diagram of True Dual Port BRAM
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3.5
AXI Interfaces
AXI stands for Advance Extensible Interface (AXI) protocol. It is mainly targeted for the Xilinx
intellectual property (IP). This feature was introduced in Xilinx from the Spartan-6 and vertex-6
devices. AXI is a part of ARM Advance Microcontroller Bus Architecture (AMBA) and was
first introduced in 2003. The advanced version of it is AXI4.
3.5.1 Working of AXI
Basically AXI is an interface to exchange the information between an AXI master and an AXI
slave. The structure called an interconnect block used to connect memory mapped AXI master
and slave. . The Interconnect IP for AXI is defined in Xilinx AXI Interconnect Core IP. It
consists of five different channels: Read Address Channel, Read Data Channel, Write Data
Channel, Write Address Channel and Write Response Channel.
This is bidirectional interface between an AXI master and an AXI slave simultaneously, and the
size of data can also be different. AXI4 is limited to 256 data transfer of burst transaction. The
AXI4-Lite which occupies lesser memory than the AXI4 allows only 1 data transfer per
transaction.
Channel Architectures of Read and Write are shown in Figure 3-4 and Figure 3-5 respectively.
Figure 3-4: Channel Architecture for read
18
Figure 3-5: Channel architecture for write
Simultaneous and bidirectional data transfer is possible in AXI4 because it provides separate
data and address connection. A single address can burst up to 256 words of data in AXI4. AXI4
protocol has verity of option to achieve very high data throughput. Few of them are data
downsizing and upsizing, out of order transaction processing and multiple outstanding addresses.
It has different clock for AXI master and slave. AXI protocol supports pipeline stages to
maintain timing closure. That means protocol allows the insertion of register slices.
The bursting is not supported in AXI4-lite all other features of AXI4 supported by AXI4-lite.
AXI4-Stream channel supports burst for unlimited amount of data but AXI4-Stream transfers
cannot be reordered like AXI4.
3.5.2 AXI BRAM Controller
AXI BRAM controller is soft core IP which are comestible Xilinx Vivado Design Suite,
Embedded Development kit. It is design as endpoint AXI slave to communicate with local block
RAM by integrating with AXI interconnect and system master devices. Single and burst
transactions to block RAM both are supported by the core for better performance.
Main module of the AXI BRAM controller and port connections are shown in Figure 3-6. It
supports several instantiation mode based on connection and BRAM module. By setting the
19
parameter we can utilize a single port Block RAM module or a dual port Block RAM. All
communications performed with AXI master port via five channel AXI interface. Write Address
Channel (AW) of the AXI bus used for all write operations. This channel is used to specify the
type of write transaction and corresponding address information. The single and burst write
operation for the communication uses Write Data Channel (W). The Write Response Channel
(B) is used to get handshaking signal or response signal or acknowledgment signal. When AXI
master sends a request for a read transfer BRAM controller uses the Read Address Channel (AR)
for read operation. The BRAM controller which is an AXI slave responds to the request on Read
Address Channel (AR). When the read data is available to be sent back to the AXI master, it is
the responsibility of the Read Data Channel (AR) to translate the data and status of the operation.
Figure 3-6: AXI BRAM Controller Module
3.6
DMA Controller
DMA controller is used while moving large amount of data without processor intervention. It can
transfer data from memory which can be anywhere in the system like to/from system memories
and PL peripherals. Here DMA Controller works on clock_2x clock frequency and uses 64 bit
20
AXI master interface. Data transfer using DMA and the management of control system related
instructions are contained in instruction set of DMA engine [9].
DMA controller can have eight DMA channels and it is configurable. Memory requests are
pushed to the appropriate write or read queue by the DMA engine. DMA controller has
multichannel FIFO to store data during read and write transaction. It has two sets of status
register and control register, each set works in separate modes like one works in secure mode and
another works non – secure code moreover this register are accessible through software. The
DMA controller block diagram is shown in Figure 3-7.
Figure 3-7: Block Diagram of DMA Controller
DMA instruction Execution engine: this block controls process program code which includes a
DMA transmission.
Instruction cache: cache is used to store instruction temporarily and cache performs a look up
when any thread requests to fetch an instruction stored in the memory.
Read/Write instruction Queues: this queues has been using to as a storage buffer prior to issue
transmission on AXI. The controller adds relevant read or wright queue when a channel thread
executes load or store instruction.
21
Multi-channel data FIFO: MFIFO is used as a data buffer to store data that it reads or writes
during DMA transmission.
Interrupt interface: enables efficient communication between DMAC and interrupt controller.
PL peripheral DMA interface: PL peripheral request is asynchronous to the DMA and supports
the connection of DMA peripherals in PL.
3.7
Interrupts
The block diagram of Interrupt system is shown in Figure 3-8. The Zed Board processing system
(PS) has two ARM Cortex A9 processors. For interrupts handling it has a pl390 Generic
Interrupt Controller (GIC). Structure of the interrupts is closely linked to the ARM architecture
and the interrupts from I/O peripherals and the interrupts from the Programmable Logic (PL)
side are accepted by the processors.
Figure 3-8: Block diagram of Interrupt system
There are three types of interrupts as shown in Figure 3-8. They are private peripheral interrupts
(PPIs), software generated interrupts (SGIs) and shared peripheral interrupts (SPIs). Both the
ARM processors have their own sets of private peripheral interrupts (PPIs). These PPIs can be
accessed privately using banked registers. The PPIs comprise of:
 Global timer
 Private watchdog timer
22
 Private timer
 FIQ/IRQ from the PL
Software generated interrupts are asserted by configuring the register ICDSGIR in the generic
interrupt controller. The I/O pins and peripherals on the PS and PL sides generate SPIs. These
SPIs and SGIs can be routed to either or both CPUs. The SPIs generated on the PS side can be
routed to PL as well.
The Generic Interrupt Controller is the centralized module which handles all the interrupts. It
comprises of two major modules: Interrupt Controller CPU (ICC) and the Interrupt Controller
Distributor (ICD). The two main tasks of GIC are controlling the interrupts and distributing the
interrupts to the CPUs. It manages the interrupts sent from the PS and PL to the CPUs. It controls
asserting and de asserting of the interrupts. They can also be assigned priorities. Interrupts can be
masked by the GIC. This controller has the “ARM Generic Interrupt Controller Architecture”
version 1.0. It is non-vectored type.
Every interrupt source has a unique interrupt ID assigned to it. The priority and the target CPUs
can be configured for every interrupt source. The ICC and ICD have different sets of registers to
handle the interrupts. The three main aspects of the interrupts that has to be handled by the GIC
are sensitivity, handling and target CPU. The ICDICFR register controls the sensitivity and the
handling of the interrupts. The ICDIPTR register handles the target CPUs of the interrupt
sources.
3.8
Timer
The two Cortex A9 Processors have private 32 bit timer and 32 bit watch dog timer. Both
processors use a common 64 bit global timer. All these timers work at half the CPU frequency.
Global Timer is a 64 bit increment counter with auto increment property. Global timer always
clocks at half the CPU frequency. Private timer and watchdog timer, 32 bit timers, generate an
interrupt when their values reach zero. One of the features of private timer is configurable
starting value for counter. This timer works in two modes which are single shot or auto reload
mode. The interconnections of all the timers of the system are shown in Figure 3-9.
23
Figure 3-9: System view of all timers
At system level there are one 24 bit watch dog timer and two 16 bit triple timers / counters. The
system watchdog timer and triple timer work on 1/4th or 1/6th of the CPU frequency. These
timers can also be clocked by external signal from an MIO pin. Along with two 32 bit CPU
private timers, it also has one system watchdog timer which is mostly used to signal catastrophic
system failure. SWDT as 24 bit internal counter and it can select input from PL bus clock or
from internal or external clock. When a timeout occurs, its output is one or both of reset or
interrupts to system. One more feature is programmable timeout and programming output
duration on timeout. Example: timeout range is 32760 to 68719476735 clock cycles. System
interrupt duration can be programmed for 4, 8, 16 or 32 clock cycles. Signal restart will reload 24
bit counter and restart counting.
There are three independent Triple Timer Counters (TTC) counters/timers. All of them have 16
bit pre scales and 16 bit up/down counters. Input clock from internal or external clock or internal
PS clock bus can be the input. All the counters have individual interrupts. This interrupt can be
on overflow, at regular interval or on matched counting value. Through MIO and to PL it can
also generate waveform output (PWM). This counter can count up or down and configurable
count for given interval.
24
Triple Timer counter works on two modes interval mode or overflow mode. In interval mode the
counter continuously increments or decrements in between 0 to value in internal register. Every
time when count passes zero or match register it generates interval interrupt. While in overflow
mode the counter counts between 0 and 0xFFFF and direction of counting is determined by DEC
bit of counter control register. This will generate interrupt when count value passes match
register.
3.9
UART
UART- Universal Asynchronous Receiver and Transmitter is a full duplex communication
protocol that supports a large range of programmable baud rates. UART controller also has some
more features like automatic parity generation and multi-master detection mode. It is designed
with two separate paths for transmission and reception. Each path contains a 64- byte FIFO.
Serialization and de-serialization of data in TX FIFO and Rx FIFO is done by the controller.
Status, interrupt status and modem status register are used to read states of FIFOs, modem signal
and other controller function. The UART functions are controlled by mode register and
configuration register.
The block diagram of UART is shown in Figure 3-10. APB bus is used for communication
between the controller and APU. The data which are arrives through system memory stored in
Transmit FIFO and the received data will be stored in the Receive FIFO. Control logic selects
various operation modes. It contains control register and Mode register. The baud rate generator
generates a clocking at proper frequency division (baud rate clock) for transmitter and receiver.
It can generate a baud rate of 600, 9600, 28800,115200, 230400, 460800, 921600 using UART
ref clock.
Maximum data width for the transmit FIFO is 8 bit, we can load data in transmit FIFO by writing
the TX FIFO reg. Transmit FIFO is used to store the data from the APB interface until it is
loaded into shift register. TX Empty flag will clear and remains low when Transfer FIFO is
loaded with data. So the software can write to TX FIFO when this flag goes high after all data
has been removed from the register. Interrupt status register shows that TX FIFO is completely
full and will not allow any additional data in Transmit FIFO; moreover nearly full flag indicates
only one byte available for being loaded in FIFO.
25
Figure 3-10: Block diagram of UART module
Receiver FIFO also has eight bit data width. It receives data by receiver serial shift register. RX
FIFO has the same characteristics as TX FIFO like receive data full flag and RX FIFO full status
register prevent any further data into RX FIFO if it is full.
There are 4 operating modes: Normal mode, Automatic echo mode, local loopback mode and
remote loopback mode. These modes decide the routing of transmit and receive signals in the
controller. Transmission and Reception of data in UART is shown in figures from Figure 3-11 to
Figure 3-14.
Transmitter module gets data in parallel from TX FIFO and stores it into transmitter shift register
to make it serialized. Transmitter shifts out start, data, parity and stop bits as a serial data as
shown in Figure 3-11. At every falling edge of TX baud rate enable data is transmitted and it
transmits LSB first.
Figure 3-11: Transmitted data stream
26
We can adjust number of data bits and number of set bits to transmit using mode register bits
CHRL (char length) and NBSTOP respectively. Software can use polling or interrupt methods to
transmit data. Number of data bits and number of set bits to transmit can be configured using
mode register bits CHRL (char length) and NBSTOP respectively. Software can use polling or
interrupt methods to transmit data.
UART samples the rxd signal with reference to baud_sample and clock enable. The low level
transaction indicates the beginning of start bit as shown in Figure 3-12. It waits for BDIV/2 baud
rate clock cycle and sample rxd for three times to get a valid start bit.
Figure 3-12: Receiver data stream
Re synchronization of baud rate clock enable is needed for next sampling of rxd as shown in
Figure 3-13. When baud_rx_rate goes high, last three bits are compared and if two samples have
same defined value then its defined as data bits, after this all data is shifted to the shift register
and then to the Rx FIFO.
Figure 3-13: Re synchronized received data
Receiver generates parity error when received parity is not matched with the one in mode
register. The receiver also generates framing error when it receives invalid stop bit. If Rx FIFO is
full and receiver gets a start bits then it will generate receiver overflow error.
27
The USB-to-UART bridge interface present on the Zed Board is shown in Figure 3-14. It is
connected UART1, PS UART peripheral. A host computer is connected using Cypress
CY7C64225 USB-to-UART Bridge device. Basic TXD and RXD connections are implemented.
The MIO [48:49] are assigned to UART1 PS peripheral.
Figure 3-14: USB-UART Bridge Interface on Zed Board
The pin connections for Cypress USB-UART Bridge interface is given in Table 3-4.
Table 3-4: USB-UART Bridge Interface Connections
3.10 Hardware
System on Chip device used for the project is of Xilinx Zynq-7000 series. The board is known as
the Zed Board which stands for Zynq Evaluation and Development Board. This board uses Zynq
SoC XC7Z020-1CSG484CES EPP which is a combination of dual core Arm Cortex 9 Processor
(known as Processing System) and 85,000 Series 7 Programmable Logic Cells (known as PL).
PS and PL are interfaced by AXI4 interface which is proprietary of Xilinx. It is a standard
interface which is used in the newer generations of IP cores by Xilinx. AXI4 interface is used in
the design since this System on chip design requires implementation of the logic on both PS and
PL sides [10].
The block diagram of the Zed Board is shown in Figure 3-15. Zed board has a large number of
on board peripherals. These peripherals are distributed on PS and PL sides. Few peripherals can
28
be accessed only from the PS and others from the PL. For the purpose of this project, UART, On
board oscillators (33.33 MHz clock for PS and 100 MHz clock for PL), QSPI Flash memory and
DDR on chip memory are used. The PROG LED indicates whether the board is programmed or
not.
Figure 3-15: Block Diagram of Zed Board
The hardware resources required for this project is the Zed Board Evaluation Kit from Avnet
manufacturer. The two micro USB cables are used to program the FPGA and talk to the UART
on PS side respectively.
3.11 Software Tools
Xilinx Vivado Design Suite 2015.2 is used to implement the design which is targeted for Zynq
SoC xc7z020clg484-1 part. The Vivado Design Suite software development kit (sdk) is used to
program the PS. IDL software is used to get the data vectors from the solar image. Tera term
software, which is a terminal emulator application, is used to transfer the image data from the PC
to the Zed Board through Serial Port connections. The software resources and their versions used
are listed in Table 3-5:
29
Software Tool
Version
Vivado Design Suite Web Pack
2015.2
Tera Term
4.88
IDL
5.0
Table 3-5: Software Listing
Vhdl Hardware Description Language is used for implementation of this System on Chip design.
This design can be implemented in Verilog Hardware Description Language as well. Xilinx IP
cores are used from the catalog for the implementation. This is a limitation of the design for
porting it to different FPGA technology or to ASIC. IP Cores used (from Xilinx) in the design
are listed in Table 3-6.
IP Core
Version
Zynq7 Processing System
5.5
Processor Reset System
5.0
AXI Interconnect
2.1
AXI BRAM Controller
1.0
Block Memory Generator
8.2
Table 3-6: IP CORE Listing
A Custom IP is created for the Image Processor so as to integrate the implemented vhdl files
with the rest of the system. The Custom IP is a block which is built with the image processing
logic so as to run on Programmable Logic clock of 100 MHz. It is connected to the Xilinx IP
Cores in the Block Design for the FPGA. A common vhdl wrapper is generated for the entire
design and used to Program the FPGA.
30
4
4.1
IMPLEMENTATION OF THE DESIGN ON FPGA
Project Settings
The proposed design is implemented on the FPGA using Vivado Design Suite 2015.2 tool.
Available Xilinx IP cores are added from the IP Catalog as per the requirements of the design. A
Custom IP is created and integrated with the Xilinx IP Core to be able to interface implemented
PS and PL modules. The project settings are as shown in Figure 4-1.
Figure 4-1: Project Settings
The project is targeted for Zynq 7020 EPP (xc7z020clg484-1) available on the Zed Board. The
target language used for the implementation of the design is VHDL Hardware Description
Language. Verilog can also be used to implement this design. Xilinx default library
(xil_defaultlib) is the default library for this design. After integrating all the IP cores (Xilinx IP
cores and the Custom IP), a vhdl wrapper is generated which is useful for generating the bit
stream to program the Zed Board PS and PL FPGA.
4.2
Block Design
The Block Design for the project is shown in Figure 4-2. It consists of Zynq7 Processing System,
Processor System Reset, AXI Interconnect, AXI BRAM Controller, Block Memory Generator
and the Image Processor blocks. The connections between the Xilinx IP Cores can be done
automatically by selecting connection automation option. Manual connections have to be done
31
for Custom IP Cores. PS side operates on 33.33 Hz clock. PL operates on 100 MHz clock which
is the FCLK_CLK0 in the Block Design. BRAM and Image Processor block reside on the PL
side while the others are on PS side.
Figure 4-2: Implemented Block Design
Processor System Reset block provides a global system reset for the AXI interconnects and the
Peripherals. Interconnect_aresetn and peripheral_aresetn are used to reset axi_mem_intercon and
axi_bram_ctrl_0. Clock input and reset input for this module is from the Processing System.
Zynq7 Processing System is configured as shown in Figure 4-3. The modules used are
highlighted in green. In I/O Peripherals UART0 is used to send/receive data to/from Host PC.
Quad SPI Flash provides non-volatile data storage capability. Reading the reference vectors from
the Host PC every time the device is powered on is cumbersome. As these reference vectors are
constant values, they are stored in Quad SPI Flash permanently. This reduces the overhead of
dealing with large set of reference vectors every time the device is powered on. Timer module is
used to keep track of the time spent for different operations so as to measure the system
performance. It also helps find the bottle necks of the design in terms of speed. DMA controller
32
module is used to transfer the data from PS to PL without interrupting the processor. This
transfer is faster than the normal transfer of data from PS to PL using the processor. The
comparison of time taken between data transfers with and without DMA is discussed in Results
and Analysis section of the document. For large data sets DMA is preferred.
Figure 4-3: Zynq Block Design
Since DMA Controller is operated in Interrupt mode, GIC module is used to handle the interrupt
enabling and disabling during the DMA operations. DDR Memory module is used to buffer the
data while sending it to PL BRAM memory from PS Flash memory.
The AXI Interconnect block provides interface between the PS and PL sides. It acts as an AXI
slave with respect to the processor and as an AXI Master with respect to the AXI BRAM
Controller. The M00_AXI master port of axi_mem_intercon block is connected to S_AXI slave
port of axi_bram_ctrl_0 block.
33
AXI BRAM Controller block is uses AXI4 Protocol. The configurations of this module for the
purpose of the project are shown in Figure 4-4. Data width is 32 bits. Memory depth was set to
2048 based on the configuration of the Block Memory Generator block. This is configurable up
to 18K. Support AXI Narrow Bursts is set to Manual as this is the necessary configuration for
data transfer using DMA controller. Only one port (PORTA) is used. This port is accessed by the
Block RAM Generator module to get the PS data.
Figure 4-4: Configuration of AXI BRAM Controller
Block RAM memory generator module generates the BRAM blocks required by the project. This
is on PL side. BRAM FPGA resources are inferred for this block. The configurations of this
block are shown in Figure 4-5. The BRAM blocks generated is of type True Dual Port RAM.
Dual Port RAM was selected so as to read the data from Port A and Port B for the DSP
computations on the PL side. Currently, Port A is used by the BRAM Controller module to write
image data from the PS, while data is read from Port B to the PL side. Port A and Port B write
and read widths are set to 32 bits. Write Depth is set to 8192 bits. It can be configured from 2
bits to 1048567 bits. The operating mode of the BRAM is Write First mode.
34
Figure 4-5: Configuration of BRAM Memory Generator
Image processor block is a Custom IP created for this project and integrated with Xilinx IP
Cores. To create a Custom IP, implemented vhdl modules are integrated and synthesized. A
wrapper is created after synthesis. Using the Review and Package IP option, the wrapper is
packed as an IP and Custom name is given to this IP. If the package was successful the IP
appears in Xilinx IP catalog. Custom IP can be used across the projects easily by instantiating
from the IP catalog. In this project the Image Processor IP was created and instantiated in the
block design. This module comprises of the DSP computation modules behaviorally modeled
using VHDL language. The buffered data from the BRAM is read from Port B. The
computations on this data are done and the result is stored back to the BRAM. This result is read
from the PS through AXI Interface and displayed on the terminal for the user to read.
4.3
Hardware Setup
The hardware used for the design is Zed Board Evaluation Kit. The board is interfaced with the
host PC using micro USB cables. The hardware setup for this project is shown in Figure 4-6. The
35
power cable of 12 V is connected to the board. A switch next to the power cable has to be in ON
position to power on the device. Micro USB cable connected to PROG slot is for programming
the FPGA with the generated bit stream. The other micro USB cable is connected to the UART
slot. This facilitates the UART communication between the device and the host PC.
Figure 4-6: Hardware Setup using Zed Board
36
5
RESULTS AND ANALYSIS
The implementation of the proposed design was accomplished in steps. Every new module added
to the existing design was tested thoroughly at module level and system level. This helped to
design a complex design efficiently. The debugging and testing of the System on Chip was easy.
5.1
Reading image data from Host PC to FPGA
First step of the project was to transfer the image data file present on Host PC to FPGA. This was
accomplished using Tera term application. Serial port connection is established with the FPGA
UART Port as shown in Figure 5-1. Baud rate is set to 115200.
Figure 5-1: Serial port connection with FPGA (USB-UART)
Once the serial port setup is successful, the file is sent from the Host PC to FPGA using Send
File option. For testing purpose, a file named IntegerDataValues.txt shown in Figure 5-2 was
sent to the FPGA to store in Flash memory. These data values were successfully read from Flash.
Results are presented in section 5.2.
Figure 5-2: Data file read from Host PC and stored in FPGA Flash
37
5.2
Spansion Quad SPI Flash Read/Write
To use the on board Spansion Flash memory, xilsif library has to be included in the Board
Support Package Settings as shown in the Figure 5-3. This library has the functions provided by
Xilinx to initialize flash memory, read/write data from/to flash memory.
Figure 5-3: Xilinx Library to use Spansion Flash
Flash memory settings for Zed Board are shown in Figure 5-4. The value 5 for
serial_flash_family indicates it is Spansion Flash. Quad SPI interface is assigned value 3.
Figure 5-4: Flash Memory Settings for Zed Board
The data from the file given in Figure 5-5 was written to Flash Memory. The result of write
operation is shown in Figure 5-6. To verify write operation, read operation was performed. The
data written to Flash was successfully read. This verifies the Read/Write operation of Flash
Memory.
38
Figure 5-5: Flash write operation
Figure 5-6: Flash read operation
5.3
Data Transfer between Flash (PS) and BRAM (PL)
The data written to the Flash memory was read after powering off and restarting the Zed Board.
This verified the nonvolatile data storage capability of Spansion Flash memory present on Zed
Board. The data read from the terminal of Vivado sdk is shown in Figure 5-7. This data is copied
39
to the DDR memory. The data is then transferred from the DDR memory on the PS side to the
BRAM memory on the PL side.
Figure 5-7: Flash data copied to DDR Memory
The data from PS was transferred to PS using two methods, one using DMA and the other using
the Processor. Data transfer of 255 bytes using the processor is shown in Figure 5-8.
Figure 5-8: Data transfer from DDR to BRAM using Processor
40
This data transfer took 16283 clock cycles. The data written to the BRAM in the PL side was
verified by reading the BRAM memory contents.
In the second method of data transfer, DMA Controller was used to transfer the data to the
BRAM Memory. The GIC interrupt controller was used to handle the interrupts required for
DMA operation. The data transfer of 255 values was verified by reading the data written to the
BRAM memory as shown in the Figure 5-9.
Figure 5-9: Data transfer from DDR to BRAM using DMA
These methods verified that a path existed between PS and PL which can be used for transferring
large data values from PS to PL. This is required in many applications which do heavy
computations because the PL with its rich DSP resources can perform the computations much
faster.
5.4
Comparison between DMA and Processor data transfers
The two methods of data transfers from DDR memory to BRAM memory using DMA and
Processor are compared. Using Processor only, the data transfer of 255 bytes of data took 16283
41
clock cycles. Same data transfer took 1526 clock cycles using DMA Controller. 10 x
improvements were seen. The results of comparison between the two methods are shown in
Figure 5-10. Hence, the preferred choice for transferring large data would be using DMA
Controller.
Figure 5-10: Comparison of DMA and Processor data transfers
5.5
Integration of Custom IP
Various experimentations were done to find a path between PS and PL domains. The PS system
was created using the available Xilinx IP cores for the processing system and the memory
modules as per the requirements of the design. For this purpose, a vhdl module was behaviorally
modeled and synthesized. A Custom IP core was created with this synthesized design and
instantiated in the PS side. It was shown that the Custom IP was able to communicate to PS side
and display the data on the terminal. The results of a BRAM IP implemented in vhdl are shown
in the Figure 5-11.
42
Figure 5-11: Data read from Custom IP block
5.6
Processing Time
The processing time for the solar image processor will be:
PS Clock = 33.33 MHz, PL = 100 MHz.
The total samples are 17000 * 280 * 230 data vectors. Each data vector is of length 256 bytes.
While calculating the processing time on PL side, the factors to be considered are:
time to populate the registers (td), time to calculate correlation (tc) and time to fill registers with
0’s (tz).
PL logic has to be implemented for a full image such that:
PL processing time = (td + tc + tz) * 17000 * 280*230/ 100 MHz
PL processing time = (256+256+256) *17000 * 280*230/ 100 MHz
PL processing time = (256+256+256) *17000 * 280*230/ 100 MHz
43
PL processing time = 2.33 hours
It is seen from Section 5.4 that PS takes 1526 cycles to transfer 256 data values to PL. So for
writing the data to PL and reading the data from the BRAM, approximately 0.4 hours can be
allocated. The software cycles are not very accurate.
So the processing time will be 3 hours (approx.).
44
6
CONCLUSION
As per the analysis presented in section 5, the design was implemented and tested using Zed
Board hardware successfully. The desired results were obtained. Hence the objective of the
project was achieved. Apart from developing a system for producing desired results, different
skills were developed during the course of this project which can be used for designing complex
systems in the future. Familiarization with different design tools such as Vivado Design Suite,
Vivado SDK, Matlab, IDL, Tera term, etc. The process of designing a complete System on Chip
design and testing it on the hardware and the challenges seen during the course of the project
have enhanced the knowledge and expertise in this field which will be of great importance in the
future projects.
45
REFERENCES
1. Moon K. R., Li J.J., Delouille V., Watson F., Hero A.O., “Image patch analysis and
clustering of sunspots: A dimensionality reduction approach”, 27-30 Oct. 2014
2. Colak T., Qawahji R., “Automatic Sunspot Classification for Real-Time Forecasting of
Solar Activities”, 14-16 June 2007
3. C. T. Johnston, K. T. Gribbon, D. G. Bailey, “Implementing Image Processing Algorithms
on FPGAs”, Reasearch gate net publication
4. Ridha Djemal, Didier Demigny and Rached Tourki, “A Real-time Image Processing with
a Compact FPGA-based architecture”, Journal of Computer Science 1 (2): 207-214, 2005
5. Rich Nass, "Xilinx puts ARM core into its FPGAs", EE Times April 27, 2010
6. "The Vivado Design Suite accelerates programmable systems integration and
implementation by up to 4X.", EDN, Jun 15, 2012.
7. Xiaohu Wang, Zhaoming Huang, “Design and implementation of high speed QSPI
memory controller”, 14394679
8. Xinrui Zhang, Jian Wang, Yuan Wang, Dan Chen, Jinmei Lai, “BRAM-based
asynchronous FIFO in FPGA with optimized cycle latency”, 13357105
9. Tumeo, A., Monchiero M., Palermo G., Ferrandi F., Sciuto, D., “Lightweight DMA
management mechanisms for multiprocessors on FPGA”, 2-4 July 2008
10. Brent Przybus, Xilinx, "Xilinx Redefines Power, Performance, and Design Productivity
with Three New 28 nm FPGA Families: Virtex-7, Kintex-7, and Artix-7 Devices." June
21, 2010.
46
APPENDIX A
Extracting Solar Image Data Vector
1. Read_IntensityVector.pro
;
;
;
;
;
;
;
Engineer: Akhila Hegde
Created Date: 06/12/2015
Filename: Read_IntensityVector.pro
Software Version Used: IDL 5.0
Description: This file reads the solar image stored in the .sav file format and generates the
solar image in a window. When any point on the image is clicked, it displays the intensity vs.
wavelength waveform curve for that point on the solar image.
pro Read_IntensityVector
restore,"..\iDL_images\oct16_5172_map04i.sav"
image_size = size (BIG_ARR_I)
print, size (BIG_ARR_I)
window,0,xsize = image_size(2),ysize = image_size(3)
tvscl,big_arr_i(10,*,*)
print,big_arr_i(*,5,5)
counter = 0
loop:
counter = counter + 1
wset,0
cursor,x,y,/device,/up
user
print,x,y
waveform
window,1,xsize=500,ysize=500
plot,big_arr_i(*,x,y)
waveform
if (counter eq 10) then goto, stop
goto, loop
stop:
end
47
; read solar image .sav file
; store the size of the Image
; print the size of the Image
; open window to display Image
; display image
; get the coordinates of the point the
; clicks on Image to get intensity
; plot the intensity vs. wavelength
; repeat for 10 points
2. Text_IntensityVector.pro
;
;
;
;
;
;
;
Engineer: Akhila Hegde
Created Date: 06/12/2015
Filename: Text_IntensityVector.pro
Software Version Used: IDL 5.0
Description: This file reads the solar image stored in the .sav file format and generates the
ASCII equivalent data. It stores these ASCII data to the text file. The data in the text file
can be processed later.
pro Text_IntensityVector
; read solar image file of .sav format
restore,'../iDL_images/oct16_5172_map04i.sav', /VERBOSE
; open the file where solar image data has to be stored in write mode
openw, 1, '../iDL_output/ImageData.txt'
; write the data to the text file
printf, 1, BIG_ARR_I
;close the file
close, 1
end
48
3. Solar Image data written to text file ImageData.txt
49
APPENDIX B
Source Code:
50
51
52
53
54
55
56
The Xilinx in-built Library functions are used where ever necessary.
SolarImageprocessing_wrapper.vhd
57
58
AXI Memory Interconnect IP Core:
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------Tool Version: Vivado v.2015.2 (win64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
--Date
: Thu Nov 12 12:35:40 2015
--Host
: Akhila running 64-bit major release (build 9200)
--Command : generate_target Solar_Image_Processing.bd
--Design
: Solar_Image_Processing
--Purpose : IP block netlist
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_D51E3L is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
59
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_D51E3L;
60
architecture STRUCTURE of s00_couplers_imp_D51E3L is
component test_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
61
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component test_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
62
signal auto_pc_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal auto_pc_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_pc_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_pc_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_pc_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(12 downto 0) <= auto_pc_to_s00_couplers_ARADDR(12 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_s00_couplers_ARCACHE(3 downto 0);
63
M_AXI_arid(11 downto 0) <= auto_pc_to_s00_couplers_ARID(11 downto 0);
M_AXI_arlen(7 downto 0) <= auto_pc_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_pc_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(12 downto 0) <= auto_pc_to_s00_couplers_AWADDR(12 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(11 downto 0) <= auto_pc_to_s00_couplers_AWID(11 downto 0);
M_AXI_awlen(7 downto 0) <= auto_pc_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_pc_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wlast <= auto_pc_to_s00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BID(11 downto 0) <= M_AXI_bid(11 downto 0);
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RID(11 downto 0) <= M_AXI_rid(11 downto 0);
auto_pc_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
64
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component test_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arid(11 downto 0) => auto_pc_to_s00_couplers_ARID(11 downto 0),
m_axi_arlen(7 downto 0) => auto_pc_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_pc_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_auto_pc_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_pc_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_pc_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_s00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_s00_couplers_AWCACHE(3 downto 0),
m_axi_awid(11 downto 0) => auto_pc_to_s00_couplers_AWID(11 downto 0),
m_axi_awlen(7 downto 0) => auto_pc_to_s00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_pc_to_s00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_auto_pc_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_pc_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_pc_to_s00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bid(11 downto 0) => auto_pc_to_s00_couplers_BID(11 downto 0),
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rid(11 downto 0) => auto_pc_to_s00_couplers_RID(11 downto 0),
m_axi_rlast => auto_pc_to_s00_couplers_RLAST,
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wlast => auto_pc_to_s00_couplers_WLAST,
65
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity test_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
66
M00_AXI_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
67
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end test_axi_mem_intercon_0;
architecture STRUCTURE of test_axi_mem_intercon_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
68
signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal s00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal s00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(12 downto 0) <= s00_couplers_to_axi_mem_intercon_ARADDR(12 downto 0);
M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(11 downto 0) <= s00_couplers_to_axi_mem_intercon_ARID(11 downto 0);
M00_AXI_arlen(7 downto 0) <= s00_couplers_to_axi_mem_intercon_ARLEN(7 downto 0);
M00_AXI_arlock(0) <= s00_couplers_to_axi_mem_intercon_ARLOCK(0);
M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= s00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(12 downto 0) <= s00_couplers_to_axi_mem_intercon_AWADDR(12 downto 0);
M00_AXI_awburst(1 downto 0) <= s00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= s00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(11 downto 0) <= s00_couplers_to_axi_mem_intercon_AWID(11 downto 0);
M00_AXI_awlen(7 downto 0) <= s00_couplers_to_axi_mem_intercon_AWLEN(7 downto 0);
69
M00_AXI_awlock(0) <= s00_couplers_to_axi_mem_intercon_AWLOCK(0);
M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awsize(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= s00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= s00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= s00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
M00_AXI_wlast <= s00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
M00_AXI_wvalid <= s00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_mem_intercon_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= axi_mem_intercon_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_mem_intercon_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= axi_mem_intercon_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_mem_intercon_to_s00_couplers_WREADY;
axi_mem_intercon_ACLK_net <= M00_ACLK;
axi_mem_intercon_ARESETN_net(0) <= M00_ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_mem_intercon_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
axi_mem_intercon_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
s00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
s00_couplers_to_axi_mem_intercon_BID(11 downto 0) <= M00_AXI_bid(11 downto 0);
s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
70
s00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
s00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_axi_mem_intercon_RID(11 downto 0) <= M00_AXI_rid(11 downto 0);
s00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
s00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_D51E3L
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(12 downto 0) => s00_couplers_to_axi_mem_intercon_ARADDR(12 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(11 downto 0) => s00_couplers_to_axi_mem_intercon_ARID(11 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_axi_mem_intercon_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_axi_mem_intercon_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(12 downto 0) => s00_couplers_to_axi_mem_intercon_AWADDR(12 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(11 downto 0) => s00_couplers_to_axi_mem_intercon_AWID(11 downto 0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_axi_mem_intercon_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_axi_mem_intercon_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => s00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(11 downto 0) => s00_couplers_to_axi_mem_intercon_BID(11 downto 0),
M_AXI_bready => s00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
M_AXI_rid(11 downto 0) => s00_couplers_to_axi_mem_intercon_RID(11 downto 0),
M_AXI_rlast => s00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => s00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
M_AXI_wlast => s00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => s00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(3 downto 0) => s00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => axi_mem_intercon_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0),
71
S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => axi_mem_intercon_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_mem_intercon_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => axi_mem_intercon_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => axi_mem_intercon_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => axi_mem_intercon_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => axi_mem_intercon_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s00_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity test is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
72
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of test : entity is "test,IP_Integrator,{x_ipProduct=Vivado
2015.2,x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=test,x_ipVersion=1.00.a,x_ipLanguage=VH
DL,numBlks=8,numReposBlks=6,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,da_axi4_cnt=1,da_bram_
cntlr_cnt=1,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of test : entity is "test.hwdef";
end test;
architecture STRUCTURE of test is
component test_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
73
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component test_processing_system7_0_0;
component test_axi_bram_ctrl_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
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s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component test_axi_bram_ctrl_0_0;
component test_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component test_rst_processing_system7_0_100M_0;
component test_axi_bram_ctrl_0_bram_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component test_axi_bram_ctrl_0_bram_0;
component test_Image_Processor_0_0 is
port (
clock : in STD_LOGIC;
resetn : in STD_LOGIC;
datain : in STD_LOGIC_VECTOR ( 31 downto 0 );
75
enable : out STD_LOGIC;
we : out STD_LOGIC_VECTOR ( 3 downto 0 );
address : out STD_LOGIC_VECTOR ( 16 downto 0 );
dataout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component test_Image_Processor_0_0;
signal GND_1 : STD_LOGIC;
signal Image_Processor_0_address : STD_LOGIC_VECTOR ( 16 downto 0 );
signal Image_Processor_0_dataout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Image_Processor_0_enable : STD_LOGIC;
signal Image_Processor_0_we : STD_LOGIC_VECTOR ( 3 downto 0 );
signal VCC_1 : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_ADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_CLK : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_DIN : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_bram_ctrl_0_BRAM_PORTA_EN : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_RST : STD_LOGIC;
signal axi_bram_ctrl_0_BRAM_PORTA_WE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_bram_ctrl_0_bram_doutb : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
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signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
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signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_bram_ctrl_0_bram_addrb_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 17 );
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0
to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0
to 0 );
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of axi_bram_ctrl_0 : label is "byte 0x40000000 32 > test
axi_bram_ctrl_0_bram";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of axi_bram_ctrl_0 : label is "yes";
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of processing_system7_0 : label is "ARM > test axi_bram_ctrl_0";
attribute KEEP_HIERARCHY of processing_system7_0 : label is "yes";
begin
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
Image_Processor_0: component test_Image_Processor_0_0
port map (
address(16 downto 0) => Image_Processor_0_address(16 downto 0),
clock => processing_system7_0_FCLK_CLK0,
datain(31 downto 0) => axi_bram_ctrl_0_bram_doutb(31 downto 0),
dataout(31 downto 0) => Image_Processor_0_dataout(31 downto 0),
enable => Image_Processor_0_enable,
resetn => processing_system7_0_FCLK_RESET0_N,
we(3 downto 0) => Image_Processor_0_we(3 downto 0)
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
axi_bram_ctrl_0: component test_axi_bram_ctrl_0_0
port map (
bram_addr_a(12 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_ADDR(12 downto 0),
bram_clk_a => axi_bram_ctrl_0_BRAM_PORTA_CLK,
bram_en_a => axi_bram_ctrl_0_BRAM_PORTA_EN,
bram_rddata_a(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DOUT(31 downto 0),
bram_rst_a => axi_bram_ctrl_0_BRAM_PORTA_RST,
bram_we_a(3 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_WE(3 downto 0),
bram_wrdata_a(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DIN(31 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(12 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(12 downto 0),
s_axi_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
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s_axi_arid(11 downto 0) => axi_mem_intercon_M00_AXI_ARID(11 downto 0),
s_axi_arlen(7 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(7 downto 0),
s_axi_arlock => axi_mem_intercon_M00_AXI_ARLOCK(0),
s_axi_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
s_axi_arready => axi_mem_intercon_M00_AXI_ARREADY,
s_axi_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
s_axi_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
s_axi_awaddr(12 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(12 downto 0),
s_axi_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => axi_mem_intercon_M00_AXI_AWID(11 downto 0),
s_axi_awlen(7 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(7 downto 0),
s_axi_awlock => axi_mem_intercon_M00_AXI_AWLOCK(0),
s_axi_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
s_axi_awready => axi_mem_intercon_M00_AXI_AWREADY,
s_axi_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
s_axi_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
s_axi_bid(11 downto 0) => axi_mem_intercon_M00_AXI_BID(11 downto 0),
s_axi_bready => axi_mem_intercon_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_mem_intercon_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => axi_mem_intercon_M00_AXI_RID(11 downto 0),
s_axi_rlast => axi_mem_intercon_M00_AXI_RLAST,
s_axi_rready => axi_mem_intercon_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_mem_intercon_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
s_axi_wlast => axi_mem_intercon_M00_AXI_WLAST,
s_axi_wready => axi_mem_intercon_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_mem_intercon_M00_AXI_WVALID
);
axi_bram_ctrl_0_bram: component test_axi_bram_ctrl_0_bram_0
port map (
addra(31) => GND_1,
addra(30) => GND_1,
addra(29) => GND_1,
addra(28) => GND_1,
addra(27) => GND_1,
addra(26) => GND_1,
addra(25) => VCC_1,
addra(24) => GND_1,
addra(23) => GND_1,
addra(22) => GND_1,
addra(21) => GND_1,
addra(20) => GND_1,
addra(19) => GND_1,
addra(18) => GND_1,
addra(17) => GND_1,
addra(16) => GND_1,
addra(15) => GND_1,
addra(14) => GND_1,
addra(13) => GND_1,
addra(12 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_ADDR(12 downto 0),
addrb(31 downto 17) => NLW_axi_bram_ctrl_0_bram_addrb_UNCONNECTED(31 downto 17),
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addrb(16 downto 0) => Image_Processor_0_address(16 downto 0),
clka => axi_bram_ctrl_0_BRAM_PORTA_CLK,
clkb => processing_system7_0_FCLK_CLK0,
dina(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DIN(31 downto 0),
dinb(31 downto 0) => Image_Processor_0_dataout(31 downto 0),
douta(31 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_DOUT(31 downto 0),
doutb(31 downto 0) => axi_bram_ctrl_0_bram_doutb(31 downto 0),
ena => axi_bram_ctrl_0_BRAM_PORTA_EN,
enb => Image_Processor_0_enable,
rsta => axi_bram_ctrl_0_BRAM_PORTA_RST,
rstb => processing_system7_0_FCLK_RESET0_N,
wea(3 downto 0) => axi_bram_ctrl_0_BRAM_PORTA_WE(3 downto 0),
web(3 downto 0) => Image_Processor_0_we(3 downto 0)
);
axi_mem_intercon: entity work.test_axi_mem_intercon_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(12 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(12 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(11 downto 0) => axi_mem_intercon_M00_AXI_ARID(11 downto 0),
M00_AXI_arlen(7 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock(0) => axi_mem_intercon_M00_AXI_ARLOCK(0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(12 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(12 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(11 downto 0) => axi_mem_intercon_M00_AXI_AWID(11 downto 0),
M00_AXI_awlen(7 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock(0) => axi_mem_intercon_M00_AXI_AWLOCK(0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(11 downto 0) => axi_mem_intercon_M00_AXI_BID(11 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(11 downto 0) => axi_mem_intercon_M00_AXI_RID(11 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
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S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
processing_system7_0: component test_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
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DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED
);
rst_processing_system7_0_100M: component test_rst_processing_system7_0_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
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dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
The IP Core was used from the vivado IP Catalog in Vivado Design Suite which is from Xilinx.
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