Computer Organization and Architecture - Definitions Functional levels Definition of Computer Architecture Computer Systems Organization – Basics: •Processors; •Main Memory; •Secondary Memory; •Peripherals: graphical, audio, printers; •Networking. Dr.Iliya Georgiev 1 6/21/2016 Functional levels diagram (T fig.1-2) Problem-oriented language level Translation Assembly Language level Operating System Machine Level Partial Interpretation Instruction Set Architecture Level Micro architecture Level Digital Logic Level Microprogram Interpretation Hardware Digital Logic Level Based on the Boolean algebra Gates: AND, OR, XOR,… Digital Devices: coder, decoder, latch, memory element,… Implementation: - mostly by electronic devices; - weird: pneumatic devices,… Dr.Iliya Georgiev 3 6/21/2016 Microarchitecture Level Arithmetic Logic Unit Register Block (File) Memories (cache, Main) Information Path Control: - microoperations and micro programs; - finite state machine. Dr.Iliya Georgiev 4 6/21/2016 Instruction Set Architecture Level Instruction Set Data Formats Principles of Operations Dr.Iliya Georgiev 5 6/21/2016 OS Machine Level Virtual Memory BIOS Virtual Instructions Virtual Machine Idea Process and Treads Management Virtual Instruction Set for Networking or Parallel Processing Dr.Iliya Georgiev 6 6/21/2016 Assembly Language level Assembler language is a symbolic form of machine language together with some macroinstructions and procedures. Programs can be written for lower levels with full access to the computer resources. Compiler from assembly programs is called Assembler. Dr.Iliya Georgiev 7 6/21/2016 Problem-oriented language level High level languages: Programming languages (Java, C++, Lisp, Prolog, Pascal, Fortran,…); Data description languages (HTML, XML,…). Procedural Languages (so called scripts) – Java script, VB script, … Dr.Iliya Georgiev 8 6/21/2016 Computer Architecture – classical definition Data Formats Instruction Set Principle of Operation (textual or formal description of every operation) Features (virtual memory, direct memory access, interrupt mechanism, etc.) Dr.Iliya Georgiev 9 6/21/2016 Some historical architecture terms 1. Von Neumann architecture (both programs and data are stored in the same memory)-T fig.1-5 CPU (mill) Memory (programs + data) 2. Harvard architecture CPU Program memory Data Memory Dr.Iliya Georgiev 10 6/21/2016 Computer Structure: Digital Blocks and Devices: processor, memories, display (video) subsystem, hard drives, CD drives, etc. Data Buses Interfaces (serial, parallel, LAN,…) Dr.Iliya Georgiev 11 6/21/2016 Computer Structure CPU1 CPU n Main Memory LAN System Bus (Hierarchy of Buses) Disk Controller Video Subsystem Interfaces Audio Parallel Serial (LPT) (COM) Dr.Iliya Georgiev 12 6/21/2016 CPU Executes programs stored in the main memory by fetching their instructions, examining them,and then executing one after another. Every CPU has its unique instruction set. According to the instruction sets and other features two types are recognized: - RISC (Reduced Instruction Set Computer); - CISC (Complex Instruction Set Computer); Dr.Iliya Georgiev 13 6/21/2016 CPU blocks Processing Block ALU Registers Control Unit Control Signals Clock Clock Generator Signals Dr.Iliya Georgiev 14 6/21/2016 CPU Performance Measurement (all in metric system) MIPS – million instructions per second (usually integer arithmetic operations as well load/store instructions are considered) MFLOPS – million floating point operations per second (one floating point instruction combines several operations) Dr.Iliya Georgiev 15 6/21/2016 CPU Clock as performance measurement Main formula: f [Hz]= 1 / T [sec], where f – frequency, T – period. 1 Hz is one pulsation per second. Example: Pentium 300 MHz means that the system clock of the processor is 300,000,000 signals/sec Dr.Iliya Georgiev 16 6/21/2016 Metric Prefixes Frequency: 1 KHz (kilo)= 10 3 Hz; 1 MHz (mega)= 10 6 Hz; 1 GHz (giga)= 10 9Hz. Period: Dr.Iliya Georgiev 1 msec (milli)= 10 -3 sec; 1 µsec (micro)= 10 -6 sec; 1 nsec (nano)= 10 –9 sec; 1 psec (pico)= 10 –12 sec; 17 6/21/2016