Simucad Proprietary
HyperFault User's Manual
Version 2001.1
By Simucad, Inc.
Simucad Proprietary
Contents
1. Overview
1-1
1.1 HyperFault Simulation Environment Overview ...............................................................1-1
1.2 Logic Simulation ..............................................................................................................1-3
1.3 Fault Simulation Explanation ...........................................................................................1-4
1.4 ASIC Design Flow............................................................................................................1-5
1.5 Accumulate Fault Simulation Results...............................................................................1-7
1.6 Developing Test Vectors ..................................................................................................1-9
1.7 Concurrent Fault Simulation...........................................................................................1-11
1.8 Sample Size for Statistical Fault Simulation...................................................................1-12
1.9 Device Under Test (DUT) ..............................................................................................1-15
1.10 Fault Selection ..............................................................................................................1-16
1.10.1 Specifying All Faults...................................................................................1-17
1.10.2 Selecting Faults by Wildcards .....................................................................1-18
1.10.3 Selecting Faults By Name ...........................................................................1-19
1.10.4 Excluding Faults..........................................................................................1-21
1.10.5 Excluding Faults by Wildcards ...................................................................1-22
1.10.6 Excluding Faults By Name..........................................................................1-23
1.10.7 Regular Expressions ....................................................................................1-24
1.10.8 Suppressing Faults.......................................................................................1-27
1.10.9 Statistical Fault Simulation Commands.......................................................1-28
1.11 Specifying Test Nodes..................................................................................................1-29
1.12 Setup Options ...............................................................................................................1-30
1.12.1 Automatic Memory Utilization ...................................................................1-31
1.12.2 Checkpoint Interval .....................................................................................1-32
1.13 Fault Detections ............................................................................................................1-33
1.13.1 Hard, Possible, and Soft Detected Faults ....................................................1-34
1.13.2 Hypertrophic Faults.....................................................................................1-36
1.13.3 Tri-state Detection.......................................................................................1-37
1.13.4 Oscillations During Fault Simulation ..........................................................1-38
1.14 Distributed Fault Simulation.........................................................................................1-39
1.15 Increasing Fault Simulation Speed ...............................................................................1-40
1.16 Fault Simulator Accuracy .............................................................................................1-41
1.17 HyperCov: Fault Coverage by Blocks ..........................................................................1-42
1.18 List of Fault Simulation Commands .............................................................................1-43
2. Installation
2-1
2.1 Steps for Evaluating HyperFault ......................................................................................2-1
2.1.1 Installation Notes:............................................................................................2-1
2.2 Microsoft Windows Installation .......................................................................................2-3
2.2.1 Minimum System Requirements for the PC:...................................................2-3
2.2.2 Materials Required: .........................................................................................2-3
2.2.3 Windows NT and Windows 2000 Installation: ...............................................2-4
2.2.4 Finding the Computer Name and HOSTID for PC Computers.......................2-8
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2.2.5 Finding the Size of RAM Memory for PC Computers....................................2-8
2.2.6 Accessing Unix Floating Licenses from PC Computers .................................2-8
2.2.7 Running HyperFault ........................................................................................2-9
2.3 Solaris Installation Instructions ......................................................................................2-10
2.3.1 Material Required:.........................................................................................2-10
2.3.2 HyperFault CD-ROM Loading .....................................................................2-10
2.3.3 Unix Security File .........................................................................................2-11
2.3.4 Distributed Fault Simulation on Unix ...........................................................2-12
2.3.5 Hostid and Hostname for Solaris and HP......................................................2-13
2.3.6 Available Memory and CPU Speed for Solaris.............................................2-13
2.3.7 Running HyperFault ......................................................................................2-14
2.3.8 Linux Installation Instructions.......................................................................2-15
2.4 Accessing Technical Support .........................................................................................2-18
3. Fault Simulation Tutorial
3-1
3.1 Fault Simulation Examples Overview ..............................................................................3-1
3.1.1 General Items for Tutorial ...............................................................................3-1
3.1.2 Fault Grading Process .....................................................................................3-2
3.2 Fault Simulation Setup for the HSE Examples.................................................................3-5
3.2.1 Starting HyperFault (GUI Examples)..............................................................3-5
3.2.2 Accessing On-line Help...................................................................................3-5
3.2.3 Creating a Project ............................................................................................3-7
3.2.4 Command Line Arguments ...........................................................................3-10
3.2.5 Device Under Test.........................................................................................3-13
3.3 Example for Logic Simulation and Toggle Report.........................................................3-15
3.4 Example for Statistical Fault Simulation ........................................................................3-17
3.4.1 Fault Simulation Setup ..................................................................................3-17
3.4.2 Running Fault Simulation .............................................................................3-24
3.4.3 Fault Report...................................................................................................3-26
3.5 Example for Incremental Fault Simulation.....................................................................3-28
3.6 Example for Iterative Fault Simulation...........................................................................3-31
3.7 Example For Distributed Fault Simulation .....................................................................3-34
3.8 Example for Batch Fault Simulation ..............................................................................3-39
4. Menus
4-1
4.1 Menus Overview...............................................................................................................4-1
4.1.1 Pull-Down Menu Bar ......................................................................................4-1
4.1.2 Context Menus ................................................................................................4-1
4.1.3 Dialog Box Conventions .................................................................................4-2
4.2 File Menu..........................................................................................................................4-3
4.2.1 New .................................................................................................................4-3
4.2.2 Open Menu......................................................................................................4-3
4.2.3 Save .................................................................................................................4-3
4.2.4 Save As............................................................................................................4-4
4.2.5 Print menu .......................................................................................................4-4
4.2.6 Print Preview ...................................................................................................4-5
4.2.7 Print Setup .......................................................................................................4-5
4.2.8 Exit Menu........................................................................................................4-5
4.3 Edit Menu .........................................................................................................................4-6
4.3.1 Undo menu selection .......................................................................................4-6
4.3.2 Cut menu selection ..........................................................................................4-6
4.3.3 Copy menu selection .......................................................................................4-6
4.3.4 Paste menu selection .......................................................................................4-7
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4.3.5 Clear menu selection .......................................................................................4-7
4.3.6 Select All menu selection ................................................................................4-7
4.3.7 Find menu selection.........................................................................................4-7
4.3.8 Find Next menu selection................................................................................4-7
4.3.9 Replace menu selection ...................................................................................4-7
4.3.10 Goto Line menu selection..............................................................................4-7
4.3.11 Delete menu selection....................................................................................4-8
4.3.12 Copy Image to Clipboard menu selection .....................................................4-8
4.4 View Menu .......................................................................................................................4-9
4.4.1 Zoom selections...............................................................................................4-9
4.4.2 Main Toolbar menu selections ........................................................................4-9
4.4.3 Analyzer Toolbar menu selections ................................................................4-10
4.4.4 Status Bar ......................................................................................................4-10
4.5 Project Menu...................................................................................................................4-11
4.5.1 New Menu Selection .....................................................................................4-11
4.5.2 Open Menu Selection ....................................................................................4-12
4.5.3 Files Menu Selection .....................................................................................4-12
4.5.4 Save As Menu Selection................................................................................4-13
4.5.5 Close Menu Selection....................................................................................4-13
4.5.6 Save Project State Menu Selection................................................................4-14
4.5.7 Restore Project State Menu Selection ...........................................................4-14
4.5.8 Project Settings Menu Selection....................................................................4-15
4.5.9 Fault Simulation Settings Menu Selection ....................................................4-19
4.5.10 Filters...........................................................................................................4-26
4.5.11 Load/Reload Input Files Menu Selection ....................................................4-27
4.5.12 Reload and Go Menu Selection...................................................................4-27
4.5.13 Filters...........................................................................................................4-27
4.5.14 Project List Size...........................................................................................4-27
4.6 Fault Sim Menu ..............................................................................................................4-28
4.6.1 Start Fault Sim Menu Selection.....................................................................4-28
4.6.2 Stop Fault Sim Menu Selection.....................................................................4-28
4.6.3 Show Fault Sim Status Menu Selection ........................................................4-28
4.7 Logic Sim Menu .............................................................................................................4-30
4.7.1 Go Menu Selection........................................................................................4-30
4.7.2 Break Simulation Menu Selection.................................................................4-31
4.7.3 Finish Current Timepoint Menu Selection ....................................................4-32
4.7.4 Step Menu Selection......................................................................................4-32
4.7.5 Breakpoints Menu Selection .........................................................................4-33
4.8 Reports Menu .................................................................................................................4-35
4.8.1 Activity Menu Selection................................................................................4-35
4.8.2 Errors Menu Selection...................................................................................4-36
4.8.3 Fault Menu Selection.....................................................................................4-37
4.8.4 Iteration Menu Selection ...............................................................................4-38
4.8.5 Nonconvergence Menu Selection..................................................................4-39
4.8.6 Size Menu Selection......................................................................................4-43
4.9 Explorer Menu................................................................................................................4-44
4.9.1 Open Explorer Menu Selection .....................................................................4-44
4.9.2 Go to Module Source Menu Selection ..........................................................4-44
4.10 Options Menu ...............................................................................................................4-45
4.10.1 Fonts menu selection ...................................................................................4-45
4.10.2 Tabs menu selection ....................................................................................4-45
4.10.3 Snap to Edges ..............................................................................................4-45
4.10.4 Title Tips menu selection ............................................................................4-46
4.10.5 Analog Integer Display ...............................................................................4-46
4.10.6 Strength Color Coding ................................................................................4-46
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4.10.7 Trace Color Coding .....................................................................................4-46
4.10.8 White Background.......................................................................................4-46
4.10.9 Black Background .......................................................................................4-47
4.10.10 Full Path Title............................................................................................4-47
4.10.11 Data Tips ...................................................................................................4-47
4.10.12 Syntax Color Coding .................................................................................4-47
4.11 Window Menu ..............................................................................................................4-48
4.11.1 Cascade Menu Selection .............................................................................4-48
4.11.2 Tile Menu Selection ....................................................................................4-48
4.11.3 Arrange Icons Menu Selection ....................................................................4-48
4.11.4 Open Explorer Menu Selection ...................................................................4-49
4.11.5 Open Watch Menu Selection.......................................................................4-49
4.11.6 Open New Data Analyzer Menu Selection .................................................4-50
4.12 Help Menu ....................................................................................................................4-57
4.12.1 Contents menu selection..............................................................................4-57
4.12.2 Using Help menu selection..........................................................................4-57
4.12.3 Quick Start Guide menu selection...............................................................4-57
4.12.4 User’ Manual menu selection......................................................................4-57
4.12.5 Verilog LRM menu selection ......................................................................4-57
4.12.6 SDF Manual menu selection .......................................................................4-57
4.12.7 About HyperFault........................................................................................4-57
4.12.8 User Registration.........................................................................................4-58
4.13 Context Menus..............................................................................................................4-59
4.13.1 Explorer Window ........................................................................................4-60
4.13.2 Watch Window............................................................................................4-63
4.13.3 Data Analyzer Context menus.....................................................................4-65
4.13.4 Source Window Context menus ..................................................................4-75
4.13.5 Output Window Context menus ..................................................................4-77
5. System Tasks
5-1
5.1 Device Under Test ($fs_dut system task) .........................................................................5-1
5.2 Fault Simulation Options ($fs_options system task) ........................................................5-3
5.3 Test Nodes ($fs_strobe system task) ..............................................................................5-16
5.4 Port Faults (‘enable_portfaults) ......................................................................................5-18
5.5 Suppressing Faults (‘suppress_faults) ............................................................................5-19
6. Fault Simulation Commands
6-1
6.1 Overview ..........................................................................................................................6-1
6.2 Activity Report For Nodes................................................................................................6-2
6.3 Fault Simulation Report....................................................................................................6-9
6.4 Fault Simulation Control Parameters..............................................................................6-14
6.5 Fault Monitor..................................................................................................................6-20
6.6 Fault Simulation Specification........................................................................................6-23
6.7 HyperCov: Fault Coverage by Blocks ............................................................................6-33
6.8 Verilog Input-Stuck High Fault Specification ................................................................6-36
6.9 Verilog Input-Stuck Low Fault Specification.................................................................6-37
6.10 Verilog Output-Stuck High Fault Specification ...........................................................6-38
6.11 Verilog Output-Stuck Low Fault Specification ............................................................6-39
6.12 Input-Stuck-At High Fault Specification Using Regular Expressions .........................6-40
6.13 Input-Stuck-At Low Fault Specification Using Regular Expressions ..........................6-42
6.14 Excluded Input-Stuck-At High Fault Specification Using Regular Expressions .........6-44
6.15 Excluded Input-Stuck-At Low Fault Specification Using Regular Expressions ..........6-46
6.16 Output-Stuck-At High Fault Specification Using Regular Expressions.......................6-48
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6.17 Output-Stuck-At Low Fault Specification Using Regular Expressions .......................6-50
6.18 Excluded Output-Stuck-At High Fault Specification Using Regular Expressions.......6-52
6.19 Excluded Output-Stuck-At Low Fault Specification Using Regular Expressions .......6-54
6.20 Excluded Input-Stuck Fault Specification ....................................................................6-56
6.21 Excluded Output-Stuck Fault Specification .................................................................6-57
7. Verilog HDL Extensions
7-1
7.1 HyperFault PLI Interface..................................................................................................7-1
7.1.1 HyperFault PLI Interface on the PC................................................................7-1
7.1.2 HyperFault PLI Interface on the Workstation .................................................7-2
7.1.3 List of Implemented PLI Routines ..................................................................7-3
7.2 Standard Delay Format .....................................................................................................7-4
7.3 Expected Values and Stimulustable..................................................................................7-6
7.3.1 BNF .................................................................................................................7-6
7.3.2 Stimulustable ...................................................................................................7-7
7.3.3 Radix ...............................................................................................................7-8
7.3.4 Delay Time ......................................................................................................7-8
7.3.5 Memory Utilization .......................................................................................7-10
7.3.6 Strobe ............................................................................................................7-10
7.3.7 I/O Pad...........................................................................................................7-12
7.3.8 Expected Value Error ....................................................................................7-13
7.3.9 Expected Value Error Storage.......................................................................7-15
7.3.10 Incremental Update .....................................................................................7-15
7.3.11 Changing Behavioral Stimulus to a “stimulustable” Format.......................7-17
7.4 “hyperflt” and “hse” keywords.......................................................................................7-19
7.5 Extensions to Turn-off, Reset, and Turn-on Saving .......................................................7-19
7.6 HyperFault Extensions to Verilog HDL .........................................................................7-20
7.6.1 Global Variables:...........................................................................................7-20
7.6.2 Global tasks and functions: ...........................................................................7-20
7.6.3 Functions with multiple outputs: ...................................................................7-21
7.6.4 Functions without any inputs: .......................................................................7-21
7.6.5 Tasks and functions with ports declared like a module:................................7-21
7.6.6 Procedural assignment to wires:....................................................................7-22
7.6.7 Continuous assignments to register and memory variables:..........................7-22
7.6.8 Continuous assignments using intra-assignment/non-blocking delays: ........7-22
7.6.9 Default state value for UDP: .........................................................................7-23
7.6.10 UDP additional states for High-Z on inputs or output: ...............................7-23
7.6.11 UDP edge for High-Z:.................................................................................7-24
7.6.12 UDP Multiple Edges in a Row: ...................................................................7-24
7.6.13 Non-Constant Specify Block Delays:..........................................................7-24
7.6.14 Parameter for Specify Block Delays: ..........................................................7-24
7.6.15 Stimulustable Extension: .............................................................................7-25
7.6.16 “input/output/inout” declarations after the variable's declaration: ..............7-25
7.6.17 Using registers as module inputs:................................................................7-25
7.6.18 Duplicate variable definitions: ....................................................................7-26
7.6.19 Parameter used for sizing numbers: ............................................................7-26
7.6.20 Null statements:...........................................................................................7-26
7.6.21 Timing checks without edge specifications for selected variables:.............7-27
7.6.22 More precision in “$timeformat” than “`timescale”:...................................7-27
7.6.23 Missing port connections are set to ground for VCS compatibility: ...........7-27
7.6.24 VCS compatibility extension for comma at the end of the port list, i.e.:
module (xx(a,): .......................................................................................................7-27
8. Additional Commands
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8.1 Command Syntax..............................................................................................................8-1
8.2 Stopping Processes ...........................................................................................................8-1
8.3 Commands in Files ...........................................................................................................8-2
8.4 Command-line Options.....................................................................................................8-4
8.5 Bus Contention Report ...................................................................................................8-10
8.6 Encrypting Library Files.................................................................................................8-12
8.7 Control Parameters For Logic Simulation ......................................................................8-13
8.8 Default Device Delay Times...........................................................................................8-18
8.9 Disk File Name Reassignment........................................................................................8-19
8.10 Error Summary .............................................................................................................8-20
8.11 Exclude Saving Simulation Node States ......................................................................8-21
8.12 Exiting The Program ....................................................................................................8-22
8.13 File Name Specification ...............................................................................................8-23
8.14 Keeping Simulation Node States ..................................................................................8-24
8.15 Exclude Saving Module Instance Variable Values.......................................................8-25
8.16 Keeping Module Instance Simulation Variable Values................................................8-26
8.17 Nonconvergence Summary...........................................................................................8-27
8.18 Preprocessing Data .......................................................................................................8-30
8.19 Probing Node States .....................................................................................................8-31
8.20 Quitting Execution........................................................................................................8-33
8.21 Resetting Selected Data ................................................................................................8-34
8.22 Scope For Printing Module Variables ..........................................................................8-36
8.23 Logic Simulation Specification ....................................................................................8-37
8.24 Size-Of-Data Reprint ....................................................................................................8-39
8.25 Spike Summary Output.................................................................................................8-40
8.26 Storing Outputs.............................................................................................................8-41
8.27 Strength Specification For Gates ..................................................................................8-42
8.28 Symbol Modification For Output .................................................................................8-44
9. Index
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1. Overview
1.1 HyperFault Simulation Environment Overview
The HyperFault Simulation Environment (HSE) is a fault simulation program that can be used to
fault grade test vectors for Verilog HDL designs. The test vectors are used by testing equipment at
a foundry during manufacturing to reject parts that have manufacturing defects.
The HyperFault Simulation Environment provides the following fault simulation capabilities:
Graphical User Interface (GUI) provides an easy method to setup fault simulation.
Full Verilog syntax is allowed in fault simulation. This saves the designer time by
eliminating the need to convert designs or test fixtures for fault simulation.
Wide range of fault selection. HyperFault uses the stuck at high and stuck at low fault
models for either input faults or output faults. HyperFault allows you to choose all faults, or
a subset of faults. You can choose or exclude faults by position in the hierarchy, by common
substrings, or by named faults. Once you've chosen the faults, you can select a statistical
sample of the faults, and change the random sample whenever you like.
Fault simulation can be run using functional (unit) delays, or fault simulation can be run
using the delays as specified in the design, and also with back annotation of delays using the
Standard Delay Format (SDF).
Mixed behavioral/gate fault simulation enables the faults to be selectively applied to each
block of RTL code as it is synthesized to the gate level, leaving the remainder of the design
at the RTL level (HyperFault propagates the effect of a fault through behavioral code). This
reduces memory usage and increases the fault simulation speed.
Automatic memory adjustment lets you specify the available memory on your computer and
HyperFault automatically figures out the number of faults per pass. This increases the
effective speed because the fault simulation always fits in memory and never swaps to disk.
Incremental fault simulation enables you to run sequences of test-benches/vectors and
HyperFault automatically tracks detected faults as you progress. An on going summary
shows progress and percent detection as each testbench is processed. This makes it simpler
to use new test vectors for increasing the fault coverage.
Distributed fault simulation divides the job across as many CPUs in the network as selected.
The result is a linear reduction in time with each CPU added. The automatic memory
adjustment lets you specify the available memory for each computer. Incremental fault
simulation also works with distributed fault simulation.
(continued on next page)
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Feature Overview
(HyperFault Simulation Environment Overview)
Crash recovery prevents the loss of fault simulation results so you never lose days of
processing again!
Automatic stop and restart allows overnight and weekend fault simulation runs. This enables
you to use additional computers without conflicting with other employees.
Hypertrophic faults are recognized as detected when the size of the faulted circuit reaches a
percentage of the size of the un-faulted reference circuit. This speeds up fault simulation.
Time dependent fault injection enables the user to inject faults after initialization, or before
the first test vector. This can reduce the potential for false detections during the
initialization.
All features for logic and fault simulation run on Unix and Windows NT, making HyperFault
platform independent for future planning and machine purchases.
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Logic Simulation
1.2 Logic Simulation
The HyperFault Simulation Environment uses the IEEE 1364 “Standard Hardware Description
Language Based on the Verilog Hardware Description Language” manual as the specification for
logic simulation. The logic simulation is typically done first to verify correct operation of the
design.
The logic simulator for HyperFault is an excellent debugging tool for locating the cause of
incorrect logic simulation results, or verifying the logic simulation behavior of HyperFault:
The Graphical User Interface (GUI) organizes the design as a project, with all of the input
files, library files, and command line options under one project name. To simulate a project,
the user opens the project, clicks on the “Go” button, and the results for every variable are
automatically saved.
Hierarchy Explorer in HyperFault lists all of the module instances in the design. For each
instance, the ports and local variables are listed. Any variable in the design can be selected
and dragged and dropped into the Data Analyzer to view the waveforms.
The Data Analyzer can change the radix for vectors, show state machine symbols as the
value for a vector, show groups of signals, remember “bookmarks” (the resolution and time
value of the current display), and display user defined buses and user defined expressions
without saving them before simulation.
The source code debugger automatically opens the source file and points to the line that is
executing when the designer single steps through source code for the design. The designer
can highlight any variable or expression in the source code file, and drag and drop the
variable or expression into the Data Analyzer to view the waveform, or into a Watch window
to see the immediate value. The source code debugger can also set breakpoints.
The Watch window can be used to view any variable or expression during single stepping.
The Watch window can also be used to set any register to a value, set or force any wire to a
value, and view the contents of memory variables.
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Fault Simulation
1.3 Fault Simulation Explanation
HyperFault uses the IEEE 1364 “Standard Hardware Description Language Based on the Verilog
Hardware Description Language” manual as the specification for fault simulation. The algorithms
for the HyperFault Simulation Environment are implemented on top of the logic simulator engine
to create one executable. The HyperFault Simulation Environment is executed via a link to the
Silos executable.
Fault simulation is used in the process of creating and fault grading test vectors. Before a chip or a
circuit board is shipped, it is tested during manufacturing to determine if there are any
manufacturing flaws. This is done by inserting it on a tester. At fixed time intervals, the tester
applies sets of binary signals (the test vectors) to the input pins of the circuit. Also at fixed
intervals (though not necessarily at the same time points) the tester senses the response of the
circuit at certain output pins. The tester compares each set of output signals against the set of
expected results from the logic simulation run with the same test vectors and the same design. If
any of the outputs do not match the expected output, the tester will reject the part.
The goal of the designer (or test engineer) is to create a set of test vectors that will uncover any
possible manufacturing defect in the circuit. This set of test vectors should be as compact as
possible to minimize the amount of time that each chip will be on the tester.
To fault grade the test vectors, fault simulation uses two copies of the circuit, a fault free circuit,
and a faulted circuit that has one fault injected into it. The basic algorithm for fault simulation is to
simultaneously run logic simulation on the fault free circuit and run logic simulation on one or
more faulted circuits with each faulted circuit using a separate space in the computer’s RAM
memory. The fault simulation compares the outputs of each faulted circuit with the outputs of the
fault-free circuit. If the faulted circuit has the same results as the fault-free circuit at each of the
strobed time points, then the fault is considered “not detected”. If one or more of the test node
levels for the faulted circuit is different from the corresponding test node level in the reference
circuit at any output strobe time, then the fault is considered to be “detected”.
The quality of the test vectors is usually described by the “detection ratio” (or “detection
percentage”). This is the ratio of the number of faults that are detectable, divided by the number of
possible faults. Thus, a detection ratio of 100% means that the test vectors were able to detect
every possible fault. Generally, a detection ratio of 95% or greater is considered to be necessary
for effective fault coverage. This process is known as “fault grading”, and the percentage of
detected faults is called the fault coverage.
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ASIC Design Flow
1.4 ASIC Design Flow
The below flow diagram shows a common design flow for fault grading the test vectors:
RTL
Hyperfault
Synthesis
Fault Simulation
Place and Route
Traditional
ASIC Foundry
Tester
Fault Graded
Test Vectors
(test chips for defects)
The traditional design flow is to run fault simulation after tape out. This is common because test
groups are separate from design groups, and usually there is no time to run fault simulation until
after tapeout. HyperFault allows fault simulation on mixed RTL and gate level designs as each
block of RTL code is synthesized. This enables the designer to fault grade test vectors as the RTL
design is synthesized to the gate level.
(continued on next page)
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Mixed Level
Typically, synthesis tools work best if the ASIC design is sub-divided into blocks (components).
Each block usually represents 2k to 5k gates. As each block is synthesized, HyperFault has the
ability to apply the faults only on the synthesized gate level block, yet simulate these faults with
the total design, as illustrated by the below diagram:
Mixed RTL/Gate Design
Outputs
Inputs
RTL Level
RTL Level
RTL Level
RTL Level
Gate Level
RTL Level
RTL Level
RTL Level
RTL Level
RTL Level
RTL Level
RTL Level
The advantages of running fault simulation early in the design cycle can be immense:
Speed. Fault simulations run faster because the portions at the RTL level simulate faster than
if the entire design was gate level. Also, fault simulations can be run sooner in the design
cycle. Thus the designer can get an early start on developing test vectors while he/she still
understands the circuit.
Design for testability. For large designs it is necessary to consider testability when designing
and writing HDL code. Otherwise, RTL level synthesis can be a fast and efficient means of
producing untestable logic. Making modifications to the design at the RTL level is much
easier then at the gate level after synthesis.
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Incremental
1.5 Accumulate Fault Simulation Results
HyperFault has the capability to accumulative fault simulation results across more than one fault
simulation run. Accumulating the fault simulation results can be used to fault grade the design
block by block, to fault grade new test vectors against only the undetected faults from previous
fault simulations, and to iterate across the types of detected faults.
When fault grading the design block by block, the designer is usually working with a mixed RTL
and gate level design. As each block of the design is synthesized, the faults are applied to the
synthesized gate level block. This reduces fault simulation run time and memory requirements.
The below diagram shows the strategy of selectively faulting portions of the circuit at the gate
level, and using iterative fault simulation to summarize the results for the entire design. To run
incremental fault simulation, see fsim/iterate command described in the “Fault Simulation
Specification” on page 6-23.
Incremental Fault Simulation for
Mixed RTL/Gate Design
Gate Level
RTL Level
(continued on next page)
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Incremental
(Incremental Fault Simulation)
Using incremental fault simulation to fault grade new test vectors against only the undetected faults
from previous fault simulations reduces the run time because the detected faults do not have to be
re-simulated (see “Example for Incremental Fault Simulation” on page 3-28, or the fsim/iterate
command “Fault Simulation Specification” on page 6-23).
Using iterative fault simulation to iterate across the types of detected faults is useful for verifying
that hypertrophic and possible detects would have been hard detects. This speeds up the fault
simulation process by allowing the designer to fault grade the test vectors without having to wait
for the hypertrophic and possible detects. After the fault grading is completed, the designer can
rerun the hypertrophic faults and the possible detects to see if they would have been hard
detections.
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Developing Test Vectors
1.6 Developing Test Vectors
The process of developing and fault grading test vectors is shown below:
Fault Simulation Methodology
Testbench
ALU
1st subset
Logic Simulation
nd
memory
other
2 subset
1st subset
2nd subset
1st subset
Activity Report
2 subset
(ensure all nets toggle)
more subsets
Statistical
Fault Simulation
nd
ALU
Pre-grade test
vectors
more subsets
Create additional
vectors by hand
Incremental
Fault Simulation
Create 95%99% fault
coverage
(apply more test vectors)
Statistical
Fault Simulation
(vary random number seed)
Confirm fault
coverage
accuracy
100%
Fault Simulation
(Optional)
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Developing Test Vectors
(Fault Grading Process)
It may seem relatively easy to generate test vectors for a circuit. If the circuit has “n” inputs, then
there can be at most 2n possible sets of input vectors. Thus, a circuit with 16 inputs would have
65536 possible different input vectors. The above assumption is true as long as the circuit is
combinational (that is, there are no internal feedback paths). If the circuit is sequential, then the
outputs depend not only upon the input vectors, but the order in which they occur. The total
number of combinations of input vectors is the factorial of the number of input patterns
(3!=1*2*3). For the 16-input circuit, the number of input combinations is 65536!, which is an
incredibly large number. Thus for sequential circuits, developing a set of test vectors is usually a
highly intuitive process.
For combinational networks, such as are used in scan-design logic circuits, the problem is much
more contained. Since the number of possible test vectors is reasonable and the circuit is much
more deterministic, automatic computation of the test vectors is possible. Synchronous circuits
may also work well with automatic test generation tools.
The typical method of developing the test vectors is to take subsets from the logic simulation’s test
bench. The designer chooses subsets that he/she thinks will exercise the circuit sufficiently to
detect manufacturing defects (see “Fault Simulation Methodology” diagram on preceding page).
The first subsets of the test bench are used to run logic simulation and generate an Activity report.
HyperFault has the unique ability to pre-grade the test vectors by using the Activity report from
logic simulation. Because logic simulation runs much faster than fault simulation, this gives you a
quick preview of the test vector effectiveness. The Activity report is used to determine if any nets
do not toggle, because if a net does not toggle then it cannot be detected. Additional slices of test
vectors are added until every net toggles.
Statistical fault simulations are then run to fault grade the test vectors. An ASIC design of 20,000
gates would have approximately 120,000 possible faults, considering stuck-at-one and stuck-atzero faults for every gate’s output and input (two inputs per gate). Just a 3% random sample that
uses 3600 faults instead of 120,000 faults can be run relatively quickly with a high degree of
accuracy.
Next, incremental fault simulations are run. These fault simulations use only the undetected faults
to fault grade the additional slices of test vectors from the logic simulation. As the number of
undetected faults gets smaller, the fault simulations run faster. Finally the designer is forced to
write additional test vectors to bring the fault coverage within 95% to 99%.
To verify the accuracy of the statistical fault simulation results, different statistical fault
simulations can be run by changing the seed for the random number generator. If the design
requirements mandate running 100% fault simulation, this can be run as a final check.
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Concurrent
1.7 Concurrent Fault Simulation
HyperFault uses a fast and efficient concurrent fault simulation algorithm. As the faulted circuits
are concurrently simulated, HyperFault tracks in memory the divergence between each faulted
circuit and the reference circuit. HyperFault strobes the level of the test nodes between each
faulted circuit and the reference circuit to determine if the fault has been detected. At the
conclusion of fault simulation the detected and undetected faults can be reported.
Running concurrent fault simulation is most efficient when many faulted circuits are run
concurrently with the reference circuit, in order to share the overhead of the reference circuit
simulation. This can require more memory than the logic simulation. To achieve optimum
performance, your computer should be configured with sufficient memory. To specify the amount
of available RAM memory so that fault simulation never swaps to disk, see the “max_memory”
option for “Fault Simulation Options ($fs_options system task)” on page 5-3.
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Statistical Analysis
1.8 Sample Size for Statistical Fault Simulation
Statistical fault simulation is a useful tool for reducing the time required to determine the fault
coverage for a set of vectors. Many designs are so large that running 100% fault simulation is not
practical. The purpose of this write-up is to show you how to calculate a meaningful sample size
for statistical fault simulation.
The size of the random sample of faults for statistical fault simulation can be very important in
reducing the time required to run fault simulation. It is very important that the user determine an
effective sample size before running his design. Too small a sample may give inaccurate results.
Too large a sample will not increase the accuracy to any meaningful extent, at the expense of
wasting valuable engineering time. Many users mistakenly think that a 10% random sample of
faults is twice as accurate as a 5% random sample of faults. Instead, the user should think in terms
of a level of confidence for the final statistical fault grading, plus or minus an acceptable margin of
error.
The formula for calculating sample size is:
n = (t)2 (s)2 / (B)2
Where “n” is the sample size, “t” is the Student’s t-distribution, “s” is the standard deviation of the
sample, and “B” is the desired bound of the error of estimation.
For random samples whose size is greater than 300, the values for Student’s t-distribution become
the same as those for the normal distribution, as shown in the table below:
Level of Confidence
Student’s “t” value
95%
1.960
98%
2.326
99%
2.576
99.9%
3.291
The standard deviation “s” of the sample can be estimated by using the “Empirical Rule” for
statistics. The “Empirical Rule” states that for normal distributions, dividing the total range by
four provides a reasonable estimate of the standard deviation. Since the range for fault coverage is
a percentage that varies from 0.0 to 1.0, the estimated standard deviation is ¼ or 0.25.
The term “B” is the desired bound of the error of estimation, which is the “plus or minus” accuracy
value for the fault grading.
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Statistical Analysis
(Sample Size for Statistical Fault Simulation)
To determine an effective sample size before running fault simulation, the user should choose the
level of confidence and accuracy desired for their final fault grading . For example, the user may
decide he wants to be 99% confident the final fault grading will be accurate to within a fault
detection result of plus or minus 2%. For this level of confidence and accuracy, the below
calculation shows the user would have to sample 1037 faults:
n = (2.576)2 (0.25)2 / (0.02)2 = 1037 faults sampled.
To check the reasonableness of the above calculation, fault simulations for three different circuits
were examined. For each circuit, fourteen separate fault simulations were run using a different
random sample for each fault simulation. Different random samples can be generated by changing
the seed for the random number generator using the “fsim / seed = value” command (see the Fault
Simulation Specification). From the table below, notice the accuracy of the random samples is not
dependent on the percentage selected, as the 4.2% random sample of faults selected for circuit 1,
the 4.5% random sample of faults selected for circuit 3, and the 1.5% random sample of faults
selected for circuit 4, gave similar levels of accuracy as the 23.4% random sample of faults
selected for circuit 2. Instead, the size of the sample for each fault simulation is the determining
factor. The table below shows that increasing the sample size above 1037 faults could have
provided only a slight increase in accuracy, as the results for using random samples were very
close to the fault detection ratio when 100 percent of the faults were run.
Circuit
Number
Total
of devices faults
Percent
selected
for each
random
sample
Total
selected
faults
Percent
detected
for 100%
of faults
Mean of
faults
detected
for 14
samples
Standard
deviation
of means
for the 14
samples
1
5894
24756
4.2%
1038
67%
66%
1.709%
2
1290
4428
23.4%
1035
15%
15.3%
0.726%
3
8513
23409
4.5%
1051
62%
62%
1.03%
4
27647
69742
1.5%
1044
38%
37.8%
1.42%
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Statistical Analysis
(Sample Size for Statistical Fault Simulation)
Normally, the user will not have the luxury of running 100% of the total faults to validate the final
statistical fault simulation results, as is shown in the table above. Therefore, the accuracy of the
final statistical fault simulation results should be checked by running fault simulations that use the
exact same test vectors and design, but use different random samples of selected faults (by
changing the seed for the random number generator). The user can calculate the mean and the
standard deviation of results for the fault simulations by using any scientific calculator. Fault
simulation run time and computer resources will probably limit the number of fault simulations
that can be run to validate the final statistical fault simulation results. The user should run at least
three, and preferably five or six fault simulations with different random samples to validate the
final results for statistical fault simulation.
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Device Under Test
1.9 Device Under Test (DUT)
HyperFault requires that the device under test (DUT) be identified. The device under test can be
specified using the $fs_dut system task (see “Device Under Test ($fs_dut system task)” on page 51). The effect of a fault is contained by HyperFault within the DUT. A fault effect will not
propagate outside of the DUT. If the DUT is not specified, the effect of the fault may propagate
into the test bench and have undesirable consequences.
Strobe points must be at the level of the DUT or below it in the design hierarchy. The typical
design has a test bench and a single instantiation for the entire design. The DUT is usually
specified at entire design level, with the outputs for the design specified as the test nodes. If a user
wants to fault a portion of the design that is further down in the hierarchy, the commands for fault
selection by wildcards are used (see “Selecting Faults by Wildcards” on page 1-18).
DUT, Testnodes, and Fault Selection
Testbench
Inputs
Outputs
DUT
Fault selection by
wildcards
Testnodes
Design
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Fault Selection
1.10 Fault Selection
Stuck at high and stuck at low faults are injected into the gate portion of the design during fault
simulation to simulate the effect of manufacturing defects (an open or a short). Stuck at high and
stuck at low faults can be specified for either the gate outputs, or the gate inputs.
Fault selection is specified by either:
Specifying HyperFault commands in separate files from the design (see “Specifying All
Faults” on page 1-17, “Selecting Faults by Wildcards” on page 1-18, “Selecting Faults By
Name” on page 1-19, “Excluding Faults” on page 1-21, “Excluding Faults by Wildcards” on
page 1-22, and “Excluding Faults By Name” on page 1-23).
Specifying fault simulation compiler directives in the design and library files, e.g.
`suppress_faults and `nosuppress_faults, `enable_portfaults and `disable_portfaults (see
“Suppressing Faults” on page 1-27 and “Port Faults (‘enable_portfaults)” on page 5-18).
After the fault selection process, a statistical percent of the selected faults can be applied to reduce
the number of faults simulated.
Select Faults
All
Wildcard
Name
Exclude
faults
Ramdon Sample
of Selected Faults
Fault Simulator
The exclusion process in HyperFault occurs after fault selection, independent of the order in which
the exclusion commands are located in the input files.
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All Faults
1.10.1 Specifying All Faults
Typical fault simulation commands for selecting all faults are shown below. These commands
must be outside of any “module … endmodule” statements:
!volow .all
!vohigh .all
!vihigh .all
!vilow .all
For more information on these commands, see “Verilog Input-Stuck High Fault Specification” on
page 6-36, “Verilog Input-Stuck Low Fault Specification” on page 6-37, “Verilog Output-Stuck
High Fault Specification” on page 6-38, and “Verilog Output-Stuck Low Fault Specification” on
page 6-39.
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Wildcard Selection
1.10.2 Selecting Faults by Wildcards
-“!vreslow \“test_bench\.test\..*\” ”
-“!vreshigh \“test_bench\.test\..*\” ”
-“!vreislow \“test_bench\.test\..*\” ”
-“!vreishigh \“test_bench\.test\..*\” ”
Wildcards can be used to select specific parts of the design hierarchy (see “Regular Expressions”
on page 1-24). The “!vreslow” and “!vreshigh” commands can be used to select output stuck at
low or output stuck at high faults (see “Output-Stuck-At Low Fault Specification Using Regular
Expressions” on page 6-50 and “Output-Stuck-At High Fault Specification Using Regular
Expressions” on page 6-48). The “!vreislow” and “!vreishigh” commands can be used to select
input stuck at low or input stuck at high faults (see “Input-Stuck-At Low Fault Specification Using
Regular Expressions” on page 6-42 and “Input-Stuck-At High Fault Specification Using Regular
Expressions” on page 6-40).
If you want to “or” regular expressions together, simply use a space to separate each regular
expression that you wish to “or” (the “||” and “&&” operators are not supported by regular
expressions), i.e. -“!vreslow \“test_bench\.test1\..* test_bench\.test2\..*\” ”
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Name Selection
1.10.3 Selecting Faults By Name
The fault simulation commands for selecting faults by name are shown below. These commands
must be outside of any “module … endmodule” statements:
-“!volow “stuck low fault”
-“!vohigh “stuck high fault”
-“!vilow “input stuck low fault”
-“!vihigh “input stuck high fault”
When selecting a fault by name, the Verilog HDL language syntax is used to specify the
hierarchical name for the fault. Below is a sample command for output stuck at low faults (volow
command):
!volow
+ "top.mux.out"
+ "top.mux.out2"
Notice that each line begins with a plus sign "+" in column one.
When selecting faults by name, remember to review the project_name.mfv file to comment out any
fault specification commands that would override the naming the faults, such as other "!volow",
"!vohigh", "!volow", or "!vohigh" commands.
To input the list of named faults from a file, simply include the file name in the project_name.cfv
file before the line "// Simucad Generated Commands Start Here". For example, if the file to name
the faults is "fault.list", then below example shows how to input it for the command file fltsim.cfv
from the batch example (see "Example for Batch Fault Simulation" on page 3-39):
Command File “faultsim.cfv” (generated by HSE)
fault.list
// List of named faults provided by user
// Simucad Generated Commands Start Here
-"!file .sav=faultsim"
// Renames the save file to the project name
// Simucad define
...
// Input Files
faulttst.v
// User file for specifying test nodes
faultsim.mfv
// File generated by HSE
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Name Selection
(Selecting Faults By Name)
For more information on these commands, see “Verilog Input-Stuck High Fault Specification” on
page 6-36, “Verilog Input-Stuck Low Fault Specification” on page 6-37, “Verilog Output-Stuck
High Fault Specification” on page 6-38, and “Verilog Output-Stuck Low Fault Specification” on
page 6-39.
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Excluding Faults
1.10.4 Excluding Faults
Fault exclusion is the ability to exclude portions of the design from being faulted. Fault exclusion
commands are typically used to exclude selected faults (such as oscillating faults) from a block of
the hierarchy for which faults have been selected.
The exclusion process in HyperFault occurs after fault selection, independent of the order in which
the exclusion commands are located in the input files. Fault selection is specified by either:
Inserting commands in fault simulation specific files exterior to the design (see “Excluded
Input-Stuck-At High Fault Specification Using Regular Expressions” on page 6-44,
“Excluded Input-Stuck-At Low Fault Specification Using Regular Expressions” on page 646, “Excluded Output-Stuck-At High Fault Specification Using Regular Expressions” on
page 6-52, “Excluded Output-Stuck-At Low Fault Specification Using Regular Expressions”
on page 6-54, “Excluded Input-Stuck Fault Specification” on page 6-56, and “Excluded
Output-Stuck Fault Specification” on page 6-57).
Inserting compiler directives into the design and library files, e.g. `suppress_faults and
`nosuppress_faults, `enable_portfaults and `disable_portfaults (see “Suppressing Faults” on
page 1-27 and “Port Faults (‘enable_portfaults)” on page 5-18).
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Excluding Faults by Wildcards
1.10.5 Excluding Faults by Wildcards
-“!vrexslow \“test_bench\.test\..*\” ”
-“!vrexshigh \“test_bench\.test\..*\” ”
-“!vreixslow \“test_bench\.test\..*\” ”
-“!vreixshigh \“test_bench\.test\..*\” ”
Wildcards can be used to exclude specific parts of the design hierarchy (see “Regular Expressions”
on page 1-24). The “!vrexslow” and “!vrexshigh” commands can be used to exclude output stuck
at low or output stuck at high faults (see “Excluded Output-Stuck-At Low Fault Specification
Using Regular Expressions” on page 6-54 and “Excluded Output-Stuck-At High Fault
Specification Using Regular Expressions” on page 6-52). The “!vreixslow” and “!vreixshigh”
commands can be used to exclude input stuck at low or input stuck at high faults (see “Excluded
Input-Stuck-At Low Fault Specification Using Regular Expressions” on page 6-46 and “Excluded
Input-Stuck-At High Fault Specification Using Regular Expressions” on page 6-44).
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Excluding Faults by Name
1.10.6 Excluding Faults By Name
The fault simulation commands for excluding faults by name are shown below. These commands
must be outside of any “module … endmodule” statements:
-“!xslow “stuck low fault”
-“!xshigh “stuck high fault”
-“!xislow “input stuck low fault”
-“!xishigh “input stuck high fault”
For more information on these commands, see “Excluded Input-Stuck Fault Specification” on page
6-56, and “Excluded Output-Stuck Fault Specification” on page 6-57.
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Regular Expressions
1.10.7 Regular Expressions
A regular expression is a notation for specifying and matching strings. Regular expressions have
two basic kinds of characters:
special characters
These are characters that have special meaning for matching strings.
The special characters for regular expressions are:
\ ^ $ . [ ]
*
+
?
where:
\
this escapes or quotes other characters, such as \$ matches the “$”. A useful
quoted string is \| which means “or”. Another useful quoted string is \( and \)
which allow the parenthesis to be used to group regular expressions. For
example, ac* means the character “a” and zero or more characters of “c”.
However, \(ac\)* means zero or more occurrences of the character string “ac”.
^
this uses the character that follows the ^ to match the beginning of a string. When
^ is the first character in a character class it means the complement of the
character class.
$
this matches the end of a string.
.
this matches any single character.
[ ]
characters enclosed in brackets are a character class.
*
this matches zero or more occurrences of the character that precedes the *.
+
this matches one or more occurrences of the character that precedes the +.
?
this matches zero or one occurrence of the character that precedes the ?.
ordinary characters
These are all the other available characters. These characters match
themselves, such as “a” would match the letter “a”.
The character class [ ] has special rules. Inside a character class, all characters have their literal
meaning, except for the quoting character “\”, “^” at the beginning, and “-“ between two
characters. Each of the characters in a character class are treated as an “or” search. For example,
[ab] will find any single character name “a” or “b”. The character class [a-z] will match any single
character lower case name. The character class [^a-zA-Z] will match any single character name
that is not an alpha.
(continued on next page)
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Regular Expressions
(Regular Expressions)
Some examples of using regular expressions are listed below:
a
matches only the letter lowercase “a”, such as a file whose name is “a”.
a.*
matches any set of characters that begins with “a”, such as a file whose
name is “apple”.
.*a
matches any set of characters that ends with “a”, and matches the name
that is just the character “a”, such as a file whose name is data.
.*a.*
matches any set of characters that has an “a” anywhere, such as the file
names apple or data.
[abc]
matches only the character “a” or “b” or “c”.
[a-z]
matches any character that is a single lower case character, such as “b”.
[a-z]*
matches any set of characters that is only lower case characters, for
example “data”.
[a-zA-Z]*
matches any set of characters that is upper and/or lower case characters,
for example file names “data”, “DATA” and “Data”.
[a-zA-Z0-9]*
matches any set of characters that has upper and/or lower case characters
and/or digits, for example file names “data”, “DATA”, “Data”, “123”,
“data1”.
[a-zA-Z0-9_]*
matches any set of characters that has upper and/or lower case characters,
and/or digits, and/or “_”, for example file names “data”, “DATA”, “Data”,
“123”, “data1”, and “DATA_bus1”.
Some programming books (such as AWK and Perl) show regular expressions enclosed with slashes
“/ /”. The HyperFault style of searching for regular expressions is a character search and forward
slashes have no special meaning. For example, using the regular expression /a/ to try to find any
name that contains an “a” will find only the name “/a/”.
If you want to “or” regular expressions together, simply use a space to separate each regular
expression that you wish to “or” (the “||” and “&&” operators are not supported by regular
expressions).
Regular expressions are not like the Unix style wildcards (where “?” matches any single character,
“*” matches any pattern, and [list] matches any character in list including ranges). For example,
using the regular expression *a* to find any name that contains an “a” will not find any names.
(continued on next page)
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Regular Expressions
(Regular Expressions)
If you want use regular expressions to find every name that has an “a”, you can enter:
.*a.*
For the above expression, “.*a.*” means search for zero or more occurrences (the first “*”) of any
character (the first “.”), followed by a single character “a”, followed by zero or more occurrences
(the second “*”) of any character (the second “.”). So, with the search “.*a.*” you could find
names such as “a”, “data”, “read”, etc.
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Suppressing Faults
Enabling Port Faults
1.10.8 Suppressing Faults
HyperFault has many optional features to assist with fault simulation. HyperFault can suppress the
application of faults within library cells. The ‘suppress_faults and ‘nosuppress_faults compiler
directives can be used to suppress the application of faults on module items that are specified
between them. The ‘enable_portfaults compiler directive allows faults to be applied to the ports
for suppressed modules. The ‘disable_portfaults compiler directive turns off port faulting for
suppressed modules. Below is an example of these compiler directives:
‘suppress_faults
‘enable_portfaults
module nand2 (in1, in2, out);
input in1, in2;
output out;
nand x2 (out, in1, in2);
endmodule
‘disable_portfaults
‘nosuppress_faults
For a module port to be eligible to be faulted, either end of the branch can be eligible. The default
case makes all devices and nodes eligible. The user can control the eligibility of either devices or
nodes as follows:
The “ ‘suppress_faults” compiler directive makes all module items ineligible until a “
‘nosuppress_faults” compiler directive is encountered (see “Suppressing Faults
(‘suppress_faults)” on page 5-19). The “ ‘enable_portfaults” compiler directive allows faults
on the module ports for suppressed modules (see “Port Faults (‘enable_portfaults)” on page
5-18.
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Statistical Specification
1.10.9 Statistical Fault Simulation Commands
When the circuit is very large, a good approximation of the fault detection ratio can be determined
by simulating only a random percentage of the faults.
For incremental fault simulation, HyperFault chooses the same set of random faults, unless the
design is changed. This enables the user to use different sets of test vectors and incrementally fault
grade the same fault base for statistical fault simulation.
To check the results of statistical fault simulation, HyperFault allows the user to modify the
random selection process by changing the “seed” value used by the pseudo-random number
generator in the program (see “Fault Simulation Specification” on page 6-23).
For specifying a statistical percentage of randomly selected faults, or 100% fault simulation, the
“!volow” and “!vohigh” commands can be used to specify output stuck at low and output stuck at
high faults (see “Verilog Output-Stuck High Fault Specification” on page 6-38 and “Verilog
Output-Stuck Low Fault Specification” on page 6-39). The “!vilow” and “!vihigh” commands can
be used to specify input stuck at low and input stuck at high faults (see “Verilog Input-Stuck High
Fault Specification” on page 6-36 and “Verilog Input-Stuck Low Fault Specification” on page 637).
Typical fault simulation commands are shown below:
!volow .pct=100
!vohigh .pct=3
!vihigh .pct=0
!vilow .pct=1
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Test Nodes
1.11 Specifying Test Nodes
Prior to fault simulation, a set of test nodes must be identified for the circuit. Usually, the output
pins for the circuit are selected as test nodes. The $fs_strobe system task is used to specify the test
nodes and to identify the strobe times (for more information, see “Test Nodes ($fs_strobe system
task)” on page 5-16). An example for using $fs_strobe is shown below:
module test;
reg clock, b, enable;
wire out1, out2;
notif1_1 x1 (b, enable, out1);
nand2
x2 (clock, b, out2);
always @(posedge clock)
$fs_strobe (out1, out2);
always if (enable == ‘b1)
#1 $fs_strobe (out1);
endmodule
Another example for using $fs_strobe in an initial block is shown below. This example creates an
offset of 500 ns, and then strobes test nodes out1 and out2 every 200 ns:
`timescale 1ns / 1ns
module test;
reg clock, b, enable;
wire out1, out2;
notif1_1 x1 (b, enable, out1);
nand2
x2 (clock, b, out2);
initial
begin
#500
forever
#200 $fs_strobe (out1, out2);
end
endmodule
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Setup Options
1.12 Setup Options
HyperFault has the following useful setup options for fault simulation:
Maximum memory specification;
Checkpoint interval for crash recovery;
Tri-state detection.
The above setup options are specified by the $fs_options system task (“Fault Simulation Options
($fs_options system task)” on page 5-3.
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Memory Size
1.12.1 Automatic Memory Utilization
$fs_options(…, “max_memory=<n>”, … );
The amount of memory used by each fault increases in size as the faulted circuit diverges from the
reference circuit. The “FMON” command can be used to monitor memory usage during fault
simulation. If the fault simulation exceeds the available memory, then the automatic memory
adjustment will suspend faults so that the fault simulation always fits in memory and never swaps
to disk (see the “Memory Usage Controls” for the “Fault Sim Options” tab in the “Fault Simulation
Settings” dialog box, or the “max_memory=value” option for “Fault Simulation Options
($fs_options system task)” on page 5-3). Suspended faults are then run at the end of the fault
simulation. Other fault simulation products that do not have automatic memory adjustment will
slow down drastically if they run out of memory and start swapping to disk. This option has no
effect on logic simulation.
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Checkpoint
1.12.2 Checkpoint Interval
$fs_options(…, “checkpoint_interval=<time>”, … );
When this option is specified, HyperFault will update the fault dictionary file with sufficient
information to re-start the fault simulation run without loss of data from the crashed run (see
“checkpoint_interval=time” option for “Fault Simulation Options ($fs_options system task)” on
page 5-3).
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Fault Detections
1.13 Fault Detections
The comparison of the good circuit with the faulty circuit results in the following conditions at a
test node:
hard detection;
possible detection;
soft detection;
hypertrophic detection;
tri-state detection;
oscillating detection;
undetected fault.
Information on the types of detections is listed in the sub-topics that follow this topic.
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Hard Detected Faults
Possible Detected Faults
Soft Detected Faults
1.13.1 Hard, Possible, and Soft Detected Faults
Before fault simulation begins, a fault is applied to each of the faulted circuits that will be
concurrently run for that pass of the test vectors. During fault simulation, the test vectors are
applied to the circuit inputs, and the results at the test nodes for each faulted circuit are compared
against the known fault free results from the reference simulation. An “actual” (or hard) detect for
a faulted node is reported when at least one test node's level differs between the faulted circuit and
reference circuit and neither level is an Unknown value. The time point that the hard detect occurs
at is recorded, and the fault is dropped for the remainder of the fault simulation. If the faulted
circuit has the same results as the fault-free circuit at each of the strobed time points, then the fault
is considered “undetected”.
Hard detects can be reported by using the “Fault Menu Selection” on page 4-37 or the “t/s
FAULTS/HARD” report (see “Fault Simulation Report” on page 6-9). Undetected faults can be
reported by using the “Fault Menu Selection” on page 4-37 or the “t/s FAULTS/UNDET” report.
A “soft” detect occurs at each strobe time that the test node for the faulted circuit is an unknown
level, and the level for the same test node in the good circuit is low or high, and only if the test
node in the faulted circuit has wiggled (been at low or high) since the last strobe time. The soft
detect count for a fault is incremented a maximum of 1 at each strobe time, regardless of the
number of test nodes that satisfy this criteria during strobing. Soft detects are reported as possible
detects when the number of soft detects for a faulted node equals the threshold value set by the
“Possible Detect Controls” box for the “Fault Sim Options” tab in the “Fault Simulation Settings”
dialog box (also see the “FCONTROL .NPDET” command “Fault Simulation Control Parameters”
on page 6-14).
When the possible detect threshold is reached, the default setting is to record the time point and
drop the possible detect fault from the remainder of the fault simulation. Possible detects can thus
mask hard detects. To continue checking for a hard detect after the possible detect threshold is
reached, uncheck the “Drop Possible Detects” check box for the “Fault Sim Options” tab in the
“Fault Simulation Settings” dialog box (also see the “FCONTROL .RETRYPOSS” command
“Fault Simulation Control Parameters” on page 6-14).
Possible detects can be reported by using the “Fault Menu Selection” on page 4-37 or the “t/s
FAULTS/POSS” report (see “Fault Simulation Report” on page 6-9).
(continued on next page)
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Hard Detected Faults
Possible Detected Faults
Soft Detected Faults
(Hard, Possible, and Soft Detected Faults)
When the number of soft detects for a net does not reach the threshold level, HyperFault calls this a
“soft” detect. HyperFault has a setup option to carry over the soft detect count between fault
simulations (see the “Carry Soft Count Forward” check box for the “Fault Sim Options” tab in the
“Fault Simulation Settings” dialog box, or the “carry_possible_counts=n” option for “Fault
Simulation Options ($fs_options system task)” on page 5-3). This is useful when the design is
being fault simulated by different sets of stimulus.
Soft detects can be reported by using the “Fault Menu Selection” on page 4-37 or the “t/s
FAULTS/SOFT” report (see “Fault Simulation Report” on page 6-9).
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Hypertrophic
1.13.2 Hypertrophic Faults
A fault is considered to be hypertrophic when the size of the faulted circuit reaches a specified
percentage of the total circuit size. Hypertrophic faults are listed as detected and then dropped
from the fault simulation (see hypertrophic option for the “Fault Simulation Options ($fs_options
system task)” on page 5-3). For most fault simulations, relatively few faults cause most of the
memory usage and the run time duration. By assuming that the hypertrophic faults will be detected
and dropping them early in the fault simulation run, the advantage is to reduce the fault simulation
run time and memory usage.
HyperFault stores the names of the hypertrophic faults in the fault dictionary file. Hypertrophic
faults can be run separately at the end of the fault simulation if the designer wants to verify that
they were detected (see “Iteration Controls” for the “Fault Sim Options tab:” on page 4-23 or the
“fsim/same-pattern-iterate” command “Fault Simulation Specification” on page 6-23.
Hypertrophic detects can be reported by “Fault Menu Selection” on page 4-37 or the “t/s
FAULTS/HYTRO” report (see “Fault Simulation Report” on page 6-9).
Hypertrophic Fault Diagram
Outputs
Inputs
ASIC chip
Size of fault effects
fault
A fault is hypertrophic when the size of the fault
effects exceeds a specified percentage of the total
circuit size.
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Tri-state Detection
1.13.3 Tri-state Detection
When the “Detect Mismatched 1/0 <-> Z (Tristate)” box is checked for the “Fault Sim Options
tab:” on page 4-23, or the !FCONTROL .TRISTATEDET command is specified, HyperFault
enables fault detection when a High-Z state is at a test node according to the following table:
reference circuit test node
faulted circuit test node
status
Z
0 or 1
detected
0 or 1
Z
detected
Z
Z
undetected
(see “TRISTATEDET” option for “Fault Simulation Specification” on page 6-23).
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Oscillating Faults
1.13.4 Oscillations During Fault Simulation
When a faulted node has caused a potential oscillation, it is excluded from further fault simulation.
Oscillating faults can be reported by the “Fault Menu Selection” on page 4-37.
To check for oscillations, HyperFault compares the iteration count of the circuitry affected by the
stuck fault against the iteration count of the identical fault-free circuit. If the iteration count for the
faulted circuit exceeds the iteration limit set by the “FCONTROL .FITR” command (see “Fault
Simulation Control Parameters” on page 6-14) before the next iteration for the fault-free circuit
occurs, then the faulted circuit is considered to be oscillating.
Oscillations during fault simulation are caused by two reasons:
The faulted node may cause a circuit with feedback to oscillate. Increasing the value for the
iteration limit set by the “FCONTROL .FITR” command may mask these oscillations as
undetected faults and will dramatically increase the fault simulation run times.
The circuit affected by the fault may have a long serial path for which the number of
iterations to resolve the circuit is greater than the value set by the iteration limit set by the
“FCONTROL .FITR” command. In general, each node in a serial path requires one iteration
to propagate a signal.
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Distributed
1.14 Distributed Fault Simulation
HyperFault has the ability to run a distributed fault simulation across specified CPUs. Distributing
the faults to computers on the network will reduce the execution time linearly by the number of
CPUs. For example, a fault simulation that takes 32 hours on a single computer would take 2 hours
when run on 16 computers using CPUs of similar speed and available memory.
With HyperFault, you can specify the amount of memory available on each machine (see “Memory
Usage Controls” on the “Fault Sim Options tab:” on page 4-23 or the “max_memory” option for
“Fault Simulation Options ($fs_options system task)” on page 5-3). HyperFault has the unique
ability to run multiple passes on each machine and automatically adjust the number of concurrent
faults on each machine so that the fault simulation is not swapped to disk.
The CPUs can be distributed across a network or they can be multiple processors on the same
machine.
Distributed fault simulation is specified by using “Distributed Process Selection Tab:” on page 421, or the $fs_options system task (see “Fault Simulation Options ($fs_options system task)” on
page 5-3). The Examples section of this manual has examples on distributed fault simulation. The
FMON command monitors the fault simulation progress for each process separately in the
process’s log file (see “Fault Monitor” on page 6-20). At the conclusion of distributed fault
simulation, the combined results for the master and slave fault simulations are reported in the
FAULTS report (see “Fault Menu Selection” on page 4-37).
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Increasing Speed
1.15 Increasing Fault Simulation Speed
Some Verilog HDL constructs can influence fault simulation speed:
Specify blocks will cause fault simulation to run slower. The delay values on individual
gates have no effect on fault simulation speed. However, using specify blocks will slow
down the fault simulation. To eliminate the specify blocks, check the “Functional
simulation” check box for the “Project Settings” dialog box. When “Functional simulation”
is checked, the rise and fall delays are set to "1" for all gates whose delays are not explicitly
specified to prevent race conditions.
Running a functional simulation will also prevent the “$sdf_annotate” system task from back
annotating the SDF delays.
Using the Standard Delay Format (SDF) to update delays will slow fault simulation.
The $readmemb or $readmemh system tasks are commonly used to load tabular stimulus
values into a memory variable, which is then accessed during fault simulation. This can take
large amounts of RAM memory. Another solution is to use the “stimulustable” statement
(for more information, see “Changing Behavioral Stimulus to a “stimulustable” Format” on
page 7-17). The “stimulustable” statement reduces memory usage by loading the stimulus
into memory in chunks, instead of all at once, like the $readmemb or $readmemh system
tasks.
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Accuracy
1.16 Fault Simulator Accuracy
Fault simulator accuracy can be verified by manually applying a stuck-fault at a single node to be
verified. Then two logic simulations are run:
one logic simulation is the reference circuit without any stuck nodes;
the other logic simulation has the node faulted manually.
After both logic simulations are run, the results can be compared (diffed) to determine if the
applied fault had a detectable effect on the test nodes.
When manually applying stuck-faults to a node, the following criteria should be used:
When applying an input-stuck fault to a module, simply replace the port name on the
appropriate module instance with a “0” for input-stuck-low faults or a “1” for input-stuckhigh faults. If the module input goes to more than one gate input, then you need to create a
separate copy of the module with a different name and have the module’s instance use the
new name. Next give the input to be faulted a unique name. Then use a Verilog “force”
statement or the HyperFault “FORCE” command to manually stick the node to a value.
When verifying output stuck faults, a “supply0” or “supply1”, a Verilog “force” statement or
the HyperFault “FORCE” command can be used to manually stick the node to a value.
When manually sticking a node for a sequential logic circuit, the fault should not be applied
until time=1, so that the circuit can initialize correctly.
The following procedure should be used to manually check the fault simulation results:
1)
Use a “$display” statement just after each “$fs_strobe” system task to display the values for
the same test nodes as specified by the “$fs_strobe” system task. To reduce clutter it is
useful to comment out all other $display and $monitor system tasks.
2)
Run two logic simulations, one with the fault stuck manually and the other a good (fault-free)
logic simulation. Store the output results for faulted circuit and the reference circuit in
separate files.
3)
Run a differences program to compare the two output files.
4)
Hard differences (High (1) and Low (0)) between the output levels indicate a detected fault at
the first time point that the levels differ (for more information, see “Hard, Possible, and Soft
Detected Faults” on page 1-34).
5)
An Unknown level at a test node for the faulted circuit and a High (1) or a Low (0) level for
the same test node for the good circuit indicates a possible detect (for more information, see
“Hard, Possible, and Soft Detected Faults” on page 1-34).
6)
No differences between the faulted and good circuit at the test nodes indicates an undetected
fault.
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HyperCov
1.17 HyperCov: Fault Coverage by Blocks
HyperCov reports in tabular format the fault coverage of individual blocks in a design hierarchy.
HyperCov is a separate program from HyperFault, and must be run from the Unix or Windows
system prompt.
One of the advantages of using HyperCov is it reports coverage of design sub-blocks. This can
reveal possible *skewing* in the coverage of the sub-blocks. For example, a HyperFault run may
show 90% coverage for the entire design composed of two blocks, “A” and “B”. However,
HyperCov can be used to reveal that sub-block “A”, containing only 20% of the faults has only
60% coverage while sub-block “B”, containing 80% of the faults, has 98% coverage. For more
information on HyperCov, see “HyperCov: Fault Coverage by Blocks” on page 6-33.
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List of Commands
1.18 List of Fault Simulation Commands
Below is a list of fault simulation commands, system tasks, and compiler directives (bold is
required syntax, plain is optional syntax, italics is user specified):.
Required Commands and System Tasks
Specify the Device Under Test
$fs_dut ( full_hierarchical_instance_name ) ;
Specify Test Nodes
$fs_strobe ( name.name, name.name, … , name.name );
Specify Faults (Note: at least one fault must be specified)
Specify Statistical Fault Simulation
voslow .pct = n
vohigh .pct = n
vilow .pct = n
vihigh .pct = n
Specify Faults Using Wildcards (Regular expressions, Verilog syntax)
vreslow “regular_expression”
vreshigh
“regular_expression”
vreislow “regular_expression”
vreishigh “regular_expression”
Specify Individual Faults
volow name.name…
vohigh name.name…
volow name.name…
vohigh name.name…
(continued on next page)
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List of Commands
(List of Fault Simulation Commands)
Optional Commands, Compiler Directives, and System Tasks
Control
Fault Simulation Control Parameters
fcontrol .carry_possible_counts=val .checkpoint_interval=time
.fbuildsave .fitr=value .fmem=value .fdcsave .npdet=value
.hypertrophic=val% retryposs=val .tristatedet .untestable=val
Specify Fault Simulation
fsim /
dict_only initial=time iterate list
quit
recover same-pattern-iterate
seed=value
Reports
Fault Monitor
fmon
.detail
Lack-of-Activity Report
t/p/s activity t1 to t2 / keywrd = value, keywrd…
Fault Simulation Report
t/p/s faults / keywrd, keywrd …
Fault Coverage Reporting by Blocks
hypercov [-a | -b | -f ] [-lnn] [-tnnnn] dictionaryFileName [ VerilogPath …]
Library Options
Suppressing Faults
`suppress_faults
module definitions …
`nosuppress_faults
Port Faults
`enable_portfaults
module definitions …
`disable_portfaults
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List of Commands
(List of Fault Simulation Commands)
(Optional Commands, Compiler Directives, and System Tasks)
Single Processor Fault Simulation Options
$fs_options (
“max_memory = n ",
“hypertrophic=’n’ ”,
“checkpoint_interval=time”,
"carry_possible_counts=n”,
);
Distributed Fault Simulation Options
Options for the Master Process
$fs_options (
Additional Options for the Master Process
"process_weight = n " ,
"faults_per_pass = n " ,
“max_memory = n ",
“hypertrophic= ‘n’ ”,
“checkpoint_interval=time”,
"carry_possible_counts=n”,
"sample = n " ,
“retry_possible_detects=n”,
“process_name= ‘ ‘ ”,
);
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List of Commands
(List of Fault Simulation Commands)
(Optional Commands, Compiler Directives, and System Tasks)
Options for a Slave Process
$fs_options (
Required Options for a Slave Process
"process_name = 'name' " ,
"process_hostname = 'hostname' " ,
Additional Options for a Slave Process
"process_weight = n " ,
"process_command = ' command ' " ,
"faults_per_pass = n " ,
“max_memory = n ",
“hypertrophic= ’n’ ”,
“checkpoint_interval=time”,
"carry_possible_counts=n”,
"process_nfs_prefix = ' prefix ' " ,
// Unix only
"process_mount_point = ' mount ' " ,
// NT only
"nt_net_use = ' string … string ' "
// NT only
“retry_possible_detects=n”,
);
Exclude Output Stuck-at Faults (SILOS syntax)
xlow (name(name (name(name … (name(name
xhigh (name(name (name(name … (name(name
Exclude Input Stuck-at Faults (SILOS syntax)
xilow (name(name (name(name … (name(name
xihigh (name(name (name(name … (name(name
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List of Commands
(List of Fault Simulation Commands)
(Optional Commands, Compiler Directives, and System Tasks)
Exclude Output Stuck-at Faults Using Wildcards (Regular expressions, Verilog syntax)
vrexslow “regular_expression”
vrexshigh
“regular_expression”
Exclude Input Stuck-at Faults Using Wildcards (Regular expressions, Verilog syntax)
vreixslow “regular_expression”
vreixshigh “regular_expression”
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Installation
2. Installation
2.1 Steps for Evaluating HyperFault
Listed below are the steps that should be followed when evaluating HyperFault:
Steps:
Completed:
1) Install HyperFault.
2) Setup the design files for logic simulation.
3) Verify the ability to read the design files (with no parse errors).
4) Run HyperFault logic simulation.
5) Verify logic simulation results against the evaluator’s reference simulator.
6) Obtain the memory usage statistics from logic simulation.
7) Setup the design files for uni-processor fault simulation.
8) Run a trial fault simulation by naming a few faults or by performing a 1%
fault simulation.
9) Setup design files for distributed fault simulation.
10) Run a trial distributed fault simulation.
2.1.1 Installation Notes:
1)
Obtain the memory usage statistics from logic simulation for estimating the memory usage
for fault simulation. Memory usage can be obtained by entering the -“!size” command after
running logic simulation. For example, the additional commands to add to the end of the “-f”
command file (or project_name.mfv file) to run logic simulation would be:
-“!sim”
-“!size”
-“!error”
-“!exit”
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Installation
(Steps for Evaluating HyperFault)
The memory usage from the size report is shown on the first entry of the size report. For
example, a circuit of 632,828 devices had the following size report entry:
Arena sizes:
/
size=469455872 free=16453120 used=453002752
The circuit size is 469,455,872 bytes for the above size report entry. Simucad recommends
using at least twice as much memory for the fault simulation as for the logic simulation. To
find out the amount of memory available and CPU speed on a Sun computer running Solaris,
see “Available Memory and CPU Speed for ” on page 2-13.
2)
To setup the design files for uni-processor fault simulation, see “Example for Batch Fault
Simulation” on page 3-39.
3)
To setup design files for distributed fault simulation, see “Example For Distributed Fault
Simulation” on page 3-34 or “Fault Simulation Options ($fs_options system task)” on page
5-3.
4)
There are system parameters for Unix that can be set if HyperFault has memory problems
during execution:
•
If “Out of Memory” messages occur, use the Unix limit command to check and set that the
“datasize” is set to 2 gigabytes. Below is an example of the Unix limit command:
Unix_prompt%
cputime
filesize
datasize
stacksize
coredumpsize
descriptors
memorysize
limit
unlimited
unlimited
2097148 kbytes
32000 kbytes
unlimited
64
unlimited
To set the datasize limit, you could enter at the Unix prompt:
limit datasize 2000000000
•
If HyperFault has a core dump during fault collapsing, use the Unix limit command to check
and check that the “stacksize” is set to be 32 megabytes .
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Installation
2.2 Microsoft Windows Installation
2.2.1 Minimum System Requirements for the PC:
1)
P5, or P6 Personal Computer.
2)
Microsoft Windows NT (version 4.0 or higher), or Microsoft Windows 2000.
3)
At least 64 MB available memory recommended. Memory usage varies depending on the
design, and the fault simulation will take at least two times as much memory as the logic
simulation. Memory usage for RTL designs is difficult to estimate, however, RTL designs
generally take much less memory than an equivalent gate level design.
4)
The HyperFault installation requires less than 50 Mb of disk space.
2.2.2 Materials Required:
1)
HyperFault CD-ROM.
2)
HyperFault security block with serial number (the security block is for the parallel port), or a
FLEXlm network (floating) license.
3)
HyperFault license from Simucad (User’s Certificate or e-mail or fax from Simucad).
(continued on next page)
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Installation
2.2.3 Windows NT and Windows 2000 Installation:
To install HyperFault, do the following steps:
1)
Insert the HyperFault CD-ROM into the CD-ROM drive.
2)
Using the Windows Explorer, double-click on file “SETUP.EXE” on the CD-ROM.
3)
Answer the questions when prompted by the HyperFault installation program. For the
installation directory you can use any valid name that does not have embedded spaces.
The installation will attempt to create the directory if it does not already exist.
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Installation
(Windows NT Installation)
4)
To install the new security code that you obtained from Simucad:
During installation of HyperFault from the CD-ROM, the installation will ask you if
you would like the installation script to set the SIMUCAD_LICENSE_FILE
environmental variable path to the “silos.lic” file in the installation directory. Click
on “yes”.
For Windows NT, the SIMUCAD_LICENSE_FILE environmental variable path is
set in the Environment tab for the System applet in the Control Panel. For Windows
2000, the SIMUCAD_LICENSE_FILE environmental variable path is set in the
Environment button for the Advanced tab for the System applet in the Control Panel.
•
If the security code that you received from Simucad does start with the keyword
“SERVER”, then this is a floating license. You can enter the security code for a
floating license into the file “silos.lic” in the installation directory for HyperFault (or
any other file and point the SIMUCAD_LICENSE_FILE environmental variable to
the file). An example security code would be:
SERVER yourhost 809d6936 TCP:14443
VENDOR simucad
FEATURE Sse simucad 99.101 01-jul-2000 3 6639804D2588 ck=125
To start a floating license, the license server must be running Windows NT or
Windows 2000. To start the floating license, open a DOS command style window.
Change directories to the installation directory for HyperFault. Then enter the
following command at the DOS prompt:
lmgrd -c path_to_hyperfault_license\silos.lic -l flexlm.log
Where “path_to_hyperfault_license” is the path to the silos.lic security license from
Simucad. If you have problems, you can review the flexlm.log file for diagnostic
messages, and you can use the “lmdiag” program to run diagnostics on the license.
Note:
1)
You can put the security license for more than one version of HyperFault in
the same “silos.lic” file, and FLEXlm is smart enough to search all of the
FEATURE lines to find the correct license.
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Installation
(Windows NT and Windows 2000 Installation)
5) If you have problems starting HyperFault after installing the SILOS III cdrom and the
FLEXlm license, the error message returned from FLEXlm is important for determining
the cause of the problem:
If the error message states “License Error: Invalid host”, click on the OK button for
the error message. The User Registration dialog box will then appear. If the Serial #
in the User Registration dialog box is “0”, then the problem is FLEXlm cannot access
the security block. Try the following to correct the problem:
Install the security drivers for FLEXlm from the Drivers directory on the
HyperFault CD-ROM.
Ensure the parallel port is working by printing from it, or trying another program
that uses a security block.
Ensure the HyperFault security block works by trying it with HyperFault on
another computer, or trying another HyperFault security block on your computer.
Ensure that nothing else on the parallel port is interfering with the HyperFault
security block, such as the security block from another program that is also
attached to the parallel port. If this is the problem, you can resolve it by installing
another parallel port (HyperFault automatically searches all of the parallel ports
for the security block), or installing a straight through cable or switch box to
make it easier to switch security blocks.
If the error message states “License Error: No such feature exists”, notice the
“License path:” entry for the path to the license file. Try the following to correct the
problem:
Ensure the path for the license file is correct and the “silos.lic” license file exists.
For Windows NT, the SIMUCAD_LICENSE_FILE environmental variable path
for the “silos.lic” file is set in the Environment tab for the System applet in the
Control Panel. Check to ensure the SIMUCAD_LICENSE_FILE environmental
variable is set in both the System environment and the User environment for the
System Applet. For Windows 2000, the SIMUCAD_LICENSE_FILE
environmental variable path is set in the Environment button for the Advanced tab
for the System applet in the Control Panel.
Ensure that the requested feature, such as Feature: Sse”, is in the license file.
If the error message states “License Error: Invalid (inconsistent) license key”, try the
following to correct the problem:
Ensure that the security code from the License Certificate from Simucad was
correctly entered into the license file.
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Installation
(Windows NT Installation)
5) (continued)
If the error message states “the ordinal “xyz” could not be located in the dynamic link
library dll_file_name.dll”, try the following to correct the problem:
Make sure that you have administrator privileges when installing HyperFault so
that you have permission to overwrite the .dlls. You will also have to reboot the
system to have the .dlls updated.
The installation directory includes a “README” file and on-line help. The on-line
“TUTORIAL” can be accessed by selecting Help/Contents from the HyperFault program, and
then clicking on topics in the “Tutorial Chapter” entry.
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Installation
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2.2.4 Finding the Computer Name and HOSTID for PC Computers
To obtain the six digit serial number for the Simucad security block on your parallel port, select
Help/User Registration (if you already have a security block).
To obtain the FLEXlm hostid for a security code that uses the hostid for your PC computer instead
of a security block, open a DOS style Command Prompt window on your PC, “cd” to the
installation directory for HyperFault, and enter “lmutil lmhostid” at the system prompt for your PC.
One method to obtain the computer (network) name for a machine is to open the Control Panel by
selecting "Start/Settings/Control-Panel. In the Control Panel, double-click on the Network applet.
Then read the -"Computer Name" on the Identification-tab in the Network dialog box.
2.2.5 Finding the Size of RAM Memory for PC Computers
One method to obtain the size of RAM memory for a PC computer is to open the Control Panel by
selecting "Start/Settings/Control-Panel. In the Control Panel, double-click on the System applet.
For the “General” tab, read the RAM memory listed under the “Computer” heading.
2.2.6 Accessing Unix Floating Licenses from PC Computers
If you have a purchased a floating license for your Unix computer and you wish to checkout a
license from your PC computer that is on the same network:
Install HyperFault on your PC computer (if you have not already installed HyperFault). The
“SIMUCAD_LICENSE_FILE” environmental variable should be pointing to the silos.lic file
in the HyperFault installation directory.
In the HyperFault installation directory on your PC computer, rename the silos.lic file to
silos.lic.old, just in case you have a node locked license on your PC and you want to keep a
copy of it.
Copy the silos.lic floating license file from your HyperFault installation directory on Unix to
the HyperFault installation directory on the PC computer.
When you run the hse.exe or the hyperflt.exe on the PC computer, it will automatically use
the information in the silos.lic file and check the network to access the floating license on the
Unix computer. If there is a problem, verify if your PC can access the Unix machine using
another method (ftp, ping, etc.), and check that the “HOSTS” file is correct in the
“\winnt\system32\drivers\etc” directory.
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Installation
(Windows NT Installation)
2.2.7 Running HyperFault
To start the interactive version of HyperFault, use the Windows “Start” menu, then select Programs
to access the SILOS III group, and select the HyperFault Simulation Environment.
To put the HyperFault icon on the desktop, use the Windows Explorer to navigate over to the
HYPERFAULT installation directory. Highlight file “hse.exe” using the Windows Explorer.
From the File menu for the Windows Explorer, select “Create Shortcut”. This will create a
shortcut to the hse.exe in the Windows Explorer, which you can then drag and drop onto the
desktop.
To run fault simulation in the batch mode, open a DOS style Command window and enter
“hyperflt” at the command prompt. For information on running HyperFault in the batch mode, see
“Example for Batch Fault Simulation” on page 3-39.
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Solaris
2.3 Solaris Installation Instructions
2.3.1 Material Required:
1)
HyperFault CD-ROM.
2)
HyperFault security license.
2.3.2 HyperFault CD-ROM Loading
Place the CD-ROM into the CD-ROM holder for your machine and close the CD-ROM door. For
Solaris, the CD-ROM is automatically mounted.
To run the installation script on Unix, you will need to enter the following commands at the Unix
prompt:
cd /cdrom/unix
./Install.
The installation script will guide you through the process of installing HyperFault. For the
installation directory you can use any valid name without embedded spaces. The installation will
attempt to create the directory if it does not already exist.
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Solaris
2.3.3 Unix Security File
After the installation from the install script is complete, you may need to do the following:
Change directories to the installation directory for HyperFault.
Use the security information provided by Simucad to create file “silos.lic” in the installation
directory.
If the security information does have “SERVER” lines, then this is a floating license. To test to see
if FLEXlm is running, enter “bin/lmstat” at the Unix prompt from the HyperFault installation
directory. If FLEXlm is not running, then you will need to run file “bin/startflexlm” in the
installation directory for HyperFault as a root user.
If you try to start FLEXlm and it is not running when you enter “bin/lmstat”, then review the
bin/flexlm.log file to see if there are any problems.
If security information is not provided by Simucad, then you may have to contact Simucad, and
provide your hostid and machine name to have a new file created for you.
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Distributed Fault Simulation on Unix
2.3.4 Distributed Fault Simulation on Unix
To setup distributed fault simulation on Unix, you need to ensure that your network has the
following capabilities:
The installation directory for HyperFault needs to be mounted on each of the slave
computers. For example, if HyperFault is installed on computer “A” in directory
“/export/home/hyperfault”, then if you enter the command “ls /export/home/hyperfault” at
the Unix prompt on a slave computer, you should see the list of files for the HyperFault
installation directory from computer “A”.
The directory that has the project file (.spj file) needs to be mounted on each of the slave
computers. For example, if your project file is in directory
“/export/home/hyperfault/examples” on computer “A”, then if you enter the command “ls
/export/home/hyperfault/examples” at the Unix prompt on a slave computer, you should see
the list of files for directory “/export/home/hyperfault/examples” on computer “A”.
You need to have read/write permission from each slave computer to the directory that has
the project file (.spj file) for the fault simulation. For example, if your project file is in
directory “/export/home/hyperfault/examples” on computer “A”, then you need to be able to
enter “touch /export/home/hyperfault/examples/test_file” from the Unix prompt on each
slave machine and create file “test_file” in the directory “/export/home/hyperfault/examples”
on computer “A”.
You should be able to enter the “rsh” command without using a password from the master
computer to start a remote shell on each slave computer. For example, if you enter the
command:
rsh slave_computer_name “ls /export/home/hyperfault”
at the Unix prompt on the master machine, you should be able to start a remote shell on the
slave computer that lists the files for the HyperFault installation directory from computer
“A”.
If you have problems running distributed fault simulation on Unix, try the following steps:
Look in the Output Window for the HSE, or the log file for the project, and find the
command to start the slave process that is having a problem.
At the Unix prompt for the master computer, try entering the first part of the command to
start that slave process and ensure that it works when this is run by hand.
At the Unix prompt for the master computer or the slave computer (as appropriate), enter the
rest of the command to start the slave process and ensure that it works when you run it by
hand.
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Solaris
2.3.5 Hostid and Hostname for Solaris and HP
To find out your host id (in hex) on the Solaris operating system, enter the following command at
the Unix prompt:
hostid
To find out your host name on the Solaris operating system, enter the following command at the
Unix prompt:
hostname
To find out your host id (in decimal) on the HP computer, enter the following command at the
Unix prompt:
uname –I
2.3.6 Available Memory and CPU Speed for Solaris
To find out the amount of memory available on a Sun computer running Solaris, enter the
following command at the Unix prompt:
dmesg
The available memory will be reported along with other statistics. For example, the below
entry shows this Sun has 3 gig of available memory:
avail mem = 3183763456
Memory usage during fault simulation is different for every circuit and set of vectors.
HyperFault has a “max_memory” parameter that can be used to limit the memory usage for
fault simulation so that it does not swap (see “Fault Simulation Options ($fs_options system
task)” on page 5-3). The “max_memory” parameter should be set to something less then the
available memory, leaving enough memory for the operating system and other processes. On
a 1 gig Sun, you may want to set the max_memory parameter to 900 meg. Contact your local
distributor or Simucad for benchmark data on circuit size and memory usage.
To see how much memory HyperFault is using during preprocessing, the easiest way would
be to enter "ps -el" periodically at the Unix prompt. On the "ps" output from Unix, there will
be a line with "silos" in the "COMD" column. On that line, write down the number under the
"SZ" column. For some Solaris computers, every 6000 units in the "SZ" column corresponds
to about 50Meg, i.e. memory-in-use = SZ * 50 / 6000, where the resulting number is in units
of MB. For example, if "SZ" is 109958 then memory-in-use is 109958 * 50 / 6000 =
916MB.
You can find out the speed of your Sun computer by entering the following command at the
Unix prompt:
/usr/sbin/psrinfo -v
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Solaris
2.3.7 Running HyperFault
To run the command line version of HyperFault for fault simulation, enter:
runfault
To run the Graphical User Interface (GUI) version of HyperFault for fault simulation, enter:
runhse
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Linux
2.3.8 Linux Installation Instructions
2.3.8.1 Material Required:
1) HyperFault CD-ROM.
2) HyperFault security code.
2.3.8.2 SILOS III CD-ROM Loading
Place the CD-ROM into the CD-ROM holder for your machine and close the CD-ROM door.
To run the installation script on Linux, you will need to be the “root” user, and bring up the Linux
installation GUI by entering the following command at the Unix prompt:
gnorpm
In the “Gnome RPM” dialog box select the Packages/Applications/Engineering menu. Next click
on the “Install” button to bring up the Install dialog box. Click on the “Add” button in the “Install”
dialog box to bring up the “Add Packages” dialog box. Navigate in the Directories box for the
“Add Packages” dialog box until you get to the “/mnt/cdrom/Unix” directory on the SILOS III
CDROM. Select “silos.rpm” in the right hand window of the “Add Packages” dialog box. Click
on the “Add” button in the “Add Packages” dialog box, and click on the “Close” button in the
“Add Packages” dialog box after the Silos application icon is added beneath the
Packages/Applications/Engineering menu in the “Install” dialog box. Click on the “Install” button
in the “Install” dialog box. An “Installing” dialog box will appear that has progress bars for the
installation. When the installation is complete, you will see the Silos application icon in the main
window for the “Gnome RPM” dialog box. Now you can exit “Gnome RPM” by clicking on the
“x” in the upper right hand corner. HyperFault has now been installed in the “/usr/local/simucad”
directory on your computer.
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Linux
2.3.8.3 HyperFault Security File
After the installation from the install script is complete, you may need to do the following:
•
Change directories to the installation directory for HyperFault.
•
Use the security information provided by Simucad to create file “silos.lic” in the installation
directory.
If the security information does have “SERVER” or “DEAMON” lines, then this is a floating
license. To test to see if FLEXlm is running, enter “bin/lmstat” at the Unix prompt. If FLEXlm is
not running, then you will need to run file “bin/startflexlm” in the installation directory for
HyperFault as a root user.
If you try to start FLEXlm and it is not running when you enter “bin/lmstat”, then review the
bin/flexlm.log file to see if there are any problems.
If security information is not provided by Simucad, then you may have to contact Simucad, and
provide your hostid and machine name to have a new file created for you.
2.3.8.4 Hostid and Hostname for Unix
To find out your host id (in hex) on the Linux computer, enter the following command at the Unix
prompt:
hostid
To find out your host name on the Linux computer, enter the following command at the Unix
prompt:
hostname
To find out which version of Linux you are running on a Linux computer, enter the following
command at the Unix prompt:
uname –a
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Linux
2.3.8.5 Running HyperFault
To run the command line version of HyperFault for fault simulation, enter:
runfault
The HyperFault copyright notice, version number, etc. will appear on your screen. You can then
enter HyperFault commands at the “Ready:” prompt for inputting files, simulating, etc.
To run the Graphical User Interface (GUI) version of HyperFault for fault simulation, enter:
runhse
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Technical Support
2.4 Accessing Technical Support
Simucad offers technical support to customers on maintenance. It is most efficient to contact
Simucad's technical support via e-mail:
support@simucad.com
When sending problem circuits to Simucad, please send the complete circuit that can be run to
duplicate the problem, including any libraries and the “.spj” file. Also enclose a few sentences that
precisely state the problem and how to run the circuit, for example:
At time=200, node “top.out1” should be high instead of unknown. To run the circuit, use
project “problem.spj”.
From a PC system, the following PKZIP commands may be the simplest way to e-mail a circuit:
pkzip -Pr foo.zip directory_name\*.*
Then e-mail support@simucad.com and attach the file using uuencode.
From a Unix system, the following Unix commands may be the simplest way to e-mail a circuit:
tar cvf foo file1 file2 ...
compress foo
uuencode foo.Z < foo.Z > foo
Edit file “foo” to briefly describe the problem, then enter:
mail support@simucad.com < foo
Simucad's mailing address, phone number, and fax number are:
Simucad, Inc.
32970 Alvarado-Niles Road
Union City, CA. 94587
Phone:
(510) 487-9700x206
Fax:
(510) 487-9721
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Tutorial
3. Fault Simulation Tutorial
3.1 Fault Simulation Examples Overview
Skills presented in the fault simulation examples are:
Understanding the steps for fault grading test vectors.
Setting up a project using the HyperFault Simulation Environment (HSE).
Logic simulation and toggle reporting.
Setting up and running the project as a statistical fault simulation.
Setting up and running the project as an incremental fault simulation.
Setting up and running the project as an iterative fault simulation.
Setting up and running the project as a distributed fault simulation.
Running a batch fault simulation.
3.1.1 General Items for Tutorial
The flow for running the Tutorial assumes that you will follow the topics in the order they are
listed. If you skip some topics then you may not have performed necessary steps for each topic.
The files used for the Tutorial examples can be found in the “examples” subdirectory for the
HyperFault installation directory. For additional examples provided in the “examples”
subdirectory, see the README file in the installation directory.
Please note:
Actions that you should do to run this tutorial are in bold.
“Click-on” means place the mouse cursor on the appropriate item, and click and release on
the item using the left mouse button.
You can see the tool tips (text labels) for each of the buttons on the Toolbars for the HSE by
placing the mouse cursor over a button for a few seconds until the text label for the button
appears. Then move the mouse along the Toolbar and stop at each button to see the text
label. There can be more than one Toolbar (see "Main Toolbar menu selections" on page 49). The location of each Toolbar on the screen can be changed by using the mouse to grab an
edge of a toolbar and dragging the toolbar to the desired location.
The menus for the HSE change depending on which window has the focus, for example the
Data Analyzer Window has different menus from the Output Window.
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Fault Simulation Steps
3.1.2 Fault Grading Process
The process of developing and fault grading test vectors is shown below:
Fault Simulation Steps
Testbench
ALU
1st subset
Logic Simulation
nd
memory
other
2 subset
1st subset
2nd subset
1st subset
Activity Report
2 subset
(ensure all nets toggle)
more subsets
Statistical
Fault Simulation
nd
ALU
Pre-grade test
vectors
more subsets
Create additional
vectors by hand
Incremental
Fault Simulation
Create 95%99% fault
coverage
(apply more test vectors)
Statistical
Fault Simulation
(vary random number seed)
Confirm fault
coverage
accuracy
100%
Fault Simulation
(Optional)
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Fault Simulation Steps
(Fault Grading Process)
Most novice fault simulation users immediately start running fault simulation using their largest set
of test vectors and selecting 100% of the available faults. Imagine how surprised they are at how
long an incorrectly setup fault simulation can take. Instead, start with a toggle report (Activity
report) for logic simulation to ensure all of the nets toggle, and then choose a statistical fault
simulation (smallest sample greater than 400 faults) with the shortest set of test vectors targeting a
single component or part of the design.
The simplest method for developing test vectors for fault simulation is to start with the test vectors
from logic simulation. Typically the logic simulation vectors are organized to separately verify
each component or block of components in the design. To fault grade these test vectors, the
designer should choose the beginning subset of the test vectors for each component in the design.
Usually the first vectors for each component detect most of the faults for the component. Do not
just use the entire set of the functional test vectors from logic simulation for fault simulation. The
redundant test vectors may substantially increase the run time and memory usage during fault
simulation. The redundant test vectors may also substantially increase the cost of using the tester
at the ASIC foundry.
The steps for fault grading test vectors for fault simulation are shown in the diagram on the
previous page. For each step of the fault grading process, the user will add to the test vectors or
add new tests until a high fault grading is attained, such as 95% to 99% of the possible faults
detected.
This Tutorial shows each step of the fault simulation process:
•
The “Example for Logic Simulation and Toggle Report” on page 3-15 shows the nets that do
not toggle during simulation. Nets that do not toggle cannot be detected when faults are
applied during fault simulation. Logic simulation will run faster and in less memory than a
fault simulation, which can save the user a substantial amount of time.
•
The “Example for Statistical Fault Simulation” on page 3-17 uses a 10% random sample to
reduce the fault simulation run time by a factor of 10.
•
The “Example for Incremental Fault Simulation” on page 3-28 fault grades additional test
vectors. Simulating only the undetected faults from previous fault simulations reduces the
run time.
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Fault Simulation Steps
(Fault Grading Process)
•
The “Example for Iterative Fault Simulation” on page 3-31 tests if the hypertrophic detected
faults would have been a hard detection (see “Hypertrophic Faults” on page 1-36).
Hypertrophic faults are considered as detected and dropped early to reduce the run time. The
designer can then fault grade the rest of the faults, and consider the hypertrophic faults at the
end. Many times the number of hypertrophic faults is so few when compared to the total
number of faults that their effect on fault grading the test vectors is not important. However,
their run time and memory usage can be significant.
•
The “Example For Distributed Fault Simulation” on page 3-34 reduces fault simulation run
time by distributing the fault base across a network of computers. Each additional CPU
provides a linear reduction in the run time.
For additional information on developing the test vectors for fault simulation, see “Developing
Test Vectors” on page 1-9.
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Starting the HSE
3.2 Fault Simulation Setup for the HSE Examples
This section explains how to setup a project for fault simulation.
3.2.1 Starting HyperFault (GUI Examples)
At the Unix prompt, enter “runhse” from the installation directory for HyperFault.
For the PC, use the Windows Start/Programs menu to start HyperFault. If you made a shortcut to
the “hse.exe” executable on the PC, you can double-click on its icon to start HyperFault (see
“Running HyperFault” on page 2-9).
3.2.2 Accessing On-line Help
Benefit
The complete HyperFault, Verilog HDL, and SDF manuals available as on-line help files.
These manuals are also in the “doc” subdirectory in the HyperFault installation as “.pdf” files
for viewing and printing. This provides easy access and lookup for answers to reference
questions.
Procedure
To access the on-line help for HyperFault:
Select the Help menu selection.
“Contents” will display the
contents for the Hyperfault
User’s Manual.
Hyperfault User's Manual
“About HyperFault” shows
the version number and the
logic engine memory usage.
2001.1xx
“User Registration” will
show the security block
number or ID of the
computer.
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On-line Help
The following manuals are provided as on-line help files:
HyperFault User's Manual (Help/Contents will also select this);
Verilog LRM (Open Verilog International (OVI) Verilog Language Reference Manual
version 1.0);
SDF Manual (OVI Standard Delay Format (SDF) Manual version 2.0);
For example, to locate help on the “Project/New” menu selection in the Menus Chapter (the next
item in the tutorial):
Click on the “Projects” menu selection, and scroll down and highlight the “New” menu
selection but do not release the left mouse button. With the left mouse button still held
down, press and release the “F1” key and the on-line help entry for Project/New will pop up
(not available on Unix).
Highlight “Project/New” and
press and release the “F1”
key on the keyboard to see
the on-line help.
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New Project
3.2.3 Creating a Project
Benefit
Projects provide easy access to the input files and libraries for a design.
Any member of the design team can open the project file and immediately be in the project.
All of the settings to run the design and organize the signal names for viewing waveforms are
remembered by the project, so that useful debugging can be immediately started after
simulating the design.
Procedure
The circuit for this example is a drink vending machine that has been synthesized, and back
annotated using SDF.
The files used for this example are listed in the README file.
This section shows you how to create a new project for inputting your source files and library files.
Project name “faultsim”
Select the “Project/New” menu selection to open the “Create New Project” dialog box.
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Project Files
To change directories to the “examples” subdirectory of the installation directory, you can
use the drop-down arrow for the “Save in” box and/or the “Up One Level button” in the
“Create New Project” dialog box.
In the “File name” box, enter “faultsim” for the project name, and then click-on the “Save”
button to close the dialog box. The HSE will automatically append the suffix “.spj” to the
project name if you do not add a suffix to the project name.
The “Project Files” dialog box will be automatically opened so that you can specify the input files
for the project.
Double-click on a file
name to add it to
project.
Use the drop-down
arrow to access
library files. Do not
input library files as
source files.
Verilog source files
for the project.
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Project Files
To input the file for project “faultsim.spj”:
Double-click on file “faulttst.v” in the list box for the examples subdirectory to add
“faulttst.v” to the “Files in Group” list box . File “faulttst.v” is an example of a file the user
would create to strobe the test nodes for fault simulation. Notice that the test nodes can be
strobed from a file and module that is separate from the user’s design.
Notice the “File Group” box has a drop down arrow for specifying library files. Do not input
library files as source files, because then every part in the library is read into memory, which
will increase the run time and memory usage.
Now click-on the “OK” button to close the “Project Files” dialog box.
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Project Settings
3.2.4 Command Line Arguments
Benefit
You may already have a design that uses Verilog command file(s) to run the logic
simulation. The same Verilog command files can be used to run HyperFault. This section
shows how to enter the Verilog command file(s).
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Project Settings
Procedure
Specify the Verilog
command file for the
design.
Check the “Enable
log file” check box.
Select the “Project/Project Settings” menu selection to open the “Project Settings” dialog
box.
In the “Command Line Arguments” box, enter “-f design1” to specify the command file for
the design.
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Project Settings
(Command Line Arguments)
Check the “Enable Log File” check box to enable the log file.
Click-on the “OK” button to close the “Project Settings” dialog box. Answering “No” to
the message box for reloading the project (if it appears on your screen) will let you see the
message box again in the future.
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Device Under Test
3.2.5 Device Under Test
Benefit
Fault effects are constrained to the device under test by specifying that the device under test
does not include the testbench. This ensures that fault effects do not enter the testbench.
There are restrictions on hierarchical names inside the device under test (they can not
reference other variables in the device under test). Hierarchical names can be used to probe
from outside of the device under test (the testbench) down into the design. For more
information on the device under test, see “Device Under Test (DUT)” on page 1-15.
Procedure
Select the “Project/Fault Simulation Settings” menu selection to open the “Fault Simulation
Settings” dialog box.
•
For the “Fault Selection Tab”:
•
In the “Devices Under Test” box, enter “stimulate.dm” to specify the device under test
(DUT) for the design.
Click-on the “OK” button to close the “Fault Simulation Settings” dialog box.
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Device Under Test
(Device Under Test)
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Activity Report
3.3 Example for Logic Simulation and Toggle Report
Benefits
•
Logic simulation should be run to verify that the circuit simulates correctly before running
fault simulation. This is especially important if the logic simulations have been previously
done with another Verilog simulator. Obtain a toggle count (Activity report) to preview
subsets of the test vectors for their effectiveness for detecting faults. The Activity report lists
nets that have no activity (level transitions) during logic-simulation. Nets that do not toggle
can not be detected when faults are applied to them during fault simulation. The advantage
of using the Activity report is the logic simulation will run faster and use less memory than a
fault simulation.
Clicking on the “Go” button is all that is required to run logic simulation for the project.
Procedure
Go Button
Output Window
Click-on the “Go” button on the Toolbar to load the input files and run logic simulation.
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Activity Report
(Example for the Activity Report)
Select the “Reports/Activity” menu selection to obtain the toggle report of the nets that do
not transition during logic simulation.
This net was
always at a
low level for
the
simulation.
This net
transitioned one
time from
unknown to
either a low or a
high.
•
For your design, you should continue to add test vectors and rerun logic simulation until all
of the nets toggle (no nets are listed by the Activity report). For this tutorial, the test vectors
are increased in the “Example for Iterative Fault Simulation” on page 3-31.
This concludes the example on Activity report for fault simulation.
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Fault Sim Settings
3.4 Example for Statistical Fault Simulation
3.4.1 Fault Simulation Setup
Benefit
The HyperFault Simulation Environment (HSE) supports a Graphical User Interface (GUI)
for specifying fault simulation commands, making the fault simulation setup simple to use
and learn.
Using the HSE for setting up fault simulation also simplifies running the fault simulator in
batch. The command file “faultsim.cfv” created by the HSE can be used to load the design
for fault simulation in a batch run (see “Example for Batch Fault Simulation” on page 3-39).
Procedure
Close the HSE if it is still open from running the logic simulation, and then restart the HSE
program. “faultsim.spj” should be the current project.
Select the “Project/Fault Simulation Settings” menu selection to open the “Fault Simulation
Settings” dialog box.
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Fault Sim Settings
(Fault Simulation Setup)
Device Under Test
(your design).
Regular expressions to apply
faults to a block of the design.
When a tab has the focus, press and release the
“F1” key on the keyboard to reach on-line help
for that tab.
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Fault Sim Settings
(Fault Simulation Setup)
•
For the “Fault Selection Tab”:
•
In the “Devices Under Test” box, enter “stimulate.dm” (if you have not already done this
for the “Fault Simulation Setup for the HSE Examples” on page 3-5). For more
information on the device under test, see “Device Under Test (DUT)” on page 1-15.
•
Uncheck the “Select all possible faults” checkbox. This will allow you to enter regular
expressions to select the faults.
For the “Regular Expressions”, enter stimulate\.dm\..* for each type of fault, “Input Stuck
Low”, “Input Stuck High”, “Output Stuck Low”, “Output Stuck High”. The regular expression is
used to probe down into the design to select one or more blocks of faults. This enables you to
synthesize RTL code to the gate level, and then apply the faults to the gate level block, and run the
fault simulation on the entire design, part at the RTL level and part at the Gate level. For this
example, the design is so small that the entire design under test is selected by a regular expression.
Notice in the regular expression “stimulate\.dm\..*”, the periods denote hierarchy that is escaped
by a backslash (“\.”). The final “.*” is a regular expression that will find all occurrences of zero or
more characters that are preceded with the hierarchical name “stimulate.dm.”. If you want to “or”
regular expressions together, simply use a space to separate each regular expression that you wish
to “or” (the “||” and “&&” operators are not supported by regular expressions), i.e.
test_bench\.test1\..* test_bench\.test2\..*
•
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Fault Sim Settings
(Fault Simulation Setup)
Next click on the “Fault Sampling Tab”:
•
For each type of fault, “Input Stuck Low”, “Input Stuck High”, “Output Stuck Low”,
“Output Stuck High”, select the “Sample” radio button and enter “10”. This means that
you will select a random sample of 10% of the faults selected on the “Fault Selection
Tab”. Statistical fault simulation can be very accurate for a sample that is greater than
300 in a population of at least 3000 (this example is much smaller than that). Using a
0.1% sample for a 100,000 gate design (600 random faults out of 600,000 possible faults)
will reduce the fault simulation run time by a factor of 1000 (see “Statistical Fault
Simulation” on page 1-28).
Select the “Sample”
radio button and
enter “10” for a 10%
random sample of
faults.
•
The “Random Number Seed Value” is used to set the “seed” for the random number
generator so you get a different random sample each time you change the seed. To
generate a different random sample for the example, set the seed value to “1777777”
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Fault Sim Settings
(Fault Simulation Setup)
Next click on the “Fault Strobing Tab”:
•
This tab provides a short example of how to identify and strobe test nodes. The user
must specify the “$fs_strobe” system task before a fault simulation is run. For this
example, the existing source file “faulttst.v” contains the “$fs_strobe” system task for
specifying the test nodes. For more information, see “Specifying Test Nodes” on page 129.
Example for
specifying
test nodes.
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Fault Sim Settings
(Fault Simulation Setup)
Next click-on the “Distributed Process Selection Tab”:
•
This tab provides an interactive method for specifying additional processors necessary
for a distributed fault simulation. You can add processors for the distributed fault
simulation during the “Example For Distributed Fault Simulation” on page 3-34. For
more information, see “Distributed Fault Simulation” on page 1-39.
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Fault Sim Settings
(Fault Simulation Setup)
Next click-on the “Fault Sim Options” tab:
•
For the “Memory Usage Controls”, the “Max Memory” specifies the maximum memory
for the fault simulation. HyperFault will automatically calculate the number of
concurrent faults per pass, and HyperFault will suspend faults rather than swap to disk if
the specified memory limit is reached. The amount of memory you specify should not
exceed the available memory on the computer. Make sure you leave enough room in the
remaining RAM memory on your computer to allow for the operating system. For
Windows NT computers, the Max Memory box is automatically updated. To find the
maximum memory for Unix systems, see “Available Memory and CPU Speed for ” on
page 2-13. This example uses less then 12 megabytes of RAM memory, so you should
not have to change any of the default settings for the “Fault Sim Options” tab.
“Max Memory” is the RAM memory for your
computer. The fault simulation automatically
adjusts the faults per pass so it does not swap.
•
Click-on the “OK” button to close the “Fault Simulation Settings” dialog box. If you are
running the Demo Version, a message box may pop up asking you to enter an integer
between 1 and 20. This means that for the Demo Version, a maximum of 20 concurrent
faults is allowed, so enter “20” in the “Maximum Concurrent Faults” box.
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Running Fault Sim
3.4.2 Running Fault Simulation
Benefit
Clicking on the “Fault Sim Go” (“F”) button is all that is required to run fault simulation for
a design, making it simple to execute.
Procedure
“Fault Sim Go”
Button
Number of faults
after collapsing.
10% random
sample of faults.
Click-on the “Fault Sim Go” (“F”) button on the Toolbar to load the input files and run Fault
simulation.
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Fault Sim Status
(Running Fault Simulation)
Each pass ends when a $finish
is reached, or, all of the faults
for that pass are detected.
The % detect is based on the
faults that are already
simulated, so the value can
increase or decrease as fault
simulation progresses.
Click on the “Display percent”
radio button to display the
values as a percentage of the
total.
When fault simulation starts, the “Fault Simulation Status” dialog box automatically opens to
provide a summary of the fault simulation progress.
When the fault simulation is completed, the “Fault Simulation Status” dialog box shows the
percent of detected faults, and a table of the results that is listed by type of fault. You can
click on the “Display percent” radio button to display the type of fault detected as a
percentage of the total number of faults. The low Detection percentage (12%) obtained by
this run will be increased in the “Example for Incremental Fault Simulation” on page 3-28.
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Fault Report
3.4.3 Fault Report
Benefit
The fault report lists the name of each fault sorted by the type of detection. This report can
be useful when developing additional vectors to increase the fault coverage.
The histogram for the fault report lists the detections versus time. This can be useful for
eliminating redundant portions of your test vectors.
Procedure
Select the “Reports/Fault” menu selection to open the “Fault Report Options” dialog box.
For this example, check the “Detected Faults” check box, “Undetected Faults” check box,
and the “Histogram” check box, and uncheck the “Summary” check box. Then click-on the
“OK” button to generate the fault report.
Scroll down the fault report and notice that detected faults are listed with a
“%time%=value”. The undetected faults are simply listed by name without a
“%time%=value”.
Time value for output stuck at
high detections.
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Fault Report
(Fault Report)
•
At the bottom of the Fault report, the histogram shows that the faults were detected before
time=8000, so the test vectors after time=8000 were redundant.
Number of
detected faults .
Detected faults, “I”=input
fault, “O”=output fault.
Time axis.
This concludes the example on statistical fault simulation.
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Incremental Fault Simulation
3.5 Example for Incremental Fault Simulation
Benefit
Additional fault simulation test vectors can be used to run an incremental fault simulation.
The incremental fault simulation can be run on one or more fault detection types, which
decreases the fault simulation run time. This example will be run on only the undetected
faults to see if the new test vectors increase the fault detection. If the previous run used
statistical fault simulation, HyperFault will use the same random sample of faults for
incremental fault simulation so that the new results are consistent with the previous fault
simulation. There is no limit on the number of incremental fault simulations that can be run.
The cumulative fault simulation results are reported. This simplifies analysis of all the fault
simulation runs.
Procedure
See “Fault Simulation Setup for the HSE Examples” on page 3-5 for information on setting
up the fault simulation example if you have not already done this.
To set up incremental fault simulation, select the “Project/Fault Simulation Settings” menu
selection to open the “Fault Simulation Settings” dialog box.
Click-on the “Fault Sim Options” tab:
•
For the “Iteration Controls”, select the “Accumulate Detections” radio button. Next
check the “Undetected” check box. This will run fault simulation on only the undetected
faults from the previous fault simulation run. If any of these faults are detected, they will
be added to the total detection rate.
“Accumulate Detections” radio button.
“Undetected” faults check box.
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Incremental Fault Simulation
(Incremental Fault Simulation)
•
Click-on the “OK” button to close the “Fault Simulation Settings” dialog box.
•
In order to specify new stimulus, select the “Project/Project Settings” menu selection to open
the “Project Settings” dialog box.
•
Change the “Command Line Arguments” to “-f design2”, so that additional test vectors are
used for the incremental fault simulation.
Change the command line
argument to “-f design2”
•
Click-on the “OK” button to close the “Project Settings” dialog box. Answering “No” to the
message box for reloading the project (if it appears on your screen) will let you see the
message box again in the future.
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Incremental Fault Simulation
(Incremental Fault Simulation)
Click-on the “Fault Sim Go” (“F”) button on the Toolbar to load the input files and run Fault
simulation. You may need to move the “Fault Simulation Status” dialog box if it is open and
covering the Main Toolbar to see the “Fault Sim Go” (“F”) button.
When the fault simulation is completed, the “Fault Simulation Status” dialog box shows the
cumulative percent of the detected faults for the current run plus all previous runs. The table
of the “Fault Simulation Results” also shows the cumulative total for the current run plus all
previous runs listed by type of fault. You can click on the “This iteration only” radio button
to display the results for the current fault simulation.
Cumulative detection rate for
current fault simulation and
the previous fault simulation.
Click on the “This iteration
only” radio button to display
the results of the current fault
simulation.
This concludes the example on incremental fault simulation.
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Iterative Fault Simulation
3.6 Example for Iterative Fault Simulation
Benefit
Iterative fault simulation can be run on selected types of detected faults, such as the
hypertrophic faults, after the fault grading of all the sets of test vectors is completed.
Normally, the designer would use incremental fault simulation (see “Example for
Incremental Fault Simulation” on page 3-28) for accumulating the fault simulation results for
each set of test vectors or part of the design. For this example, the hypertrophic detected
faults are run to determine if they would have been hard detects. Running fault simulation on
the hypertrophic faults as one of the last steps for fault grading the test vectors saves time
because the designer can first test the remainder of the faults without having to wait for the
hypertrophic faults to be detected. Typically in large designs, relatively few hypertrophic
faults take much of the memory and run time. Also, the number of hypertrophic faults may
be so few as to not have a significant effect on the detection rate.
The cumulative fault simulation results are reported. This simplifies analysis of all the fault
simulation runs for the test vectors.
Procedure
See “Fault Simulation Setup for the HSE Examples” on page 3-5 for information on setting
up the fault simulation example if you have not already done this.
Select the “Project/Fault Simulation Settings” menu selection to open the “Fault Simulation
Settings” dialog box.
Click-on the “Fault Sim Options” tab:
“Replace Detections” radio button.
“Hypertrophic” faults check box.
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Iterative Fault Simulation
(Iterative Fault Simulation)
•
For the “Iteration Controls”, select the “Replace Detections” radio button. Next check
the “Hypertrophic” box, and uncheck the “Undetected” check box. This will run fault
simulation on only the hypertrophic faults from the previous fault simulation run. If any
of these faults are detected, they will be added to the total detection rate.
•
For the “HyperFault Controls”, set the “Hypertrophic Limit” to “100”. This turns off
hypertrophic faults, because a fault cannot exceed 100% of the design size and be
hypertrophic.
Set the “Hypertrophic Limit” to 100 to
turn off hypertrophic fault detection.
•
Click-on the “OK” button to close the “Fault Simulation Settings” dialog box.
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Iterative Fault Simulation
(Iterative Fault Simulation)
Click-on the “Fault Sim Go” (“F”) button on the Main Toolbar to load the input files and run
Fault simulation.
When the fault simulation is completed, the “Fault Simulation Status” dialog box shows the
percent of the cumulative detected faults for the current run and any previous runs. For this
example, most of the Hypertrophic faults are now hard detects.
Cumulative detection rate for
current fault simulation and
the previous fault simulations.
Three of the hypertrophic
faults from the previous run
are now hard detects, one is a
possible detect, and two are
undetected.
This concludes the example for iterative fault simulation.
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Distributed Fault Simulation
3.7 Example For Distributed Fault Simulation
Benefit
HyperFault has the ability to run a fault simulation on more than one CPU. This mode is
called distributed fault simulation. Distributing the faults to more than one CPU on the same
machine or across the network will reduce the execution time linearly by the number of
CPUs that are used.
Distributed fault simulation can be run with a random sample of the faults (statistical) to
reduce the run time. Distributed fault simulation can be run using an incremental fault
simulation or an iterative fault simulation. This can further reduce the run time for
distributed fault simulation.
Each computer can be set to its own memory limit. Since the computers on the network may
have different amounts of memory, each computer can use all of its available memory
without swapping.
The results are summarized and reported by the master machine. This simplifies analysis of
the results. Contact Simucad for benchmark results.
Procedure
See “Fault Simulation Setup for the HSE Examples” on page 3-5 for information on setting
up the fault simulation example if you have not already done this. Note, the Demo Version
of the HSE does not support distributed fault simulation.
Select the “Project/Fault Simulation Settings” menu selection to open the “Fault Simulation
Settings” dialog box.
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Distributed Fault Simulation
(Distributed Fault Simulation)
Click-on the “Fault Sim Options” tab:
•
Select the “Disable” radio button for the “Iteration Controls” so that distributed fault
simulation will be run on the entire fault sample. Set the “Hypertrophic Limit” to the
default value of “5” to enable the hypertrophic detection of faults.
“Disable” radio button.
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Distributed Fault Simulation
(Distributed Fault Simulation)
Click-on the “Distributed Process Selection” tab:
•
Check the “Use Distributed Fault Simulation” check box.
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Unix Distributed Fault Simulation
(Distributed Fault Simulation)
•
For distributed fault simulation for Unix:
•
Click-on the “Add New Computer” button to open the “Computer Settings” dialog
box. Specify the “Computer Name” for the slave computer (to find the computer
name for your computer, see “Hostid and Hostname for ” on page 2-13).
The “Max Memory” box specifies the maximum memory for the slave computer for
fault simulation. The “Max Memory” for the master computer is specified on the
“Fault Sim Options” tab. HyperFault can run multiple passes on each slave
computer. HyperFault automatically calculates the number of concurrent faults per
pass, and will suspend faults rather than swap to disk if the specified memory limit is
reached. The amount of memory you specify should be less than the maximum RAM
memory on your computer to allow room for the operating system (when using
multiple processors on the same computer as slaves, the available memory is the
RAM memory divided by the number of processors). To find the maximum memory
for Unix systems, see “Available Memory and CPU Speed for ” on page 2-13. This
example uses less then 12 megabytes of RAM memory, so any value greater than
12000000 will cause all of the faults to be run in one pass.
The “Process Weight” box specifies weighting used to calculate the faults for the
slave computer (see the “process_weight” option for “Fault Simulation Options
($fs_options system task)” on page 5-3) For this example, enter 1 to evenly divide
the faults between the master computer and slave computer.
The “Process Command” box specifies the location of the HyperFault executable
(“runfault” command file) on the slave computer.
“Process weight” allocates faults
between computers.
“Max Memory” prevents swapping to
disk.
Location of hyperfault executable.
• Click-on the “OK” button to close the “Computer Settings” dialog box.
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Distributed Fault Simulation
(Distributed Fault Simulation)
•
Click-on the “OK” button to close the “Fault Simulation Settings” dialog box.
Click-on the “Fault Sim Go” (“F”) button on the Toolbar to load the input files and run
distributed fault simulation.
When the distributed fault simulation is completed, the “Fault Simulation Status” dialog box
shows the percent of the cumulative detected faults for master and the slave runs.
If you have problems running the example for distributed fault simulation, see “Distributed
Fault Simulation on Unix” on page 2-12
This concludes the example on distributed fault simulation.
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Batch Runs
3.8 Example for Batch Fault Simulation
The below example sets up the fault simulation specifications so that they do not modify the test
bench or design (bold is required syntax, plain is optional syntax, italics is user specified). The
command files to run this example are automatically created when you run the “Example for
Statistical Fault Simulation” on page 3-17. The command line option to run this example is:
hyperflt -f faultsim.cfv
(for Windows NT)
runfault –f faultsim.cfv
(for Unix)
Diagram of the Files for the Batch Fault Simulation Example
Command and input files
created by Hyperfault
GUI
User command file
for design
stimulus.v
User file to
specify test nodes
($fs_strobe).
faultsim.cfv
design1
faultsim.mfv
design.v
design.lib
faulttst.v
User’s stimulus, design, and library.
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Batch Runs
(Example for Batch Fault Simulation)
Command File “faultsim.cfv” (generated by HSE)
// Simucad Generated Commands Start Here
-"!file .sav=faultsim"
// Renames the save file to the project name
// Simucad define
+define+hse
// Defines “hse” as true
-f design1
// Nested control file to input the
// user’s test bench, design, and libraries.
+typdelays
// Sets delay parsing for “typical” delays
-"!control .sav=3"
// Has no effect on fault simulation
-"!control .savcell=0"
// Has no effect on fault simulation
-"!control .disk=1000M"
// Has no effect on fault simulation
// Input Files
faulttst.v
// User file for specifying test nodes
faultsim.mfv
// File generated by HSE
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Batch Runs
(Example for Batch Fault Simulation)
Fault Simulation File “faultsim.mfv” (generated by HSE)
// Fault Simulation Controls
!fmon
!islow .pct=10.0
!ishigh .pct=10.0
!shigh .pct=10.0
!slow .pct=10.0
!fcon .fmem = 8000
!fcon .retryposs = 0
!fcon .tristate
// Command to specify the fault monitor.
// Commands to specify 10% random sample
// for output stuck at low and high faults
// and for input stuck at low and high faults.
!vreishigh stimulate\.dm\..*
!vreislow stimulate\.dm\..*
!vreshigh stimulate\.dm\..*
!vreslow stimulate\.dm\..*
// Commands to specify wild card
// fault selection for output stuck-at-low,
// output stuck-at-high, input stuck-at-low,
// and input stuck-at-high faults. The regular
// expressions select all the faults
// below instance stimulate.dm.
// Command to enable fault detection
// when a High-Z state is at a test node.
module fault_setup;
initial begin
$fs_dut ( stimulate.dm );
$fs_options( "max_memory = 200724480",
"process_weight = 1"
// Specify the device under test.
// Specify available memory
// Specify process weight for
// distributed fault simulation
);
end
endmodule
//Uncomment the below commands to store the activity report (comment out the !fsim command):
//!mkeep (stimulate(dm
// save results for block being faulted
//!control .savsim=1
// limit saved results to block specified by “!mkeep”
//!sim
// run logic simulation
//!disk activity.out
// name file to store activity report results
//!store activity
// write activity results to file “activity.out”
!fsim
!disk fault.out
!store fault/undet
Hyperfault User's Manual
// Command to run fault simulation.
// name file to store fault results
// write fault results to file fault.out
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Batch Runs
(Example for Batch Fault Simulation)
File “faulttst.v” (Created by user for strobing test nodes)
`timescale 1ns / 100 ps
module fault_strobe;
// declare delays as parameters for ease of modification.
parameter offset=50, wait_strobe=2;
// setup the strobe for the test nodes.
initial
// Specify a startup time of “offset” before strobing test nodes.
#offset
// After a negative clock edge occurs,
// strobe the test nodes after a wait time of “wait_strobe”.
forever @(negedge stimulate.clock)
#wait_strobe $fs_strobe( stimulate.vendcoke,
stimulate.vendpepsi, stimulate.vendsoft_drink );
endmodule
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Batch Runs
(Example for Batch Fault Simulation)
User’s Command File “design1” (Created by user for inputting the test bench and design)
stimulus.v
design.v
// File “stimulus.v” is the user’s test bench.
// File “design.v” is the user’s design.
-v design.lib
// The file “design.lib” is the library parts required for this example from Actel.
File “stimulus.v” (contains the drink machine test bench)
/*****************************
1998 Copyright Actel Corporation
*****************************/
`timescale 1ns / 1ns
module stimulate;
reg clock;
reg resetn;
reg [1:0] coin;
reg coke;
reg pepsi;
reg soft_drink;
wire vendcoke;
wire vendpepsi;
wire vendsoft_drink;
reg [96:1] info;
//instantiate the drink machine
drink_machine dm(.clock(clock), .resetn(resetn),.coin(coin),.coke(coke),
.pepsi(pepsi),.soft_drink(soft_drink),.vendcoke(vendcoke),
.vendpepsi(vendpepsi),.vendsoft_drink(vendsoft_drink));
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Batch Runs
(Example for Batch Fault Simulation)
(File “stimulus.v” (contains the drink machine test bench) )
//instantiate SDF file
initial
$sdf_annotate("design.sdf",stimulate.dm);
//display output
initial
begin
$display("\t\t\t\tTime Reset vendcoke
vendpepsi
vendsoft_drink\n");
$monitor("%d %d
%d
%d
%d", $time, resetn, vendcoke, vendpepsi,
vendsoft_drink);
end
//Stimulate the state machine
initial
begin
clock = 0;
coin = 0;
resetn = 0;
coke = 0;
pepsi = 0;
soft_drink = 0;
#50
resetn = 1;
@(negedge clock);
//Put in two dimes and a nickel and select a coke
#80 coke = 1;
#80 coin = 2;#40 coin = 0;
#80 coin = 2;#40 coin = 0;
#80 coin = 1;#40 coin = 0;
#80 coke = 0;
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Batch Runs
(Example for Batch Fault Simulation)
(File “stimulus.v” (contains the user’s test bench) )
//Put in one dime and three nickels and select a soft_drink
#80 soft_drink = 1;
#80 coin = 2;#40 coin = 0;
#80 coin = 1;#40 coin = 0;
#80 coin = 1;#40 coin = 0;
#80 coin = 1;#40 coin = 0;
#80 soft_drink=0;
//Put in one quarter and select a pepsi
#80 pepsi = 1;
#80 coin = 3;#40 coin = 0;
#80 pepsi=0;
//Put in three dimes and select a coke
#80 coke = 1;
#80 coin = 2;#40 coin = 0;
#80 coin = 2;#40 coin = 0;
#80 coin = 2;#40 coin = 0;
#80 coke=0;
#80
$finish;
end
//clock setup
always
begin
#20 clock = ~clock;
end
endmodule
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Batch Runs
(Example for Batch Fault Simulation)
File “design.v” (contains the drink machine design)
`timescale 1 ns/100 ps
module drink_machine(coin,clock,resetn,coke,pepsi,soft_drink,vendcoke,
vendpepsi,vendsoft_drink);
input [1:0] coin;
input clock, resetn, coke, pepsi, soft_drink;
output vendcoke, vendpepsi, vendsoft_drink;
wire present_stateZ0Z_0, present_stateZ0Z_1,
present_stateZ0Z_2, N_45, N_46, N_47, clock_y, resetn_y,
coin_y_0, coin_y_1, coke_y, pepsi_y, soft_drink_y, N_60,
N_38, N_49, N_55, N_67, N_35_i_0, G_30_1,
present_state_4_0_3_0, G_32_1, GNDZ0, VCCZ0,
present_state_4_0_1_n_2, N_62_n, N_55_n;
CM8 G_29_2(.D0(GNDZ0), .D1(coin_y_0), .D2(GNDZ0), .D3(GNDZ0),
.S00(resetn_y), .S01(VCCZ0), .S10(present_stateZ0Z_0),
.S11(present_stateZ0Z_1), .Y(N_49));
…
// the “…” denotes the remainder of the file
endmodule
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Batch Runs
(Example for Batch Fault Simulation)
File “design.lib” (contains selected parts from the Actel library for this example)
`celldefine
// Compiler directives to suppress faults
// and to enable the portfaults for subsequent
// source code read into HyperFault.
`suppress_faults
`enable_portfaults
`timescale 1 ns / 100 ps
module GND(Y);
output Y;
supply0 Y;
specify
specparam LibName = "act2";
specparam OutputLoad$Y = 0;
endspecify
endmodule
// Compiler directives to disable the portfaults
// and to no longer suppress fault selection
// for subsequent source code read into HyperFault.
`disable_portfaults
`nosuppress_faults
`endcelldefine
…
// the “…” denotes the remainder of the file
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4. Menus
4.1 Menus Overview
4.1.1 Pull-Down Menu Bar
The HyperFault Simulation Environment (HSE) provides the following top-level pull-down
menus:
File menu;
Edit menu;
View menu;
Project menu;
Fault Sim menu;
Logic Sim menu;
Explorer menu;
Reports menu;
Options menu;
Window menu;
Help menu.
The top-level pull-down menus for the HSE change depending on which window has the focus (the
window that is in focus has its title bar highlighted). For example, when the Data Analyzer
Window has the focus the available top-level pull-down menus are different from the Output
Window.
Many of the menu selections can be accessed by clicking-on buttons on the Toolbar. To see a label
for each button on the Toolbar, place the mouse cursor over the button for a few seconds and an
explanatory text message will appear.
4.1.2 Context Menus
Many of the windows in HyperFault have a context menus that can be accessed by putting the
mouse cursor in the window and then clicking on the right mouse button (for more information, see
“Context Menus” on page 4-59). For example, if you put the mouse cursor in the left-hand side of
the Explorer Window and click on the right mouse button, you will see the context menu for the
Explorer.
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Menus
4.1.3 Dialog Box Conventions
The following conventions should be noted for the dialog boxes:
Selecting the “OK” button will close the dialog box and any active options or specifications
will be used.
Selecting the “Cancel” button will close the dialog box and not affect any options or
specifications.
Selecting the “Close” button will close the dialog box, however, options selected for the
dialog box are not canceled.
Selecting the “STOP” button on the Toolbar or the Escape key (Esc) on the keyboard will
stop the current process, such as inputting a file or running logic simulation or fault
simulation. If HyperFault “hangs” during logic simulation and does not respond to the
“STOP” button, see “Nonconvergence (“Hanging”) for Behavioral Designs” on page 4-41.
For the command-line version (“hyperflt.exe” on the PC and “runfault” on Unix), pressing
the “Ctrl” and “c” keys on the keyboard will stop the current process.
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File Menu
4.2 File Menu
The “File” menu provides the following menu selections:
New menu selection;
Open menu selection;
Save menu selection;
Save As menu selection;
Print menu selection;
Print Setup selection;
Exit menu selection.
4.2.1 New
The “File/New” menu selection opens a new source window for editing.
4.2.2 Open Menu
The “File/Open” menu selection opens a source window for an existing file so that you can view or
edit the file. More that one source window can be open at the same time. Use the Window menu
to switch among the multiple open documents.
To simulate a project, use the “Project/New” menu to create a new project (see “New” on page 4-3
for the Project menu).
Shortcuts:
Toolbar button
Keys:
CTRL+O
4.2.3 Save
The “File/Save” menu selection saves the contents of the source file window that has the focus.
When you choose “Save”, the document remains open so you can continue working on it.
To save the results for logic simulation, see the “Save Project State Menu Selection” on page 4-14
in the Project menu.
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File / Print
4.2.4 Save As
The “File/Save As” menu selection allows you to specify a file name and then save the contents of
the source file window that has the focus.
When you choose “Save As”, the document remains open so you can continue working on it.
To save a project to a different project name, see the “Save As Menu Selection” on page 4-13 for
the Project menu.
4.2.5 Print menu
The “File/Print” menu selection uses a Windows common dialog box to print the Output Window,
the source windows and the report windows.
The Data Analyzer waveforms use the “Analyzer Print Options” dialog box for print.
Selecting this will print the time
values for the T1 and T2 timing
markers and the delta time.
The number of pages will
automatically adjust to the
print start and stop times.
The fonts for the Data Analyzer window can be modified by the “Options/Fonts” menu selection.
The “Analyzer Print Options” dialog box will print multiple pages of the waveform display. The
number of pages to be printed is specified in the pages box. When printing multiple pages, the
pages are automatically determined based on the Print Start and Print Stop times, and the number
of pages specified.
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File / Exit
4.2.6 Print Preview
The File/Print Preview menu selection displays a preview of the printout for the Output Window,
the source windows, and the report windows.
4.2.7 Print Setup
The “File/Print Setup” menu selection uses a Windows common dialog box to setup the printer for
the Output Window, the source windows, and the report windows.
4.2.8 Exit Menu
The “File/Exit” menu selection exits the HyperFault Simulation Environment. When the HSE is
exited the logic simulation history is lost unless the “Project/Save Project State” menu is selected
before exiting.
Shortcuts:
Mouse:
Keys:
Double-click the application's Control menu button.
ALT+F4
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Edit Menu
4.3 Edit Menu
The “Edit” menu provides the following menu selections:
Undo menu selection;
Cut menu selection;
Paste menu selection;
Clear menu selection;
Select All menu selection;
Find menu selection;
Find Next menu selection;
Replace menu selection;
Goto Line menu selection;
Delete menu selection;
Copy Image to Clipboard menu selection.
4.3.1 Undo menu selection
The “Edit/Undo” menu selection undoes your last editing or formatting action, including cut and
paste actions. If an action cannot be undone, Undo appears dimmed on the Edit menu.
4.3.2 Cut menu selection
The “Edit/Cut” menu selection deletes text from a document and places it onto the Clipboard,
replacing the previous Clipboard contents.
4.3.3 Copy menu selection
The “Edit/Copy” menu selection copies text from a document onto the Clipboard, leaving the
original intact and replacing the previous Clipboard contents. When the Data Analyzer window
has the focus, the “Edit/Copy” menu selection copies the full path for the selected signal name
from the Data Analyzer window to the Clipboard.
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Edit Menu
4.3.4 Paste menu selection
The “Edit/Paste” menu selection pastes a copy of the Clipboard contents at the insertion point, or
replaces selected text in a document.
4.3.5 Clear menu selection
The “Edit/Clear” menu selection deletes selected text from a document, but does not place the text
onto the Clipboard.
Use Clear when you want to delete text from the current document but you have text on the
Clipboard that you want to keep.
4.3.6 Select All menu selection
The “Edit/Select All” menu selection selects all the text in a document at once.
You can copy the selected text onto the Clipboard, delete it, or perform other editing actions.
4.3.7 Find menu selection
The “Edit/Find” menu selection searches for characters or words in a document.
You can match uppercase and lowercase letters and search forward or backward from the insertion
point.
4.3.8 Find Next menu selection
The “Edit/Find Next” menu selection repeats the last search without opening the Find dialog box.
4.3.9 Replace menu selection
The “Edit/Replace” menu selection replaces one string with another.
4.3.10 Goto Line menu selection
The “Edit/Goto Line” menu selection goes to the source line number that was specified.
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Edit Menu
4.3.11 Delete menu selection
When the Finite State Machine (FSM) window has the focus, the “Edit/Delete” menu selection will
delete the selected object or objects in the FSM window.
4.3.12 Copy Image to Clipboard menu selection
When the Finite State Machine (FSM) window has the focus, the “Edit/Copy Image to Clipboard”
selection will copy the current image on the screen for the Finite State Machine (FSM) window to
the Windows Clipboard.
When the Data Analyzer window has the focus, the “Edit/Copy Image to Clipboard” menu
selection copies the Data Analyzer window (signal names, scope, values, and waveforms) to the
Clipboard so it can be pasted into Microsoft Word.
Select the “Edit/Copy Analyzer Metafile” menu to copy the Data
Analyzer so it can be pasted into MS Word. You can use the
“Edit/Copy” menu, or “Ctrl-C” on the keyboard to copy the full
path for a text name.
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View Menu
4.4 View Menu
The “View” menu provides the following menu selections:
Zoom menu selections;
Toolbar menu selections;
Status Bar menu selection.
4.4.1 Zoom selections
The View menu has Zoom selections for the Data Analyzer Window. A check mark appears next
to the menu item that is used. These zoom selections are also buttons on the Toolbar.
4.4.1.1 Zoom-all menu selection
Zoom-all
- will display the entire logic simulation time range.
4.4.1.2 Zoom-out menu selection
Zoom-out
- zoom out by a factor of two.
4.4.1.3 Zoom-in menu selection
Zoom-in
- zoom in by a factor of two.
4.4.1.4 Zoom-markers menu selection
Zoom markers -will zoom-in-between the T1 and T2 timing markers if they are displayed.
4.4.2 Main Toolbar menu selections
A check mark appears next to the Main Toolbar when it is displayed.
Many of the selections for pulldown menus can also be accessed by clicking-on buttons on the
Main Toolbar. To obtain a text message of each button’s function, place the mouse cursor over the
button for a few seconds and an explanatory text message will appear.
The location of the Main Toolbar can be changed by using the mouse to grab an edge of either
toolbar and dragging the toolbar to the desired location.
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View Menu
4.4.3 Analyzer Toolbar menu selections
A check mark appears next to the Analyzer Toolbar when it is displayed.
Many of the selections for pulldown menus and context menus can also be accessed by clicking-on
buttons on the Analyzer Toolbar. To obtain a text message of each button’s function, place the
mouse cursor over the button for a few seconds and an explanatory text message will appear.
The location of the Analyzer Toolbar can be changed by using the mouse to grab an edge of either
toolbar and dragging the toolbar to the desired location.
4.4.4 Status Bar
The View/Status Bar menu selection displays or hides the Status Bar at the bottom of the HSE.
The left area of the Status Bar describes actions of menu items as you use the arrow keys to
navigate through menus. This area similarly shows messages that describe the actions of toolbar
buttons as you depress them, before releasing them. If you wish not to execute the toolbar button
after viewing the description of the toolbar button, then release the mouse button while the pointer
is off the toolbar button.
The right area of the Status Bar displays the time values for the T1, T2, the delta time, and the
current time. The farthest right area of the status bar displays which of the following keys are
latched down:
Indicator
Description
CAP
The Caps Lock key is latched down.
NUM
The Num Lock key is latched down.
SCRL
The Scroll Lock key is latched down.
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Project Menu
4.5 Project Menu
The “Project” menu provides the following menu selections:
New menu selection;
Open menu selection;
Files menu selection;
Save As menu selection;
Close menu selection;
Save Project State;
Restore Project State;
Project Settings menu selection;
Fault Simulation Settings menu selection;
Filters
Load/Reload Input Files menu selection;
Reload and Go menu selection.
4.5.1 New Menu Selection
The “Project/New” menu selection opens the “Create New Project” dialog box. The “Create New
Project” dialog box enables you to specify the name and working directory for a new project.
Projects provide a useful method for organizing your source files, as the files and libraries for the
project may be scattered across many directories.
The new project name can be typed into the “File Name” box. The HSE will automatically
append the suffix “.spj” to the project name if you do not add a suffix to the project name. Click
on “Save” to create the project name and exit the dialog box. Click-on “Cancel” to exit the dialog
box without creating a project name.
After selecting the “Save” button, the “Project Files” dialog box is automatically opened. The
“Project Files” dialog box enables you to specify all the source files, library files, and PLI library
files associated with a project.
To create a new project that is similar to an existing project, you may want to use the “Project/Save
As” menu selection (see “Save As Menu Selection” on page 4-13).
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Project Menu
4.5.2 Open Menu Selection
The “Project/Open” menu selection opens the “Open Project” dialog box to specify the name for
opening an existing project. Click on the “Open” button to open the project. Click on the “Cancel”
to exit the menu. Before opening a project, the HSE is automatically reset so that the results from
any previous project are lost.
4.5.3 Files Menu Selection
The “Project/Files” menu selection opens the “Project Files” dialog box for specifying the input
files and library files for a project. To select a project for the “Project Files” dialog box use the
Project/New or Project/Open menu selections.
The “File Group” list box allows you to select Verilog HDL “Source Files”, “Library Files”, and
“PLI Library Files”. To add source files, have the Source Files option selected in the File Group
box. Next double-click on a file name in the list box, or highlight a file name in the list box and
click on the Add button to add the source file to the “Files in Group” list box. Files can be deleted
from the project by highlighting the file name in the “Files in Group” box and selecting the
“Remove” button. The “Move Up” and “Move Down” buttons allow you to rearrange the file
names in the “Files in Group” list box. Click on “Ok” to update the project and close the dialog
box and “Cancel” to exit the dialog box without affecting the project.
To specify library files, click-on the drop-down arrow in File Group list box in the Project Files
dialog box, and select “Library Files”. Double-click on library file names in the list box to add
them to the “Files in Group” list box. You can also select more than one library file by clicking on
a file name to highlight it, and then hold down the “Shift” key or the “Ctrl” key on the keyboard
while clicking on additional file names. To specify a directory of library files whose file name
extensions end in “.v”, enter the directory name followed by “{.v}" in the “File Name” box, and
click-on the Add button. An example for specifying all the files ending with “.v” for directory
“library” would be “library{.v}”. For more information on specifying library files, see the “-y”
and “-v” “Command-line Options” on page 8-4.
To specify PLI library files, click-on the drop-down arrow in File Group list box in the Project
Files dialog box, and select “PLI Library Files”. Double-click on PLI library file names in the list
box to add them to the “Files in Group” list box as PLI library file names.
To actually input the files for a project, use the “Project /Load/Reload Input Files” menu selection
or the “Load/Reload Input Files” button on the Toolbar.
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Project Menu
(Files Menu Selection)
HyperFault projects also allow relative paths to files so that the path names in a project will work at
different sites. To specify this, you need to specify a `define compiler directive in the
Project/Project Settings dialog box, such as "foo=c:\hyperfault\examples". Then edit the project
file (.spj file) and put the `define compiler directive before the path names, such as:
[Files]
0=`foo\vendtest.v
1=`foo\vend.v
HyperFault now preprocesses the information in the project file (.spj file), and substitutes the string
"c:\hyperfault\examples" for `foo. This feature will work for path names that are set in the Project
Files dialog box, such as the Source Files, Library Files, Include Directories, and PLI Library Files.
This also works with path names that are set from the Project Settings dialog box, such as
Command Line Arguments, Simulation Data File Path, and the plusargs settings.
4.5.4 Save As Menu Selection
The “Project/Save As” menu selection saves the project to the project name that you specify. It
does not save the logic simulation history for the Data Analyzer (see “Save Project State Menu
Selection” on page 4-14). The Save As feature can be used to easily clone projects for testing
purposes without having to modify the original project.
4.5.5 Close Menu Selection
The “Project/Close” menu selection closes a project. All “child” processes such as the Output
Window and the Data Analyzer Window are also closed.
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Project Menu
4.5.6 Save Project State Menu Selection
The “Project/Save Project State” menu selection saves the logic simulation results and the current
state of the logic simulator to disk. This feature is very useful for preventing logic simulation data
loss so that you do not have to re-simulate your design if you exit HyperFault or if HyperFault
crashes. The Project/Save Project State menu can be selected at any time after logic simulation has
halted. This feature can not be used for fault simulation.
When HyperFault is restarted, the Project/Restore Project State menu selection can be used to
reload the logic simulation up to the last time point that was saved. The Data Analyzer can then be
used to view the logic simulation results and the simulation can be continued. The Project/Restore
Project State menu must be selected immediately after HyperFault is reopened or a project is
opened. The Project/Restore Project State menu can not be selected after selecting the
Project/Load/Reload Input Files menu or the “Go” button.
The logic simulation history is stored on disk in the file named “project_name.sim”, and the
simulation state is stored on disk in the file named “project_name.cmm”. The
“project_name.cmm” file will be slightly larger than the size of you HyperFault logic simulation in
RAM memory.
4.5.7 Restore Project State Menu Selection
When HyperFault is restarted, the Project/Restore Project State menu selection can be used to
reload the logic simulation up to the last time point that was saved by the “Project/Save Project
State” menu selection. The Data Analyzer can then be used to view the logic simulation results
and the logic simulation can be continued. The Project/Restore Project State menu must be
selected immediately after HyperFault is reopened or a project is opened. The Project/Restore
Project State menu can not be selected after selecting the Project/Load/Reload Input Files menu or
the “Go” button. This feature can not be used for fault simulation.
The logic simulation history is stored on disk in the file named “project_name.sim”, and the logic
simulation state is stored on disk in the file named “project_name.cmm”. The
“project_name.cmm” file will be slightly larger than the size of you HyperFault simulation in
RAM memory.
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Project Menu
4.5.8 Project Settings Menu Selection
The “Project/Project Settings” menu selection allows you to set the command-line options and
other options for HyperFault. you must click on the Load/Reload Input Files button, or select the
Project/Load/Reload Input Files menu selection.
Available options for the Project Settings dialog box are:
Analyzer Symbol Table File: This specifies a file that substitutes text strings for state values
for vectors displayed in the Data Analyzer for logic simulation. The text strings can be
symbols for a state machine, making the state machine much easier to debug. For an
example, see “Displaying Vectors using Symbolic Names” in the on-line help for the
HyperFault User’s Manual.
Auto File Save: Enabling this feature will cause HyperFault to automatically save any
source file you have modified whenever you click on the Load/Reload Input Files button on
the Main toolbar, or select the Project/Load/Reload Input Files menu selection.
Command Line Arguments: You can use Verilog style command line arguments for
HyperFault. The command line arguments can be entered from the Command Line
Arguments box in the Project Settings dialog box, or, from the command line if you are
running a batch simulation. For a list of the available command line arguments, see
“Command-line Options” on page 8-4. The command line arguments can make use of
relative names (see “Files Menu Selection” on page 4-12).
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Project Menu
(Project Settings)
`define’s: The user can enter `define statements that are project specific. These `define
compiler directives will be used in addition to any `define compiler directives in the design.
When entering the `define, use just the <text_macro_name> <MACRO_TEXT> part of the
`define syntax. For example, for the Verilog compiler directive:
`define wordsize 8
you would enter in the Project Settings dialog box:
wordsize 8
HyperFault allows relative paths to files so that the path names in a project will work at
different sites. To specify this, you need to specify a `define compiler directive in the
Project/Project Settings dialog box, such as "foo=c:\hyperfault\examples". Then edit the
project file (.spj file) and put the `define compiler directive before the path names, such as:
[Files]
0=`foo\vendtest.v
1=`foo\vend.v
HyperFault preprocesses the information in the project file (.spj file), and substitutes the
string "c:\hyperfault\examples" for `foo. This feature will work for path names that are set in
the Project Files dialog box, such as the Source Files, Library Files, Include Directories, and
PLI Library Files. This also works with path names that are set from the Project Settings
dialog box, such as Command Line Arguments, Simulation Data File Path, and the plusargs
settings.
Delay Selection: You can select the “min/typ/max” delay setting for all delays in the project.
Disable cache: This feature disables the caching to RAM memory for the part of the
simulation history save file that is used to draw the waveforms in the Data Analyzer. For
example, if you do a Zoom Full in the Data Analyzer, the simulation information for the
signals currently displayed is saved in RAM memory in a format that is faster to access. If
you then zoom in, the information is taken from RAM memory instead of disk, and the Data
Analyzer is updated much faster. However, if your computer does not have enough RAM
memory, you may choose to disable this feature.
Disable floating node warnings: This feature disables the warning message that informs the
user that a wire is not driven by anything, i.e. a floating node.
Enable Silos extensions: This feature enables extensions to the Verilog HDL language, such
as assigning to wires in procedural code and global variables (see “HyperFault Extensions to
Verilog HDL” on page 7-20).
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Enable log file: This feature causes standard output to be written to a log file when the HSE
program is exited. The default log file name is the project name with the “.log” file
extension. When this option is selected the HSE will write to both standard output and the
log file.
Functional simulation: This feature reduces the memory used and increases simulation speed
by eliminating the specify blocks from logic simulation and fault simulation. To prevent
nonconvergence problems, the unit delay mode is used for all modules.
•
Maximum File Size: You can select one of two options to control the maximum simulation
save file size on disk, the “Size In Bytes” or the “Recirculate Start Time”.
•
The “Size In Bytes” option sets the maximum size on disk for the simulation history save
file. This prevents HyperFault from crashing when all available disk space is used.
HyperFault will return to the “Ready:” prompt when the simulation history save file reaches
the limit. The “reset savfile” command can be entered in the Command window in the Main
Toolbar to reset the simulation history save file to a few bytes. The simulation can be
continued and the simulation results that are after the “reset savfile” can be reviewed.
•
The “Recirculate Start Time” option specifies the maximum time interval for saving the
simulation history results. When the simulation time exceeds this interval, the new
simulation results are saved and the earliest simulation results are discarded so that the save
file interval and file size on disk stay relatively constant, very much like a FIFO. The
interval can be specified in time units, such as “100ns” for 100 nanoseconds.
plusargs: You can enter “+” command-line arguments that are project specific, such
“+compare”, “+sdf”, .etc. For example, suppose you wanted to specify the SDF file only if
you entered “+sdf” in the “plusargs” box for the Project Settings dialog box. Then your test
bench may look like:
module test_bench;
initial
if ( $test$plusargs( “sdf”))
$sdf_annotate(“test.sdf”);
endmodule
// only execute if “+sdf” is an argument
The plusargs arguments can make use of relative names (see “Files Menu Selection” on page
4-12).
Retain simulation data file: This prevents the simulation history save file for logic
simulation from being deleted from disk when the HSE is exited. The default is to delete the
simulation history file when the HSE is exited. Checking this option is not recommended, as
it has no use and may clutter up your disk with large save files. This setting is for logic
simulation only and has no effect on fault simulation.
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Project Menu
(Project Settings Menu Selection)
Save all sim data: This feature will save the logic simulation history for every variable. If
“Save all sim data” is not enabled, then the only variables saved are those specified on each
instance in the hierarchy by the Properties menu selection in the Explorer context menu.
This setting is for logic simulation only and has no effect on fault simulation.
Simulation Data File Path: This specifies the directory where the simulation history file is
stored. This enables you to use disk drives with more space or that are more convenient.
The simulation data file path can make use of relative path names so that projects are
independent of the file systems they are run on (see “Files Menu Selection” on page 4-12).
Save `celldefine data: This feature determines if variables in `celldefine - `endcelldefine
boundaries are saved during logic simulation. This feature is useful for excluding variables
that are inside of library cells from the save file, thus reducing the size of the save file on
disk. When using the Data Analyzer, if you see “No Saved Data” instead of a waveform, this
may mean that the signal is inside of a `celldefine boundary. To correct this, enable the
"Save `celldefine data" option and re-simulate. This setting is for logic simulation only and
has no effect on fault simulation.
Tabs: This feature will set the spacing for tabs in the source file windows. This can be
useful for customizing the tab spacing.
Use Alternate Behavioral Evaluation Order: This instructs the simulator to evaluate selected
behavioral code in a similar order of execution as used by other Verilog HDL simulators for
logic simulation or for fault simulation.
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Project Menu
4.5.9 Fault Simulation Settings Menu Selection
The “Project/Fault Simulation Settings” menu selection opens the “Fault Simulation Settings”
dialog box. This dialog box allows you to set the options for HyperFault.
When the “Ok” button is selected, the dialog box is closed and the information for fault simulation
is written to two ASCII files, “project_name.mfv” and “project_name.cfv”, where “project_name”
is the name of the current project. If you want to setup a batch run, you can enter “hyperflt –f
project_name.cfv” at the DOS window command prompt.
When the “Cancel” button is selected, the dialog box is closed and the “project_name.mfv” and
“project_name.cfv” files are not updated.
The "Apply" button is active any time you change an item for the “Fault Simulation Settings”
dialog box. Clicking on "Apply" will save these changes to “project_name.mfv”
“project_name.cfv” files without closing the dialog box.
Available options for the Project Settings dialog box are:
4.5.9.1 Fault Selection Tab:
This tab specifies which parts of the design to select the faults from. The tab has the following
selection items :
•
Device Under Test: The user must type in the full hierarchical path name for the Device
Under Test (DUT). For more information, see “Device Under Test (DUT)” on page 115.
•
Selected Faults: The “Select all possible faults” feature will select every possible fault
in the DUT.
If the “Select all possible faults” feature is unchecked) then the faults from a particular
block in the design can be selected by the Regular Expressions and / or from a Fault List
File.
Block selection is useful when doing a mixed RTL/Gate level design, or when
incrementally using patterns that only apply to one block of the design.
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Project Menu
(Fault Simulation Settings Menu Selection)
For most applications, applying faults to a specific block in the hierarchy is very simple.
Just put in the hierarchical name for the block that you want to apply the faults. Then
escape the periods in the hierarchical name with a backslash because period is a reserved
character for regular expressions. Next add “\..*” at the end of the hierarchical name to
select every name below it in the hierarchy. For example, if the hierarchical name was
“stimulate.dm”, then the regular expression to select every name below “stimulate.dm” in
the hierarchy would be “stimulate\.dm\..*”. If you want to “or” regular expressions
together, simply use a space to separate each regular expression that you wish to “or” (the
“||” and “&&” operators are not supported by regular expressions. For more information
on specifying faults using regular expressions, see “Selecting Faults by Wildcards” on
page 1-18, “Excluding Faults by Wildcards” on page 1-22, and “Regular Expressions” on
page 1-24.
The Fault List File is a file that can be produced by the fault report. For more
information on specifying faults using regular expressions, see “Selecting Faults By
Name” on page 1-19 and “Excluding Faults By Name” on page 1-23.
•
Excluded faults: The Regular Expressions can be used to define the scope for excluding
faults. This can be useful for excluding part of the circuit, such as excluding a block of
circuitry that is inside of a selected block of circuitry. For more information on
excluding faults, see “Excluding Faults” on page 1-21.
4.5.9.2 Fault Sampling Tab:
This tab allows you to sample the faults you selected in the “Fault Selection” tab. You can
specify a statistical percent for the type of stuck-at faults, “Input Stuck Low” faults, “Input Stuck
High” faults, “Output Stuck Low” faults, and “Output Stuck High” faults, or simply select all of
the faults. For more information on specifying statistical percentages, see “Statistical Fault
Simulation” on page 1-28. Varying the value for the “Random Number Seed Value” changes the
faults selected for a statistical sample. This is useful for checking the results of a statistical fault
simulation by running another statistical fault simulation that samples different random faults.
4.5.9.3 Fault Strobing Tab:
This tab is a reminder note to include the test nodes for fault simulation. For more information
on specifying the test nodes, see “Specifying Test Nodes” on page 1-29. We recommend that a
separate module and file contain the $fs_strobe so that it is separate from the design.
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(Fault Simulation Settings Menu Selection)
4.5.9.4 Distributed Process Selection Tab:
This tab is used to specify the slave computers for distributed fault simulation. Checking the
“Use distributed fault simulation” check box un-grays the following items:
•
The “Master Process Weight” specifies the percentage of the total fault set to be given to
the master process.
•
The “Add New Computer” button opens the “Computer Settings” dialog box. For the
“Computer Name:” box, enter the host name for the slave computer. On Unix, you can
find the host name by entering “hostname” at the Unix prompt on the appropriate slave
computer. On NT 4.0, you can find the host name by selecting Start/Control Panel/
Network tab to open the Network dialog box, and using the “Computer Name” for the
appropriate slave computer.
For the “Max Memory” box, enter the maximum available memory for the slave
computer. You can find out the maximum memory on Solaris by entering “dmesg” at the
Unix prompt. You can find out the maximum memory on NT by selecting the
Start/Control Panel/ System tab to open the System Properties dialog box, and reading
the RAM memory on the General tab.
Note: If you are on a multi-processor computer, the amount of available memory is not
the RAM installed on the machine, instead it is the amount of RAM installed divided by
the number of processors you are using. You should also allow as much as 10% of the
installed RAM for other processes, such as the operating system.
For the “Process Weight” box, this option specifies a percentage of the total fault set
given to a slave process. This option is required for each slave process. The fault
partitioning algorithm is:
f = (F) ( n / N)
where "f" is the number of faults assigned to a process, "n" is the process weight, "N" is
the sum of all the process weights, and "F" is the total number of faults.
For the “Process Command” box, on Unix this option specifies the location of the
“runfault” script, and on Windows NT this option specifies the location of the “hyperflt”
executable.
For the “Windows NT Net Use Command” box (Windows NT only), this option specifies
the "nt_net_use” option for the $fs_options system task that is necessary to establish the
link between the slave drive and the master drive on Windows NT (for more information,
see “Fault Simulation Options ($fs_options system task)” on page 5-3).
For the “Silos license file path for this computer:” box (Windows NT only), this option
specifies path to the license file for running HyperFault on the slave computer.
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The “Use this computer for distributed fault simulation” check box lets you “Enable” a
computer for distributed fault simulation. Double-clicking on the “Computer Name”
after it has been entered will toggle the “Enable” selection. A “Y” in the Enable column
indicates that a computer will be used for distributed fault simulation. A “N” in the
Enable column indicates that a computer will not be used for distributed fault simulation.
•
The “Edit Computer Settings” button edits an existing entry for distributed fault
simulation.
•
The “Remove Computer” button will remove a computer from distributed fault
simulation.
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4.5.9.5 Fault Sim Options tab:
This tab specifies many of the options available for fault simulation:
•
“Memory Usage Controls”:
The “Max Memory” box specifies the amount of available RAM memory in bytes. This
prevents the fault simulation from swapping to disk, which would drastically increase the
run time. The fault simulator will attempt to keep the process size within the amount of
memory specified. It will accomplish this by adjusting the number of concurrent faults
per pass, both at the beginning of a pass and during the simulation of the pass itself.
Faults that are suspended during a pass will be rerun at the end of the fault simulation.
Note: If you are on a multi-processor computer and if you are doing distributed fault
simulation, the amount of available memory is not the RAM installed on the machine,
instead it is the amount of RAM installed divided by the number of processors you are
using for distributed fault simulation. You should also allow as much as 10% of the
installed RAM for other processes, such as the operating system.
The “Maximum Concurrent Faults” box specifies the maximum number of current faults
per pass. Because the number of concurrent fault per pass is automatically calculated for
the “Max Memory” limit, there is no advantage in using this parameter.
•
“Detection Controls”:
The “Hypertrophic Limit” box specifies an early detection method where the fault is
considered detected if its effect propagates to a percentage of the design. These faults are
declared as a hypertrophic detected and dropped. For most fault simulations, relatively
few faults cause most of the memory usage and the run time. Typically these are
hypertrophic faults. By considering these faults as detected and dropping them early in
the fault simulation run, the advantage is to reduce the fault simulation run time and
memory usage. For more information, see “Hypertrophic Faults” on page 1-36.
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The “Number of soft detects to record a possible detect:” box assigns the threshold value
for reporting possible detects. A “soft” detect occurs at each strobe time that the test
node for the faulted circuit is an unknown level, and the level for the same test node in
the good circuit is low or high, and only if the test node in the faulted circuit has wiggled
(been at low or high) since the last strobe time. The soft detect count for a fault is
incremented a maximum of 1 at each strobe time, regardless of the number of test nodes
that satisfy this criteria during strobing. When the number of soft detects equals the
threshold limit, the fault is considered a possible detect and dropped. Setting the value to
zero will turn off possible detect and soft reporting. For more information, see “Hard,
Possible, and Soft Detected Faults” on page 1-34.
Soft detect counts are brought forward from prior runs when the “Carry Soft Count
Forward” box is checked (default). Un-checking the box means soft counts do not
contribute to the current fault simulation run. For more information, see “Hard, Possible,
and Soft Detected Faults” on page 1-34.
The “Drop Possible Detects” check box allows possible detects to remain active to give
them the opportunity to become a Hard detect for the current fault simulation run. When
the box is unchecked (default), a fault which becomes a possible detect will be dropped
from further processing. For more information, see “Hard, Possible, and Soft Detected
Faults” on page 1-34.
The “Detect Mismatched 1/0 <-> Z (Tristate)” check box enables fault detection when
either the faulted circuit test node or the reference circuit test node is High-Z, and its
comparison test node is a high or a low level. When the box is unchecked, a High-Z state
at a test node is considered undetected. For more information, see “Tri-state Detection”
on page 1-37.
•
“Fault Sim Schedule”
When the “Enable” check box is checked, the “Edit Schedule” button is active. Clicking
on the Edit Schedule button opens the “Fault Sim Schedule” dialog box, which allows
you to specify automatic shutdown and optional restart. This is useful for setting up fault
simulations that can be run consecutive nights. If you check the “Enable Restart” box in
the “Fault Sim Schedule” dialog box, you can enter a restart command in the “Restart
Command” box. For more information on restart commands, see the “quit” parameter for
the !fsim command in “Fault Simulation Specification” on page 6-23.
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•
“Crash Recovery Controls”
When the “Enable” box is checked for the “Crash Recovery Controls”, the user can
specify the interval for writing to the fault dictionary file. If the fault simulation crashes,
the fault simulation can be recovered to the last time that the fault dictionary file was
written.
•
“Iteration Controls”
The “Iteration Controls” can be used to incrementally accumulate the fault simulation
results across fault simulation runs, or to replace the faults results with the results of the
most recent run.
The “Disable” radio button will prevent previous fault simulation runs from affecting the
current fault simulation run. The fault simulation results from the current run are then
saved in the fault dictionary file for a subsequent fault simulation.
The fault simulation results from the previous run can be accumulated into the current
run by selecting the “Accumulate Detections” radio button. The fault simulation results
from the current run are then saved in the fault dictionary file for a subsequent fault
simulation. This is useful for testing new patterns, or for applying faults to a new block
of the design. For more information, see the “!fsim/iterate” command for the “Fault
Simulation Specification” on page 6-23.
The “Replace Detections” radio button will replace the faults results with the results of
the most recent run. This is useful for further qualifying faults when the detection criteria
is changed. For example, the “Hypertrophic Limit” could be changed to 100% to see if
the hypertrophic faults become detected, undetected, or possible detects. For more
information, see the “!fsim/same-pattern-iterate” command for the “Fault Simulation
Specification” on page 6-23.
•
“Detection Types”
When “Accumulate Detections” or “Replace Detections” is selected, the “Detection
Types” will iterate only the faults of the detection types selected. This reduces the run
time of the fault simulation. For more information on detection types, see “Fault
Detections” on page 1-33.
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•
“Other Controls”
The “Inject Faults at Simulation Time” box specifies the time that faults will be injected.
Units can specified for the time value, such as “10ns” specifies ten nanoseconds. Time
dependent fault injection provides the capability of injecting faults after initialization, or
before the first test vector. When a test is built for a certain area of the chip, the test often
contains initialization vectors necessary to activate the area of the chip under test.
Injecting the faults prior to the initialization may have multiple bad effects:
•
•
The potential for slowing the fault simulation during the initialization.
The potential for false detections during the initialization. Such as, the initialization
period in the test vectors could have a power-up sequence, which could cause faults
to be detected during initialization of the power-up instead of when simulating the
chip itself.
4.5.10 Filters
The “Project/Filters” menu selection opens the “File Filters” dialog box for specifying file name
filters for the “Project Files” dialog box (Project/Files menu selection). If you specify a file filter,
then the default filters are hidden for the “Project Files” dialog box.
The name filtering for the “Project Files” dialog box uses the standard Windows style wildcard
characters for file name expansion:
•
The asterisk character “ * ” is used to match any pattern, including null.
•
The question mark character “ ? ” is used to match any single character.
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4.5.11 Load/Reload Input Files Menu Selection
The “Project/Load/Reload Input Files” menu selection automatically resets HyperFault and inputs
the files specified for the project that is open.
Logic simulation is then run to time=0 and you can begin debugging your project by setting
breakpoints, single stepping, etc. The Data Analyzer can be opened to display the results during
simulation. Choosing the “Go” button on the Toolbar will run logic simulation until a “$stop” or
“$finish” is encountered in the design, or until you choose the “STOP” button on the Toolbar.
4.5.12 Reload and Go Menu Selection
The “Project/Reload and Go” menu selection automatically resets HyperFault, inputs the files
specified for the project, and then runs logic simulation until a $stop or a $finish system task is
encountered, or until you choose the “STOP” button on the Toolbar.
4.5.13 Filters
The Project/Filters menu selection opens the “Recent Project List” dialog box for specifying file
name filters for the “Project Files” dialog box (Project/Files menu selection). If you specify a file
filter, then the default filters are hidden for the “Project Files” dialog box.
The name filtering for the “Project Files” dialog box uses the standard Windows style wildcard
characters for file name expansion:
•
The asterisk character “ * ” is used to match any pattern, including null.
•
The question mark character “ ? ” is used to match any single character.
4.5.14 Project List Size
•
The Project/Project List Size menu selection opens the “File Filters” dialog box for specifying
the number of recently used projects that are listed at the end of the Projects menu.
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Fault Sim Menu
4.6 Fault Sim Menu
The “Fault Sim” menu provides the following menu selections:
Start Fault Sim menu selection;
Stop Fault Sim menu selection;
Show Fault Sim Status menu selection.
4.6.1 Start Fault Sim Menu Selection
The “Fault Sim/Start Fault Sim” menu selection starts the fault simulation. The “F4” key on the
keyboard or the “Fault Sim Go” button on the Main toolbar will also start the fault simulation.
4.6.2 Stop Fault Sim Menu Selection
The “Fault Sim/Stop Fault Sim” menu selection stops the fault simulation. The “Esc” key on the
keyboard will also stop the fault simulation.
4.6.3 Show Fault Sim Status Menu Selection
The “Fault Sim/Show Fault Sim Status” menu selection will open the Fault Simulation Status
dialog box when the fault simulation starts. Holding down and releasing the shift key and the “F4”
key on the keyboard will also open the Fault Simulation Status dialog box.
The Fault Simulation Status dialog box provides a summary of the fault simulation progress. The
Elapsed Time (cpu seconds) is computed from the time the fault sim button is pushed, and it
includes the preprocessing and setup times as well as the simulation time.
The radio buttons at the bottom of the dialog box can display the actual counts or the percentages.
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Fault Sim Menu
(Show Fault Sim Status Menu Selection)
Elapsed time days:hours:minutes
in wall time
Number of passes and
faults per pass
Useful after incremental or
iterative fault simulation
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4.7 Logic Sim Menu
The “Logic Sim” menu provides the following menu selections:
Go menu selection;
Break Simulation menu selection;
Finish Current Timepoint menu selection;
Step menu selection;
Breakpoints menu selection.
4.7.1 Go Menu Selection
The “Logic Sim/Go” menu selection performs logic simulation. The “Go” button is also available
on the Toolbar.
When “Go” is selected the files specified for the project are automatically input into HyperFault
(unless they have already been input). Logic simulation is then run until a “$stop” or “$finish” is
encountered in the design. During simulation, the “Go” button will change into a “Stop” button
which can be clicked on to halt the simulation at any time.
The “Go” button can be useful during single stepping to skip across uninteresting source code to
the next breakpoint, at which point the single stepping can be resumed.
4.7.1.1 Simulation Suggestions
Libraries
To increase the speed of processing your design for logic simulation or for fault simulation, use the
library feature to specify large library files from vendors. Any file of Verilog source code can be
specified as a library file. To specify library files, see the “Files Menu Selection” on page 4-12.
Library files can also be specified from the command line, see “Command-line Options” on page
8-4.
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Simulation
Simulation Save File Size
HyperFault is very efficient in saving the logic simulation results to disk. In general, there is only
a 10% to 15% difference in speed between the saving every variable in the hierarchy and saving
nothing. However, if the save file on disk becomes large enough (over a few hundred megabytes)
then the time spent writing to disk may be significant. The save feature is disabled for fault
simulation.
To reduce logic simulation save file size on disk, you can select which parts of the hierarchy that
you want to save the logic simulation results for. To specify which instances to save information
for during logic simulation, select the “Properties” menu selection in the context menu for the lefthand side of the Explorer Window (see “Properties” on page 4-62).
Restarting Logic Simulation
HyperFault has the ability to restart the logic simulation from any time point by using the save and
restore feature (see “Save Project State Menu Selection” on page 4-14). Using this feature
eliminates the time required to re-input and re-simulate the design. A debugging strategy may be
to simulate to a time point, and then use the Project/Save Project State menu to save the state of the
logic simulation. You can then set variables to a value and continue logic simulation. To restart
the logic simulation, exit HyperFault, then restart HyperFault, and select the Project/Restore
Project State menu to return the logic simulation to the time point the logic simulation was saved
at.
To restart the logic simulation from time=0, you do not need to exit HyperFault. Instead, click on
the “Load/Reload Input Files” button on the Main Toolbar.
Loss of Logic Simulation Data
To prevent the loss of the logic simulation results due to unexpected interruptions, you can save the
state of HyperFault after logic simulation. When logic simulation has completed, save the
simulation results by selecting the “Project/Save Project State” menu. Then open the Data
Analyzer, review your simulation results, and debug your design. If you need to re-enter
HyperFault, you can select the “Project/Restore Project State” menu, open the Data Analyzer and
view the waveforms without re-simulating. To prevent the loss of data during fault simulation, see
“Crash Recovery Controls” for “Fault Sim Options tab:” on page 4-23.
4.7.2 Break Simulation Menu Selection
The “Logic Sim/Break Simulation” menu selection will stop HyperFault from simulating logic
simulation. The Escape key (“Esc”) on the keyboard or the “STOP” button on the Toolbar
performs the same function.
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4.7.3 Finish Current Timepoint Menu Selection
The “Logic Sim/Finish Current Timepoint” menu selection is used to continue the logic simulation
until the end of the current time point. This is useful to complete the time step during singlestepping so that the Data Analyzer waveforms are updated.
4.7.4 Step Menu Selection
The “Logic Sim/Step” menu selection single steps through the HDL source code for logic
simulation. As HyperFault single steps it places a “yellow arrow” to the left of the line.
Single stepping can be very useful when combined with breakpoints and the Watch Window for
debugging behavioral code. As you step through the HDL source code you can highlight variables
and expressions and drag and drop them into the Data Analyzer Window and the Watch Window.
The Toolbar also has a “Step” button.
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Logic Sim Menu
4.7.5 Breakpoints Menu Selection
The “Logic Sim/Breakpoints” menu selection opens the “Breakpoints” dialog box for setting
breakpoints for logic simulation. A typical method to debug a design using breakpoints would be
to set a breakpoint in a module instance, then click on the “Go” button on the toolbar and simulate
until the logic simulation stops in the module with the breakpoint. Next single step through the
module to review how the source code is executing and watch variables change value in the Watch
Window and the Data Analyzer Window. The “Go” button could then be used again to simulate
until the logic simulation stops in the module and single-stepping is resumed.
There are four types of breakpoints:
Break at Simulation Time:
The "Break at Simulation Time" selection allows you to specify a logic simulation time and
stops the logic simulation before the specified time is simulated. To specify a stop time,
select “Break at Simulation Time” in the “Type” box and enter the stop time in the
“Timepoint” box. Then choose the “Add” button.
Break at Location:
The “Break at Location” selection stops logic simulation before the selected source line is
simulated. To select a breakpoint location, you can use the “Toggle Breakpoint” button on
the Toolbar or you can use the Breakpoints dialog box. To use the “Toggle Breakpoint”
button, first open a source file window by single-stepping with the HSE, or use the
“File/Open” menu selection or “Open” button on the Toolbar to open the source file window.
Next, put the mouse cursor on an HDL source line you want to stop at. Then click-on the
“Toggle Breakpoint” button on the Toolbar to set the breakpoint. A red stop sign symbol
will be placed to the left of the line next to the line number. You can also see that the
breakpoint has been set in the “Breakpoints” dialog box.
Break in Module Instance:
The “Break in Module Instance” selection allows you to select a module instance and then
stop logic simulation each time a source line in the selected module instance is to be
simulated. To select a breakpoint location, use the Explorer Window to highlight the module
instance you want to select. In the “Breakpoints” dialog box select “Break in Module
Instance” for the “Type” box. The name of the module instance that you selected from the
“Explorer” Window will then appear in the “Scope” box. Next press the “Add” button to add
the name of the module instance to the list of breakpoints.
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Logic Sim Menu
(Breakpoints Menu Selection )
Break in Module (Any Instance):
The “Break in Module (Any Instance)” selection allows you to select a module instance and
then stop logic simulation each time a source line in any instance of the module is to be
simulated. To select a breakpoint location, use the Explorer Window to highlight the module
instance you want to select. In the “Breakpoints” dialog box select “Break in Module (Any
Instance)” for the “Type” box. The name of the module instance that you selected from the
“Explorer” Window will then appear in the “Scope” box. Next press the “Add” button to add
the name of the module instance to the list of breakpoints.
The “Add” button adds the specified breakpoint to the “Breakpoints” list. Active breakpoints are
preceded by a plus (“+”) sign. Inactive breakpoints (“Disable” button) are preceded by a minus (“”) sign. Individual breakpoints can be deleted with the “Delete” button. All breakpoints can be
deleted by the “Clear All” button. The “OK” button closes the “Breakpoints” dialog box and saves
the changes. The “Cancel” button closes the “Breakpoints” dialog box without saving the changes.
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Reports Menu
4.8 Reports Menu
The “Reports” menu provides the following menu selections:
Activity menu selection;
Errors menu selection;
Fault menu selection;
Iteration menu selection;
Nonconvergence menu selections;
Sizes menu selection.
4.8.1 Activity Menu Selection
The Reports/Activity menu selection can be used to pre-grade the test vectors for fault simulation
by reporting nodes that have no activity (level transitions) during a logic-simulation. The logic
simulation is much faster to run than fault simulation. An ACTIVITY report can be very useful for
developing input test patterns to detect circuit faults for fault simulation. The number of level
transitions at a node indicates an input test pattern's effectiveness. Faults at nodes which make no
level transitions can not be detected.
The Activity menu selection can be used to generate the following report:
An activity table that lists the node names of nodes that do not transition.
An HDL Code Coverage table that lists the lines of each file that were not executed.
This can be used to find problems with the HDL code, or stimulus that is not exercising
all of the HDL code.
An activity summary that lists totals for the number of nodes at each level of activity
count.
An activity histogram that shows known and potential level transitions versus time.
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Reports Menu
Activity Menu Selection (continued)
For the activity table for the Activity report, you will see the following legend:
Legend for "TRANSITION COUNT" column:
value
- number of definite transitions
(value)
- number of possible transitions
"H"
- no definite transitions, node High at Min time specified
"L"
- no definite transitions, node Low at Min time specified
The legend is stating that a “value” is reported to the left of a node name. A “definite” transition is
defined as a change from a Low to High level or High to Low level, even if it goes through an
intermediate Unknown level. A “possible” transition is defined as a change from a High or Low
level to the Unknown level or from the Unknown level back to a High or Low level. A “H”
reported to the left of the node name, means the node never had a definite transition, and the node
was High at the time specified as the minimum time for the time range for the report. The default
minimum time is time=0. A “L” reported to the left of the node name, means the node never had a
definite transition, and the node was Low at the time specified as the minimum time for the time
range for the report. For additional information on the Activity report, see “Activity Report For
Nodes” on page 6-2.
For the Summary for the Activity report, the percentages are based on the nodes listed that are
within the range specified for the Activity report. The default range is zero transitions for the
maximum and minimum number of transitions. The default is zero because the purpose of the
Activity report is to report nodes that did not toggle for fault simulation. If you want to set the
maximum number of transitions to greater than zero so you can see how many times the nodes are
toggling, see the “Activity Report For Nodes” on page 6-2.
4.8.2 Errors Menu Selection
The Reports/Errors menu selection reports the errors that occurred during read-in, preprocessing or
simulation. An error level of “1” indicates a warning. Error levels 2 through 5 will prevent
simulation until the error has been corrected.
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Fault Report
4.8.3 Fault Menu Selection
After fault simulation has been performed, the Reports/Fault menu selection can be used to
generate a report on the fault simulation.
Shown below is a list of the options for the Fault menu selection:
•
Detected Faults
fault (i.e. stuck-low).
Lists a detailed table of detected faults that are sorted by the type of
•
Histogram Faults
detected versus time.
Reports a fault histogram that plots actual and possible faults
•
Hypertrophic Faults
Lists a detailed table of hypertrophic faults that are sorted by the
type of fault (i.e. stuck-low).
•
Oscillating Faults
Lists a detailed table of oscillating faults that are sorted by the type
of fault (i.e. stuck-low).
•
Possible Faults
fault (i.e. stuck-low).
•
Summary Faults
Reports a fault summary that provides a table of the number of
nodes faulted, the number of hard detections, possible detections and undetected faults.
•
Undetected Faults
Lists a detailed table of undetected faults that are sorted by the type
of fault (i.e. stuck-low).
Lists a detailed table of possible faults that are sorted by the type of
For iterative fault simulation, the Fault report will show the cumulative totals for all of the fault
simulations performed with the “fsim/iterate” and “fsim/same-pattern-iterate” commands.
For distributed fault simulation, the Fault report will show the cumulative totals for all of the
master/slave fault simulations.
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Iteration Report
4.8.4 Iteration Menu Selection
The Reports/Iteration menu selection is useful for finding order of evaluation problems and race
conditions for logic simulation. This menu selection displays every signal that has more than one
iteration at a time point from time=0 to the current time point. To view a graphical display for
iterations at a time point, see “Display Iteration Data Menu Selection” on page 4-70.
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Nonconvergence
4.8.5 Nonconvergence Menu Selection
The Reports/Nonconvergence menu selection generates a report for logic simulation of any
nonconverged nodes and their oscillating states for the time point that nonconvergence occurred.
The Nonconvergence menu selection can only be used to debug nonconvergence in gate level
designs. For behavioral level designs, the Nonconvergence menu selection will produce a report
that states there is no data to report. To debug nonconvergence for behavioral designs see
“Nonconvergence (“Hanging”) for Behavioral Designs” on page 4-41.
4.8.5.1 Nonconvergence For Gate Designs
The Reports/Nonconvergence menu selection for logic simulation reports the following
information:
names of the unresolved devices and nodes.
the “type” of device and node as either a “.type” data keyword, “NODE” for a wired
connection with at least one bi-directional device or “BUS” for a wired connection
between two or more unidirectional enabled gates.
the node state values for the nonconvergence time point. State values reported are
preceded by a “...” to indicate possible previous states.
Nonconvergence for logic simulation only occurs when gate delays are zero. Zero delays can
cause the circuit to oscillate at a single time point. As the circuit oscillates, the simulator must
iterate over the circuit trying to resolve the circuit to a single set of values. When the iteration
limit is exceeded, the circuit nonconverges. A simple example of a circuit that would cause
nonconvergence is a ring of three inverters whose delays are set to zero. Zero-delays occur during
logic simulation when either a zero delay, or no delay is specified for devices (the default delay for
Verilog HDL gate devices is zero). Zero-delays also occur during logic initialization (LINIT
command), which forces delays to be zero so that HyperFault can perform a steady-state, DC
solution of the circuit at time=0.
Nonconvergence may be due either to circuit path length or problems with designs involving
feedback. To eliminate oscillations caused by problems involving feedback, the circuit design must
be corrected. When nonconvergence is due to path length, increasing the iteration limit should
enable the circuit to converge. In general, each node in a serial path length requires one iteration to
propagate a signal. The iteration limit during logic simulation is specified by the “.CONTROL
.MXITR” command. The iteration limit at time=0 is specified by the “.CONTROL .MXDCI”
command. Arbitrarily increasing the iteration limits is not recommended as it may dramatically
increase the execution time necessary to reach nonconvergence.
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Nonconvergence
To debug a non-convergence due to a problem in the circuit design, you will need to use the
NONCONV command to store the nonconvergence report (see the “Nonconvergence Summary”
on page 8-27). Many times an important clue in solving a nonconvergence is to know which signal
started oscillating first. The "probe" command can be used to find out which signal started
oscillating (see “Probing Node States” on page 8-31). Use following steps to debug your circuit:
In the Command window for the Main toolbar, enter the "disk" command to name an output
file, such as:
disk
file1
Then, in the Command window for the Main toolbar, enter the "store nonconv" command to
store the nonconvergence report in file1.
Next edit file1 and copy and paste the net names from the nonconvergence report to another
file (file2) that you have the probe command in, for example:
!probe iter time1 time_end net1,,net2,,net3
where time1 is the timepoint before the non-convergence and time_end is the
nonconvergence timepoint. If the net names use the SILOS style "(" to delimit hierarchy,
then you will have to change the "(" to ".".
Then, in the Command window for the Main toolbar, prompt input the file that has the !probe
command:
input file2
From the probe report, determine which net is oscillating first.
Next open the Data Analyzer and the Explorer Window. In the Explorer Window, select the
signal that was first oscillated and drag and drop it to the Data Analyzer. Then highlight the
signal in the Data Analyzer and use the "Trace Signal Inputs" menu to trace backwards from
the net that started oscillating so that you can draw the circuit for that net and figure out the
cause of the nonconvergence.
The Nonconvergence menu selection only reports the basic options for the nonconvergence report.
For additional options, such as the INPUT option that reports the states for all inputs of devices
which drive the oscillating nodes, and the ITER=val option that specifies the iteration number to
the 1st of eight states for each node reported for nonconvergence, see the “Nonconvergence
Summary” on page 8-27.
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Nonconvergence
4.8.5.2 Nonconvergence (“Hanging”) for Behavioral Designs
When nonconvergence occurs in behavioral designs for logic simulation, HyperFault may be able to
stop the logic simulation and report an error stating that there has been nonconvergence. For
nonconvergence during behavioral logic simulation, the “Reports/Nonconvergence Menu” selection
report may produce a report that states there is no data to report. When this happens, you can click
on the Step button on the Main Toolbar and immediately begin to single step in the nonconverged
source code.
Infinite loops in the user’s behavioral code can cause HyperFault to “hang” and not respond. When
the infinite loop occurs at time=0 HyperFault will “hang” and never get to the “Ready:” prompt.
When the infinite loop occurs during logic simulation, HyperFault will hang and does not respond to
the "STOP" button or the Esc key on the keyboard. Different techniques are used to debug “hangs”
at time=0 and “hangs” during logic simulation.
When HyperFault hangs at time=0 and the Output Window never displays the "Ready:" prompt, this
is usually due to an error in the behavioral code in an initial or an always block. The below example
hangs at time=0 due to the incorrect code "i = +1" which should be "i = i+1" in the below "for" loop:
module hang_at_0;
reg a;
integer I;
initial for (i = 0; i < 10; i = +1)
a = ~a;
endmodule
To debug a design that hangs at time=0, use comments "/* */" to comment out portions of the
design until it no longer hangs at time=0. Then inspect the commented code and fix the problem in
the behavioral code.
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Nonconvergence
When HyperFault hangs during logic simulation the program will not respond to the STOP button or
the Esc key on the keyboard. User errors in behavioral code are usually what cause HyperFault to
"hang". These errors are usually caused by a loop with no delay, such as in these code segments:
Code Segment 1:
for (i = a; b < c; i = i + 1) begin
if (d & 9'h100) == 0) begin
b = b + 1;
end
end
Code Segment 2:
always @a
b = ~b;
always @b
a = ~a;
Code segment 1) hangs when the "if" test is not true, causing the "for" loop to infinitely loop at a
time step. Code segment 2) hangs because each "always" block is triggering the other "always"
block and neither “always” block has delay.
To debug a “hang” during logic simulation, run the logic simulation until it hangs, and then note the
logic simulation time value on the status bar in the lower right-hand corner of HyperFault. Next kill
HyperFault, restart HyperFault, and press the "Load/Reload Files" button. When HyperFault stops
at time=0, enter a simulation time to one less then when the logic simulation hangs in the Command
window for the Main toolbar. Such as, if the logic simulation hangs at time=11251ns, enter "sim
11250ns" so that HyperFault stops just before it hangs. Then press the "Step" button. Keep singlestepping until you find the problem code.
If you single-step past the time point where the logic simulation was hanging, then the time value for
the status bar had not yet been updated when HyperFault hung. To find the true time value that
HyperFault hangs at, keep entering short simulation times at the "Ready:" prompt until the logic
simulation hangs, such as enter "sim 10ns" or "sim 1ns" until the logic simulation hangs. Then
restart HyperFault, re-simulate to just before the logic simulation hangs, and single-step until you
find the problem.
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Size
4.8.6 Size Menu Selection
The Reports/Size menu selection reports the memory usage for HyperFault. The maximum size of
HyperFault during logic simulation or fault simulation is read from the “/size=value” entry at the
start of the Size report, where “value” is listed in bytes.
A simpler method of obtaining the memory usage is to select the Help/About HSE menu selection
to open the About HSE dialog box, which has the memory usage for HyperFault. The memory
usage will increase during circuit read-in and preprocessing until logic simulation starts at time=0.
After logic simulation starts the memory usage remains constant.
After fault simulation, the Size report displays the maximum size of HyperFault during fault
simulation. The Size report also lists the memory usage for each hard detect.
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Explorer Menu
4.9 Explorer Menu
The “Explorer” menu provides the following menu selections:
Open Explorer menu selection;
Go to Module Source menu selection.
4.9.1 Open Explorer Menu Selection
The Explorer/Open Explorer menu selection opens a hierarchical Explorer Window. The Explorer
displays the name of every module instance and variable in the design in a tree structure similar to
the directory structure for the Windows Explorer. The shift and control keys can be used to select
variable names in a similar manner to the Windows Explorer. Names can then be dragged and
dropped to the other windows, such as the Data Analyzer Window and the Watch Window. The
Explorer Window also has context menus that can be accessed by using the right mouse button (see
“Explorer Window” on page 4-60). The Explorer is multi-threaded. This enables you to use the
Explorer or even simulate while the Explorer is “working”.
The hierarchical Explorer Window is divided into two vertical windows with the hierarchy of
module instances and gates listed in the left window and the variable names listed in the right
window. To traverse the hierarchy of the design in the left window, click-on the plus sign to the
left of the instance, or double-click on module instances. As each module instance or gate is
selected in the left window, the names of the variables in that instance are displayed in the right
window. Symbols to the left of the variables distinguish port variables (the symbol is a pad) from
variables local to the instance (the symbol is a box with an “X” for logic variables, “R” for real
variables and “I” for integer variables). Input ports have the pad symbol pointing to the right,
output ports have the pad symbol pointing to the left, and inout ports have the pad symbol pointing
in both directions.
When you open the Explorer Window, the first hierarchical name listed is the “global” module.
The global module contains the names of any global variables (see “Global Variables:” on page 720). HyperFault also has global variables called “ExpectedValueError” for checking the results of
expected values (for more information, see "Expected Values and Stimulustable" on page 6-1).
4.9.2 Go to Module Source Menu Selection
The Explorer/Go to Module Source menu selection opens a source window that displays the source
code for the hierarchical instance you selected in the left hand “Tree” side of the Explorer Window.
This enables you to quickly find the source code for a module instance when you have a large
design that spans many files scattered across many directories.
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Options Menu
4.10 Options Menu
The “Options” menu provides the following menu selection:
•
Fonts menu selection;
•
Tabs menu selection;
•
Snap to Edges;
•
Title Tips menu selection;
•
Analog Integer Display;
•
Strength Color Coding;
•
Trace Color Coding;
•
White Background;
•
Black Background;
•
Full Path Title;
•
Data Tips;
•
Syntax Color Coding.
4.10.1 Fonts menu selection
The “Options/Fonts” menu selection opens the “Fonts” dialog box for setting the fonts for the Data
Analyzer Window and the source windows..
4.10.2 Tabs menu selection
The “Options/Tabs” menu selection opens the “Tabs” dialog box for setting the number of spaces
in the Tab Interval for the source windows..
4.10.3 Snap to Edges
When setting the T1 and T2 timing markers for the Data Analyzer, they will snap to the nearest
edge if the “Options/Snap to Edges” menu selection is active. When setting a timing marker, you
can hold down the shift key to temporarily toggle the “Snap to Edges” selection to its opposite
effect. Such as, if the “Snap to Edges” is not selected, you can have the timing marker snap to the
nearest edge when you set it by holding down the shift key as you click-on the left or right mouse
button with the mouse indicator (arrow) in the Waveform Display Window.
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Options Menu
(Options Menu)
4.10.4 Title Tips menu selection
The “Options/Title Tips” menu selection enables the title tips for the signal names in the Data
Analyzer. The title tips show the full hierarchical path name for a signal.
4.10.5 Analog Integer Display
Integer variables can be displayed as a vector type of waveform or as an analog waveform. The
“Options/Analog Integer Display” menu selection sets the method of displaying integers.
4.10.6 Strength Color Coding
The “Options/Strength Color Coding” menu selection will use different colors to denote waveform
strength in the Data Analyzer:
•
Supply strength - black
•
Strong strength - blue
•
Pull strength - green
•
High-Z, Unset, and Uncertain strength - red
•
mixed strength for inserted groups and vectors - purple
4.10.7 Trace Color Coding
The “Options/Trace Color Coding” menu selection will uses a single color to denote waveforms in
the Data Analyzer:
•
Black background - white signal traces
•
White background - black signal traces
4.10.8 White Background
•
The “Options/White Background” menu selection will set the background color for the Data
Analyzer to white.
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Options Menu
(Options Menu)
4.10.9 Black Background
•
The “Options/Black Background” menu selection will set the background color for the Data
Analyzer to Black.
4.10.10 Full Path Title
The full directory path for a source file can be turned “on” or turned “off” by using the
“Options/Full Path Title” menu selection.
4.10.11 Data Tips
The Data Tips feature for displaying the value, scope, radix, and simulation time point for a
variable or expression in the source window can be toggled “on” or “off” with the Options/Data
Tips” menu selection. Any variable or expression in a source window can be viewed by opening
the source window and holding the mouse cursor over a variable or by highlighting an expression
and holding the mouse cursor over the expression. This feature enables the designer to trace the
cause of problems directly in a Verilog HDL source code window. The Open Module Source
menu selection can be used to quickly display the module definition for any instance in the
hierarchy. This saves time opening the source window for displaying the value for variables and
expressions when there are numerous files in the design.
4.10.12 Syntax Color Coding
The “Options/Syntax Color Coding” menu selection will set Verilog HDL keywords and constructs
to different colors in the source windows for HyperFault, thus increasing the readability of the
Verilog HDL text.
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Window Menu
4.11 Window Menu
The “Window” menu provides the following menu selections:
Cascade menu selection;
Tile menu selection;
Arrange Icons;
Open Explorer menu selection;
Open Watch menu selection;
Open New Data Analyzer menu selection.
4.11.1 Cascade Menu Selection
The Window/Cascade menu selection arranges multiple opened windows in an overlapped fashion.
4.11.2 Tile Menu Selection
The Window/Tile menu selection arranges multiple opened windows in a non-overlapped fashion.
4.11.3 Arrange Icons Menu Selection
The Window/Arrange Icons menu selection arranges icons for the minimized windows.
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Window Menu
4.11.4 Open Explorer Menu Selection
The Window/Explorer menu selection opens the hierarchical Explorer Window that displays the
name of every module instance and variable in the design in a tree structure similar to the directory
structure for the Windows Explorer (for more information, see “Open Explorer Menu Selection”
on page 4-44).
4.11.5 Open Watch Menu Selection
The Window/Watch menu selection opens the Watch Window that can be used to display the state
value for specified variables and expressions as you single-step through the design for logic
simulation. Variables or expressions can be dragged and dropped into the Watch Window from
any source file window, from the Explorer Window, and from the Data Analyzer window. The
Watch Window also has a context menu for setting and forcing variables to a value. The context
menu can be accessed by using the right mouse button. For more information on the Watch
Window, see “Setting and Forcing Values” for the Tutorial for the on-line help for the HyperFault
User’s Manual.
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Data Analyzer
4.11.6 Open New Data Analyzer Menu Selection
The Window/Data Analyzer menu selection opens the Data Analyzer Window that can be used to
display the waveforms for specified variables and expressions as you single-step through the
design. Variables or expressions can be dragged and dropped into the Signal Window for the Data
Analyzer from any source file window and from the Explorer Window.
The Data Analyzer Window displays the logic simulation results as waveforms. The list box to the
left of the waveforms shows the signal’s “Name”, its “Scope” (hierarchical path for the signal
name), and the “Value” of the signal at either the left axis of the waveform window or the T1
timing marker. To copy the waveform display to Microsoft Word, select the “Edit/Copy Image to
Clipboard” menu selection when the Data Analyzer Window has the focus, and then paste it into
Word.
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Data Analyzer
(Data Analyzer Menu Selection)
Scan left buttons
Scan Value
Value for the signal
Scan right buttons
Put the cursor here to display the timescale, T1
and T2 times, and the delta time.
T1, T2, and delta time
T1 and T2 timing markers, set by
the left and right mouse buttons
respectively. Hold down the shift
key to snap to edge.
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Waveforms
4.11.6.1 Digital and Analog Signal Display
Digital Signals
For digital signals, logic simulation results are displayed with waveforms denoting signal levels
and colors denoting signal strength (on color monitors).
Supply strength - black
Strong strength - blue
Pull strength - green
High-Z, Unset, and Uncertain strength - red
mixed strength for inserted groups and vectors - purple
Either the High level or Low level for the signal trace can be displayed as a thicker horizontal line.
The default setting is for the High level to be a thicker line.
For group names that are inserted into other groups, vector names, and the name for real or integer
variables, the value is displayed in the center of the waveform (resolution permitting). Doubleclicking on an inserted group or vector name will show (or hide) the individual bits. Color is used
to denote the strength for vector signals. Purple is used to represent a vector whose bits are at
different strengths. If the timing markers have been set, then the vector value is provided at the top
of the display along with the vector strength. If the bits for the vector are at different strengths, then
“Mixed Strength” is displayed at the top of the display.
When the timing markers have been set, their value is shown in the status bar at the bottom of the
Data Analyzer. If the bits are at different strengths then “Mixed Strength” is displayed for the
timing marker value.
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Analog Signals
Analog Signals
Double-click to toggle
between stepping function
and piece-wise linear.
Stepping function display of
analog signal.
Piece-wise linear display of
analog signal.
Analog signals for real variables are displayed as piece-wise linear or step waveforms. Doubleclicking on the signal name will toggle between the two methods of displaying analog signals for
real variables.
Integer variables can be displayed as a vector type of waveform or as an analog waveform. Select
the "Options/Analog Integer Display" menu selection to set the method of displaying integers.
Displaying integer variables as analog waveforms can be very useful for designing digital filters,
etc.
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Data Analyzer
4.11.6.2 Notes on using the Data Analyzer Window
Viewing More Waveforms
To create more space to display waveforms:
Decrease the size of the “Name”, “Scope”, or “Value” buttons by grabbing and moving the
vertical edge for the buttons.
Increase the size of the Waveform Display by grabbing the vertical line that separates the
“Name” list from the Waveform Display and moving the vertical line to the left or right.
Use the “View” menu to hide the Status Bar or Tool bars.
Grab the Tool bars and move them to any part of your monitor display, even outside of the
HyperFault program.
Multiple Data Analyzers
To open one or more Data Analyzer windows, you can use the “Open Analyzer” button on the
Toolbar. Each time the Analyzer is started, it can be used to simultaneously display another copy
of the logic simulation results.
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Data Analyzer
“No Saved Data”
Ensure these items are
checked if you see
“No Saved Data” in
Data Analyzer.
If the Data Analyzer reports “No Saved Data” for a waveform, check the following:
The “Save `celldefine data” option in the “Project Settings” dialog box may need to be
enabled (Project/Project Settings menu). This will save the local variables for modules in
library cells that are bounded by `celldefine and `endcelldefine.
The “Save all sim data” option in the “Project Settings” dialog box may need to be enabled
(Project/Project Settings menu). This will save the logic simulation history for every
variable.
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Data Analyzer
The “Save simulation data for this entry” in the “Module Properties” dialog box may need to
be enabled (Explorer Window/Tree/Properties menu) See “Keeping Module Instance
Simulation Variable Values” on page 8-26 for a simpler method of saving instances in the
hierarchy.
Click with right mouse button in
left side of Explorer Window to
open context menu.
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Save simulation entry should be checked
to save the simulation history.
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Help Menu
4.12 Help Menu
4.12.1 Contents menu selection
The Help/Contents menu selection opens the contents listing for the “HyperFault User’s Manual”
on-line help file.
4.12.2 Using Help menu selection
The Help/Using Help menu selection opens a Microsoft help file for an explanation of how to
effectively use the Index and on-line Help.
4.12.3 Quick Start Guide menu selection
The Help/Quick Start Guide menu selection has instructions for opening a project, creating a new
project, and simulating.
4.12.4 User’ Manual menu selection
The Help/User’s Manual menu selection provides the complete HyperFault User's Manual.
4.12.5 Verilog LRM menu selection
The Help/Verilog LRM menu selection provides the complete OVI Verilog Language Reference
Manual version 1.0.
4.12.6 SDF Manual menu selection
The Help/SDF Manual menu selection provides the complete OVI Standard Delay Format (SDF)
Manual version 2.0.
4.12.7 About HyperFault
The Help/About HyperFault menu selection opens the “About HyperFault” dialog box. This
dialog box contains the HyperFault version number, copyright notice, and the total memory
allocated in RAM memory for the logic simulation engine. The first number listed for the “Sim
Engine Mem” is the total memory allocated for the logic simulation engine. The second number
listed for the “Sim Engine Mem” is the total amount of memory that HyperFault thinks it can
possibly allocate for your computer. If you select the “Load/Reload Input Files” button on the
Main Toolbar, HyperFault will simulate to time=0. You can then use the “About HyperFault”
dialog box to determine the RAM memory usage for your design for the logic simulation engine.
To find out the amount of memory used for fault simulation, see the “Fault Monitor” on page 6-20.
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Registration
4.12.8 User Registration
The Help/User Registration menu opens the “User Registration” dialog box to update the HSE
registration.
The following is an explanation for the registration fields:
“Name”: This field is where you can personalize this copy with your name (optional).
“Company”: This field is for your company name (optional).
“Serial #”: This is the serial number of your security block on the parallel port. The HSE
automatically interrogates the parallel ports on your computer for the serial number.
“NetId: This is your Ethernet card address.
When you have completed the registration information, click on the “OK” button.
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Context Menus
4.13 Context Menus
HyperFault has context menus for the Watch Window, Explorer Window, Data Analyzer Window,
Output Window, and the source windows,. The context menus for the Output Window and the
source windows allow you to Cut, Copy, and Paste.
The context menus for windows are:
•
The right-hand side of the Explorer Window has a context menu for the “Go to Definition”,
“Add Signals to Analyzer”, “Name Filter”, “Sort by Name”, and “Sort by Type” menu
selections. To invoke this context menu, use the right mouse button to click on any part of
the right-hand side (the side with the signal names) of the Explorer Window. The context
menu will remain open while the left mouse button is used to select a menu item.
•
The left-hand side of the Explorer Window has a context menu for the “Copy Scope”, “Go
To Module Source”, “Go To Scope”, “Instance Name Filter” and “Properties” menu
selections. To invoke this context menu, use the right mouse button to click on any part of
the left-hand side (the side with the hierarchical tree) of the Explorer Window. The context
menu will remain open while the left mouse button is used to select a menu item.
•
The Watch Window has a context menu for the “Add Signal/Expression” “Set Value”, “Free
Forced Wire”, and “Clear All” menu selections. To invoke this context menu use the right
mouse button to click on any part of the Watch Window. The context menu will remain open
while the left mouse button is used to select a menu item.
•
The Data Analyzer has a context menu for the “Goto Timepoint”, “Pan to T1”, “Pan to T2”,
“Pan to Last View”, “Timescale”, “Snap to Edges”, “Add Bookmark” and “Delete
Bookmark” menu selections. To invoke this context menu use the right mouse button to
click on any part of the time point display area (the gray area just above the Waveform
Display Window). The context menu will remain open while the mouse is used to select a
menu item.
•
The Data Analyzer has a context menu for the “Trace Signal Inputs”, "Display Iteration
Data", “New Group”, “Delete Group”, “Insert Group”, “Show Groups”, “Set Radix”, “Add
“One” Bit”, “Add “Zero” Bit”, “Reverse Bit Order”, “Add Signal”, “Add Blank Line”, “Set
Strength Color Coding”, “Set Trace Color”, “Delete Item/s”, “Clear Signal List”, and
“Reload Groups”. To invoke this context menu, use the right mouse button to click on any
part of the Signal List Box. The context menu will remain open while the left mouse button
is used to select a menu item.
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Explorer Name Filter
4.13.1 Explorer Window
4.13.1.1 Go To Definition Menu Selection
The “Explorer/Signal/Go to Definition” menu selection is located in the context menu in the right
hand "Signal" side of the Explorer Window. The “Go to Definition” menu selection will
automatically open the source file, and highlight the definition line for the variable that is selected
in the right side of the Explorer Window.
To invoke this menu selection, use the right mouse button to click on a variable in the right hand
side of the Explorer Window to open the context menu. The context menu will remain open while
the mouse is used to select the “Go to Definition” menu item.
4.13.1.2 Add Signals to Analyzer Menu Selection
The “Explorer/Signal/Add Signals to Analyzer” menu selection is located in the context menu in
the right hand "Signal" side of the Explorer Window. The Add Signals to Analyzer menu selection
is useful for adding signals to the Data Analyzer when it is difficult to drag and drop the signals
due the screen size.
To invoke this menu selection, use the right mouse button to click on any part of the right hand
side of the Explorer Window to open the context menu. The context menu will remain open while
the mouse is used to select the Add Signals to Analyzer menu item.
4.13.1.3 Name Filter Menu Selection
The “Explorer/Signal/Name Filter” menu selection is located in the context menu in the right hand
"Signal" side of the Explorer Window. The Explorer Window supports the ability to filter the
names in the right-hand window of the Explorer.
To invoke this menu selection, use the right mouse button to click on any part of the right hand
side of the Explorer Window to open the context menu. The context menu will remain open while
the mouse is used to select the Name Filter menu item.
The name filtering in the Explorer Window uses regular expressions. Explanations for regular
expressions can be found in many programming books. For a short description of regular
expressions, see “Regular Expressions” on page 1-24.
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Explorer Context Menus
4.13.1.4 Sort by Name or Type Menu Selections
The “Explorer/Signal/Sort by Name” and the “Explorer/Signal/Sort by Type” menu selections are
located in the context menu in the right hand "Signal" side of the Explorer Window. The Explorer
Window supports the ability to sort the names in the right-hand window by the type of variable
(port, wire, register, etc.), or by name.
4.13.1.5 Copy Scope Menu Selection
The “Explorer/Tree/Copy Scope” menu selection is located in the context menu in the left hand
"Tree" side of the Explorer Window. When you select a hierarchical instance in the Explorer
Window, the “Copy Scope” menu selection (or simultaneously holding down the “Ctrl” and the
“C” keys on the keyboard) will copy the hierarchical instance name to the Windows Clipboard.
This enables you paste the hierarchical name (simultaneously holding down the “Ctrl” and the “V”
keys on the keyboard) for the Device Under Test (DUT) entry in the “Fault Simulation Settings”
dialog box.
To invoke this menu selection, use the right mouse button to click on any part of the left hand side
of the Explorer Window to open the context menu. The context menu will remain open while the
mouse is used to select the Go To Module Source menu item.
4.13.1.6 Go to Module Source Menu Selection
The “Explorer/Tree/Go to Module Source” menu selection is located in the context menu in the
left hand "Tree" side of the Explorer Window. When you select a hierarchical instance in the
Explorer Window, the “Go to Module Source” menu selection opens a source window that displays
the source code for the hierarchical instance. This enables you to quickly find the source code for
any instance in your design.
To invoke this menu selection, use the right mouse button to click on any part of the left hand side
of the Explorer Window to open the context menu. The context menu will remain open while the
mouse is used to select the Go To Module Source menu item.
4.13.1.7 Go to Scope Menu Selection
The “Explorer/Tree/Go to Scope” menu selection is located in the context menu in the left hand
"Tree" side of the Explorer Window. This feature enables you to quickly find an instance in the
Explorer Window. The “Go to Scope” menu selection opens the “Enter Scope” dialog, where you
specify the scope for the instance that you want to find. Then click on the “Ok” button and the
Explorer Window will highlight the instance you selected.
To invoke this menu selection, use the right mouse button to click on any part of the left hand side
of the Explorer Window to open the context menu. The context menu will remain open while the
mouse is used to select the Go To Scope menu item.
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Explorer Context Menus
4.13.1.8 Instance Name Filter Menu Selection
The “Explorer/Tree/Instance Name Filter” menu selection is located in the context menu in the left
hand "Tree" side of the Explorer Window. This feature allows you to use a regular expression to
filter the instance names to assist you with quickly finding an instance in the Explorer Window.
The “Instance Name Filter” menu selection opens the “Name Filter” dialog, where you specify the
filter for the instance that you want to find. Then click on the “Ok” button and the Explorer
Window will show only the instances you selected. For more information on regular expressions,
see “Regular Expressions” on page 1-24.
4.13.1.9 Properties
The “Explorer/Tree/Properties” menu selection is located in the context menu in the left hand
"Tree" side of the Explorer Window. The “Properties” menu selection opens the “Module
Properties” dialog box. The Module Properties” dialog box enables you to specify which module
instances you want to save the simulation data for during logic simulation. You can also see
“Keeping Module Instance Simulation Variable Values” on page 8-26 for a simpler method of
saving instances in the hierarchy.
If the “Save simulation data for this entry” is selected, then HyperFault saves the simulation data
for the following items during logic simulation:
all local variables for the module instance;
all port variables for the module instance (even if the ports connect to module instances that
are not saved below it in the hierarchy);
any instance below it in the hierarchy of the design, unless the instance below it is
specifically not saved.
If the “Save simulation data for this entry” is not selected, then HyperFault does not save the
simulation data for following items during logic simulation:
all local variables for the module instance not selected;
the simulation data for any instance below it in the hierarchy of the design.
Before the “Save simulation data for this entry” specifications can take effect, the Project must be
reloaded by using the Project/Open menu selection or by selecting a project name from the Most
Recently Used list of projects at the end of the Project menu.
To invoke this menu selection, use the right mouse button to click on any part of the left hand side
of the Explorer Window to open the context menu. The context menu will remain open while the
mouse is used to select the Properties menu item.
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Watch Context Menus
4.13.2 Watch Window
4.13.2.1 Add Signal/Expression Menu Selection
The “Watch/Add Signal/Expression” menu selection opens the “Specify Signal/Expression” dialog
box. To invoke this menu selection, use the right mouse button to click on any part of the Watch
Window to open the context menu. The context menu will remain open while the mouse is used to
select the Add Signal/Expression menu item.
The “Specify Signal/Expression” dialog box contains an edit box “Scope” to specify the scope for
the signal. The “Specify Signal/Expression” dialog box also contains an edit box
“Signal/Expression” to enter a signal or an expression. Any valid Verilog HDL expression can be
entered. If the expression or scope is not valid then the expression will list an “Error”.
The OK button closes the dialog box and displays the specified expression in the Watch Window.
The Cancel button closes the dialog box and does not display the expression.
4.13.2.2 Set Value For Watch Window
The “Watch/Set Value” context menu selection can be used to force or set a vector in the Watch
Window. To invoke this menu selection, use the right mouse button to click on any part of the
Watch Window to open the context menu. The context menu will remain open while the mouse is
used to select the Set Value menu item.
4.13.2.3 Free Forced Wire For Watch Window
The “Watch/Free Forced Wire” context menu selection frees a wire that has been forced in the
Watch Window. To invoke this menu selection, use the right mouse button to click on any part of
the Watch Window to open the context menu. The context menu will remain open while the
mouse is used to select the Free Forced Wire menu item.
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Watch Context Menus
4.13.2.4 Clear All For Watch Window
The “Watch/Clear All” context menu selection clears all of the expressions from the Watch
Window. To invoke this menu selection, use the right mouse button to click on any part of the
Watch Window to open the context menu. The context menu will remain open while the mouse is
used to select the Clear All menu item.
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Analyzer Context Menus
4.13.3 Data Analyzer Context menus
4.13.3.1 Data Analyzer Timeline Area
4.13.3.1.1
Goto Timepoint menu selection
The “Analyzer/Timepoint/Goto Timepoint” menu selection opens the “Goto Timepoint” dialog
box for specifying the time point for the left axis or the center of the Waveform Display Window.
The “Goto Timepoint” dialog box enables you to precisely position the Waveform Display
Window for debugging and printing. The time value for the “Time Point” box can be specified in
any standard time unit, such as “ns” for nano seconds, “ps” for pico seconds, etc., i.e.:
12000.3ns
To invoke the context menu use the right mouse button to click on any part of the timeline display
area (the gray area just above the Waveform Display Window). The context menu will remain
open while the mouse is used to select the Goto Timepoint menu item.
4.13.3.1.2
Pan to T1, Pan to T2, and Pan to Last View menu selection
The “Analyzer/Timepoint/Pan to T1” menu selection and the “Pan to T2” menu selection will
center the Waveform Display Window around the T1 or T2 timing marker. The “Pan to Last
View” will return the Waveform Display Window to the preceding view. These menus are useful
during debugging for jumping between views of the logic simulation results.
To invoke the context menu use the right mouse button to click on any part of the timeline display
area (the gray area just above the Waveform Display Window). The context menu will remain
open while the mouse is used to select the Pan to T1, Pan to T2, or Pan to Last View menu item.
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Analyzer Context Menus
4.13.3.1.3
Timescale menu selection
The “Analyzer/Timepoint/Select Timescale” menu opens the “Time Scale” dialog box for setting
the number of time units per division of display. Setting the timescale is useful for debugging the
design.
The current time scale, T1 time value, T2 time value, and delta time value can be displayed by
holding the mouse cursor over the timeline for a few seconds. To modify the time scale, open the
“Time Scale” dialog box and enter a value in the “Time/Div” box. You can use any standard time
unit, such as “ns” for nano seconds, “ps” for pico seconds, etc. i.e.:
12000.3ns
The “OK” button closes the dialog box and causes the Data Analyzer to use the selected time scale.
The “Cancel” button closes the dialog box and does not affect the Data Analyzer.
To invoke the context menu use the right mouse button to click on any part of the time point
display area (the gray area just above the Waveform Display Window). The context menu will
remain open while the mouse is used to select the Select Timescale menu item.
4.13.3.1.4
Snap to Edges Menu Selection
When setting the T1 and T2 timing markers for the Data Analyzer, they will snap to the nearest
edge if the “Analyzer/Timepoint/Snap to Edges” menu selection is active.
When setting a timing marker, you can hold down the shift key to temporarily toggle the “Snap to
Edges” selection to its opposite effect. Such as, if the “Snap to Edges” is not selected, you can
have the timing marker snap to the nearest edge when you set it by holding down the shift key as
you click-on the left or right mouse button with the mouse indicator (arrow) in the Waveform
Display Window.
To invoke the context menu use the right mouse button to click on any part of the time point
display area (the gray area just above the Waveform Display Window). The context menu will
remain open while the mouse is used to select the Snap to Edges menu item.
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Bookmark
4.13.3.1.5
Add Bookmark menu selection
The “Analyzer/Timepoint/Add Bookmark” menu selection enables you to place a virtual marker
for the time and the timescale resolution of the center of the Waveform Display Window. When
debugging your design, the bookmakers you set enable you to jump back and forth between
waveform views with the same or different timescale.
After opening the “Add Bookmark” dialog box you will see the default bookmarks, i.e.
“Bookmark1”, “Bookmark2”, etc. You can specify any string of characters for the bookmark name
and then click-on OK to set the bookmark. The bookmarks you have set are listed at the bottom of
the context menu. To go to a bookmarker select it with the left mouse button.
To invoke the context menu use the right mouse button to click on any part of the time point
display area (the gray area just above the Waveform Display Window). The context menu will
remain open while the mouse is used to select the Add Bookmark menu item.
4.13.3.1.6
Delete Bookmark menu selection
The “Analyzer/Timepoint/Delete Bookmark” menu selection enables you to delete a bookmarker.
After opening the “Delete Bookmark” dialog box you will see the bookmarkers, i.e. “Bookmark1”,
“Bookmark2”, listed in the “Bookmarks” list box. You can delete a bookmark by selecting it with
the mouse can clicking-on the “Delete” button. Click on the OK button to close the dialog box.
To invoke the context menu use the right mouse button to click on any part of the time point
display area (the gray area just above the Waveform Display Window). The context menu will
remain open while the mouse is used to select the Delete Bookmark menu item.
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Trace Signal Inputs
4.13.3.2 Data Analyzer Signal List Box
4.13.3.2.1
Trace Signal Inputs Menu Selection
The “Analyzer/Name box/Trace Signal Inputs” menu selection opens a Trace Signal Inputs
Window. The Trace Signal Inputs Window allows you to interactively trace an incorrect value at a
net to its cause by displaying the waveforms of all the devices that are driving the net.
To invoke the context menu, use the right mouse button to click on any part of the Name list box.
The context menu will remain open while the mouse is used to select the Trace Signal Inputs menu
item.
When you wish to trace a net, highlight a signal name in the Name list box of the Data Analyzer.
With the mouse cursor still in the Name list box, click on the right mouse button to open the
context menu. Next, select the “Trace Signal Inputs” menu selection in the context menu. A Trace
Signal Inputs Window will then be opened and it will display the signals that are driving the net
you selected.
To continue the fan-in tracing, double-click on any input and the waveform for that node will be
displayed along with the waveforms for the devices driving it. To “undo” your signal tracing,
double-click on the node name that is being traced.
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Trace Signal Inputs
When the waveforms for the Trace Signal Inputs Window are displayed, the name of the node
being traced is listed first in the Name box. Blank lines delineate each device listed in the Name
box. The format for each device is similar to the format for a module instance when passing ports
by name in Verilog HDL. For example, the name:
not top.bit4.dff2.n6 (
.out (top.bit4.dff2.\q_<specify> )
.in (top.bit4.dff2.\qbar_<specify> ))
the device is a “not” gate and the instance name is “top.bit4.dff2.n6”. The output port name
“.out” has the instance name “top.bit4.dff2.\q_<specify>“. The input port name “.in” has the
instance name “top.bit4.dff2.\q_<specify>“.
You can continue to double-click on device inputs and trace your way back through the topology.
To “undo” your signal tracing, double-click on the signal name that was traced. If you see “No
Saved Data” instead of a waveform, this may mean that the signal is inside of a `celldefine
boundary. To save data within `celldefine boundaries, see the “Save `celldefine data” option in the
“Project Settings Menu Selection” on page 4-15.
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Display Iteration
4.13.3.2.2
Display Iteration Data Menu Selection
The “Analyzer/Name box/Display Iteration Data” menu selection is useful for finding order of
evaluation problems and race conditions.
To invoke the context menu, use the right mouse button to click on any part of the Name list box.
The context menu will remain open while the mouse is used to select the Display Iteration Data
menu item.
When the “Display Iteration Data” menu selection is selected it opens an Iteration Data Window
that displays all of the iterations at a single timepoint for each signal in the Name list box. The
timepoint to display the iterations is specified by the T1 timing marker.
To display a text report for iterations at a timepoint, see “Iteration Menu Selection” on page 4-38.
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Groups
4.13.3.2.3
Groups of Signals
Using groups provides a convenient method for organizing your signals in the Data Analyzer
Window. Not only does this help organize the display of your signals, it also prevents you from
losing your list of signals if the default group gets inadvertently changed or lost. Display groups
are also useful for assisting engineers who are unfamiliar with the design, and for record keeping if
the design is reused.
The context menu for the Name list box provides the following selections for groups:
Selections for groups.
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Groups
(Groups of Signals)
New Group: This selection can be used to add a new group to the Name list box.
Delete Group: This selection can be used to delete a group.
Insert Group: This selection opens the “Add Group” dialog box. This dialog box will insert
a group within a group. The inserted group is displayed as a bus, which can be expanded and
hidden by double-clicking on it.
Show Groups: This selection opens the “Select Signal Groups” dialog box. This dialog box
can be used to select which groups are displayed in the Data Analyzer.
To invoke the context menu, use the right mouse button to click on any part of the Name list box.
The context menu will remain open while the mouse is used to select the group menu item of
interest.
When the Data Analyzer Window is opened, the “Default” group is displayed. To save any signals
that are added to the Default group, click on the minus sign “-” just to the left of the Default group
in the Name list box. HyperFault will ask you if you want to save the changes to the Default
group.
4.13.3.2.4
Set Radix Menu Selection
The “Analyzer/Name box/Set Radix” menu selection is located in the context menu for the Name
list box. Setting the radix for a vector can assist with debugging the design. The radix can be set
to binary, octal or hexadecimal to conveniently display the vector. Symbolic names can be used to
represent the values for a state machine. ASCII vectors can be displayed to create a timeline of
events for the Data Analyzer display.
To invoke the context menu, use the right mouse button to click on any part of the Name list box.
The context menu will remain open while the mouse is used to select the Set Radix menu item.
To set the radix for a vector:
Click on the vector with the right mouse button to open the context menu.
Next, select the “Set Radix” menu selection in the context menu.
The “Set Radix” dialog box will then be opened and you can select the Radix.
If you select the “Symbol Table” radix, then select the correct symbol table in the “Symbol
Table” box.
The OK button closes the dialog box and sets the vector to the selected radix. The Cancel button
closes the dialog box and does not affect the vector’s radix.
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Bit Menus
4.13.3.2.5
“Bit” Menu Selections
The context menu for the Name list box for the Data Analyzer has the following selections:
Add "One" Bit - adds a single bit signal at a high level just ahead of the selected signal name.
Add "Zero" Bit - adds a single bit signal at a low level just ahead of the selected signal name.
Reverse Bit Order - reverses the signal order for the highlighted signals in the Name list box.
This is useful for reversing the bit order for a group.
To invoke the context menu, use the right mouse button to click on any part of the Name list box.
The context menu will remain open while the mouse is used to select the Set Radix menu item.
4.13.3.2.6
Add Signal Menu Selection
The “Data Analyzer/Name box/Add Signal” menu selection opens the “Specify Signal/Expression”
dialog box. Adding a signal can be very useful for performing conditional searches. The added
waveform can be any expression whether the expression exists in your HDL source code or not.
For a conditional search, you can then use the scan to change feature and the States List Box to
review the signal values for the conditional search.
The Add Signal feature can also be useful for adding expressions that exist in your source code,
such as for an “if” test, and then viewing then the expression is true (high).
The “Specify Signal/Expression” dialog box contains an edit box “Scope” to specify the scope for
the signal. The “Specify Signal/Expression” dialog box also contains a “Signal or (Expression)”
edit box to enter a signal or an expression. Any valid Verilog HDL expression can be entered,
however, the expression must be enclosed by parentheses. You can copy and paste an expression
that is in your source code window by highlighting the expression and using the “Ctrl c” keys on
the keyboard to copy and the “Ctrl v” keys to paste the expression into the Signal or (Expression)
list box. If the expression or scope is not valid then the waveform will be blank.
The OK button closes the dialog box and displays the specified expression in the Data Analyzer.
The Cancel button closes the dialog box and does not display the expression.
If you single click on the expression that you added to the Data Analyzer, pause, then click on the
expression again, you can modify the expression.
4.13.3.2.7
Add Blank Line Menu Selection
The “Data Analyzer/Name box/Add Blank Line” menu selection inserts a blank line in the Data
Analyzer just above the signal name that is highlighted..
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Clear Signal
4.13.3.2.8
Set Strength Color Coding Menu Selection
The “Data Analyzer/Name box/Set Strength Color Coding” menu selection uses color to denote
waveform strength.
4.13.3.2.9
Set Trace Color Menu Selection
The “Data Analyzer/Name box/Set Trace Color” menu selection opens the “Select Trace Color”
dialog box, which can be used to select a color for a waveform.
4.13.3.2.10
Delete Item/s Menu Selection
The “Data Analyzer/Name box/Delete Items” menu selection deletes all of the signal names that
are selected by the user in the Name list box.
4.13.3.2.11
Clear Signal List Menu Selection
The “Data Analyzer/Name box/Clear Signal List” menu selection deletes all of the signal names in
the Name list box..
4.13.3.2.12
Reload Groups Menu Selection
The "Data Analyzer/Name box/Reload Groups" menu selection will cause the Data Analyzer to
clear the list box and reload the group information from the project file. This is useful when a user
written program is used to modify the groups while Silos is running.
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Source Window Context Menus
4.13.4 Source Window Context menus
4.13.4.1 Undo menu selection
The “Source Window/Undo” menu selection undoes your last editing or formatting action,
including cut and paste actions. If an action cannot be undone, Undo appears dimmed on the Edit
menu.
4.13.4.2 Cut menu selection
The “Source Window/Cut” menu selection deletes text from a document and places it onto the
Clipboard, replacing the previous Clipboard contents.
4.13.4.3 Copy menu selection
The “Source Window/Copy” menu selection copies text from a document onto the Clipboard,
leaving the original intact and replacing the previous Clipboard contents.
4.13.4.4 Paste menu selection
The “Source Window/Paste” menu selection pastes a copy of the Clipboard contents at the
insertion point, or replaces selected text in a document.
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Source Window Context Menus
(Source Window Context menus)
4.13.4.5 Add/Remove Breakpoint menu selection
The “Source Window/Add or Remove Breakpoint” menu selection places or removes a simulation
breakpoint at the location of the cursor in the source window.
4.13.4.6 Data Tips menu selection
The “Source Window/Data Tips” menu selection toggles the Data Tips capability “on” or “off”.
The Data Tips capability displays the value, scope, radix, and simulation time point for a variable
or expression in the source window. Any variable or expression in a source window can be viewed
by opening the source window and holding the mouse cursor over a variable or by highlighting an
expression and holding the mouse cursor over the expression. This feature enables the designer to
trace the cause of problems directly in a Verilog HDL source code window.
4.13.4.7 Data Tip Radix menu selection
The “Source Window/Data Tip Radix” menu selection sets the radix for the Data Tips capability.
The allowed radixes are binary, octal, hexadecimal, decimal and string.
The Data Tips capability displays the value, scope, radix, and simulation time point for a variable
or expression in the source window. Any variable or expression in a source window can be viewed
by opening the source window and holding the mouse cursor over a variable or by highlighting an
expression and holding the mouse cursor over the expression. This feature enables the designer to
trace the cause of problems directly in a Verilog HDL source code window.
4.13.4.8 Go to Instance menu selection
When viewing source code, you can select a line of source code and use the “Source Window/Go
to Instance” selection in the context menu of the source window to open the Explorer at the
instance for that line. This provides you with a hierarchical representation for the selected line of
source code.
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Output Window Context Menus
4.13.5 Output Window Context menus
4.13.5.1 Copy menu selection
The “Output Window/Copy” menu selection copies text from a document onto the Clipboard,
leaving the original intact and replacing the previous Clipboard contents.
4.13.5.2 Select All menu selection
The “Output Window/Select All” menu selection selects all the text in a document at once. You
can copy the selected text onto the Clipboard, delete it, or perform other editing actions.
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$fs_dut
5. System Tasks
5.1 Device Under Test ($fs_dut system task)
The $fs_dut system task is used to identify the device under test (DUT). This system task is
required for all fault simulation runs. .
$fs_dut( full_hier_name );
$fs_dut
name of system task that specifies which parts of the HDL design can become part
of the faulted circuit as the effects of a fault are propagated.
full_hier_name represents the full hierarchical path name for the device under test. If the device
under test is at the top level, then simply specify its module name. For iterative
fault simulation runs, this name can be changed, e.g. "(test(top" and "(TEST(top".
This assists with using different test benches during iterative fault simulation.
Application Note:
1)
A purpose of the $fs_dut system task is to reduce memory usage by ensuring that the test
bench is not loaded into memory with each fault.
2)
Sometimes designers use “$readmemb” or “$readmemh” system tasks to load large
stimulus files into memory variables in their test bench. A preferred method of loading
stimulus for the test bench is to use the “stimulustable” statement (see “Expected Values
and Stimulustable” on page 7-6). The “stimulustable” statement has the advantage that it
is read into memory in chunks so the impact of the “stimulustable” statement on faulted
partitions is minor.
3)
When applying faults to a block of the design, keep the $fs_dut system task pointing to
the top level of the design. Use the wildcard fault specification to apply the faults to a
block of the design (see “Selecting Faults by Wildcards” on page 1-18).
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$fs_dut
($fs_dut system task)
Example:
1)
The below example shows how the device under test is specified so that the large memory
variable “big” is not loaded into memory for each faulted circuit:
‘celldefine
‘timescale 100ps / 100 ps
‘suppress_faults
‘enable_portfaults
module NAND2(A, B, Y);
input A, B;
output Y;
nand ND1 (Y, A, B);
endmodule
‘disable_portfaults
‘nosuppress_faults
‘endcelldefine
module test_bench;
reg in1_r, in2_r;
reg [10000:0] big[0:1000];
NAND2 dut (in1_r, in2_r, out); <--- device under test
initial
begin
$fs_dut (test_bench.dut); <--- $fs_dut command
$readmemb (“mem.v”, big);
big[0] = 0;
in1_r = 0; in2_r =0;
#10 in1_r = 1;
#10 $finish;
end
initial #10
forever #100 $fs_strobe(out);
endmodule
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$fs_options
5.2 Fault Simulation Options ($fs_options system task)
The $fs_options system task is used to specify distributed fault simulation (bold is required syntax,
plain is optional syntax, italics is user specified).
Single Processor Fault Simulation Options
$fs_options (
"max_memory = n ",
"hypertrophic='n' ",
"checkpoint_interval=time",
"carry_possible_counts=n",
);
Distributed Fault Simulation Options
Options for the Master Process
$fs_options (
Additional Options for the Master Process
"process_weight = n " ,
"faults_per_pass = n " ,
"max_memory = n ",
"hypertrophic= 'n' ",
"checkpoint_interval=time",
"carry_possible_counts=n",
"sample = n ",
"retry_possible_detects=n",
"process_name = ' ' "
);
Options for a Slave Process
$fs_options (
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$fs_options
($fs_options)
Required Options for a Slave Process
"process_name = 'name' " ,
"process_hostname = 'hostname' " ,
Additional Options for a Slave Process
"process_weight = n " ,
"process_command = ' command ' " ,
"faults_per_pass = n " ,
"max_memory = n ",
"hypertrophic= 'n' ",
"checkpoint_interval=time",
"carry_possible_counts=n",
"process_nfs_prefix = ' prefix ' " ,
// Unix only
"process_mount_point = ' mount ' " , // NT only
"nt_net_use = ' string … string ' "
// NT only
"retry_possible_detects=n",
);
$fs_options
name of system task for specifying distributed fault simulation. The
double quotes ( " " ) and single quotes ( ' ' ) for each of the options are a
part of the syntax. Each master and slave process must be specified with
its own $fs_options system task. Note that only one “fsim / options”
command can be used for each distributed fault simulation run. For
example, you can have a distributed fault simulation run that uses either
the “!fsim” command or the “!fsim / iterate” command, but not a
distributed fault simulation run that uses both commands.
"faults_per_pass = n "
this option specifies the number of concurrent faults "n" per pass for each
process. When specified on the master process, the slave process will
inherit the faults_per_pass value unless it is specified on the slave. The
faults_per_pass setting will override the HyperFault “fcontrol .fmem”
command for setting the concurrent faults per pass. When the
“$fs_options(“max_memory=value”);” system task is used, the
"faults_per_pass = n " option limits the number of faults per pass to “n”.
Maximum allowed value for “n” is 8,000.
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$fs_options
($fs_options)
"sample = n "
this option specifies a percentage of the total faults to be randomly
selected for all fault models: the output stuck-at-low faults, output
stuck-at-high faults, input stuck-at-low faults, and input stuck-at-high
faults.
The value for “n” is an integer from 1 to 100. If decimal values are
specified they will be truncated. If zero is specified, the “sample=n”
option is ignored.
The “sample = n ” option is specified on the master process. The slave
processes inherit the sampled fault list from the master process. This
option is ignored if it is specified on a slave process.
The “sample = n ” specification will override a statistical percentage
of faults specified by the volow, vohigh, vilow, and vihigh HyperFault
commands. The “sample=n” is ignored if faults are named by the
volow, vohigh, vilow, and vihigh HyperFault commands, or wildcards
are used by the vreslow, vreshigh, vreislow, and vreishigh HyperFault
commands.
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$fs_options
($fs_options)
"process_name = 'name' "
this option specifies a process name for a slave CPU. The
process_name is a name that the user creates and specifies, such as
alpha or beta. The name specified cannot contain the quotation mark
character or blanks. This option must be first in the list of options
applying to a slave process.
The master process can be designated by specifying two consecutive
single quotation marks (a null argument), or by omitting this option.
The master $fs_options system task must be parsed before any slave
$fs_options system tasks are parsed.
The process name is appended to the fault simulation save file and log
file to uniquely identify these files for each slave. If there are
problems with running distributed fault simulation, the log file (and
also on NT the .bat file) can be useful for understanding the cause of
the problem.
On Unix, the log file is named “save.log.slave_process_name”, where
slave_process_name is the name of the slave process, i.e.
save.log.alpha.
On WinNT, the log file is named save.slave_process_name.blg where
slave_process_name is the name of the slave process, i.e.
save.alpha.blg. WinNT also has an additional file,
save.slave_process_name.bat, i.e. save.alpha.bat, used to run the slave
process on the slave machine.
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$fs_options
($fs_options)
"process_hostname = 'hostname' " this option specifies the network name of the CPU to run the
process on. This option is required for slave processes.
On Unix, this name is found by entering “hostname” at the
Unix prompt.
On NT, this name is found by selecting the
“Start/Settings/Control Panel” menu, then selecting the
Network applet, and reading the Computer Name on the
Identification tab.
"process_weight = n "
this option specifies a percentage of the total fault set given to
a process. The default for this option is “1” for the master
process and for each slave process. The fault partitioning
algorithm is:
f = ( n / N) (F)
where “f” is the number of faults assigned to a process, “n” is
the process weight, “N” is the sum of all the process weights,
and “F” is the total number of faults.
For example, if a distributed fault simulation has a master
process with a process weight of 1, and two slave processes
with process weights of 4 and 5 respectively, then the master
process would receive 10% of the faults, and the slave
processes would receive 40% and 50% of the faults
respectively. The process_weight "n" is must be a positive
integer whose range is from 1 to (2**32-1).
"max_memory = n "
When this option is specified, the fault simulator will attempt
to keep the process size within the amount of memory
specified (in bytes). It will accomplish this by adjusting the
number of concurrent faults per pass, both at the beginning of a
pass and during the simulation of the pass itself. This option
has no affect on logic simulation.
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$fs_options
($fs_options)
("max_memory = n ")
Below is a sample of the output from a “!fmon” fault monitor command for the
following $fs_options:
$fs_options("process_name = '' ",
"process_weight = 1",
"max_memory=6000000");
Fault Monitor Report
!fmon
!fsim 0 10k
Fault sim begins
.SLOW
Max Possible Faults:
304
Percent Random Select: 100
Non-Redundant Faults: 178
.SHIGH
304
100
178
Total Faults to be Simulated:
.ISLOW
665
100
527
.ISHIGH
664
100
501
1384
Memory available for fault effects: 5048936 bytes. Limit: 6000000
bytes
Beginning 58 concurent faults per pass.
6% Complete
1% Detection
5936472 bytes
0.49s user 0:00:00 elapsed
Completed 48 concurent faults in last pass.
Suspended faults = Beginning faults - Completed faults
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$fs_options
($fs_options)
("max_memory = n ")
Please note the following items:
When the “max_memory” option is not specified in a master or a slave, it
is disabled.
When the “max_memory” option is specified in the master and not the
slaves, it is inherited by the slaves.
When the “max_memory” option is specified on a slave, it overrides any
value also specified on a master.
"hypertrophic= ‘n’ "
this option specifies the percentage of the design that the fault affects
before the fault is declared as a hypertrophic detection and dropped. For
most fault simulations, relatively few faults cause most of the memory
usage and the run time duration. By assuming that the hypertrophic faults
will be detected and dropping them early in the fault simulation run, the
advantage is to reduce the fault simulation run time and memory usage.
Hypertrophic faults are considered as detected for the fault monitor
(FMON command) report listings of “Total Faults Detected”, “Actual
Detected Faults”, and “Actual Detection Rate”. Hypertrophic faults
appear in the fault report in the “Fault Summary Table” under the heading
"Hypertrophic Detection". In the specification "hypertrophic= ‘n’ ", “n”
can be an integer number from 0 to 100 (decimal values will be truncated).
The default value is 5.
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$fs_options
($fs_options)
"checkpoint_interval=time "
When this option is specified, HyperFault will update the fault
dictionary file with sufficient information to re-start the fault
simulation run without loss of data from a crashed run. The fault
dictionary file will be updated every “time” seconds, where “time”
is specified on the “checkpoint_interval” option. When a
checkpoint occurs, HyperFault will write a message to the standard
output window.
An example of using the “checkpoint_interval” option is: to
checkpoint the fault simulation at least every hour, specify
"checkpoint_interval=3600 ". To restart the fault simulation from
the last checkpoint in the event of a crash, enter the “fsim”
command that was used to start the crashed run, and append “/
recovery" to the “fsim” command. Some examples are:
before crash
to recover
fsim
fsim/recover
fsim 0 10k
fsim 0 10k/recover
fsim/recover
fsim/recover
The option "/recover" causes HyperFault to read the fault
dictionary file, and initialize itself from the crashed run, instead of
starting from scratch. So, in the initial run, don't use "/recover", or
you won't have an initial run, just a recovered one! Note that in
the event of a crash for the run that is already recovering, you don't
have to change anything.
"carry_possible_counts=n"
Soft detect counts are brought forward from prior runs when
"carry_possible_counts=1” is specified (default). For example,
when "fsim/iterate" or “fsim/same-pattern-iterate” is used, if a
stuck low fault on net “out1” has four soft detects from the
previous fault simulation run, then one soft detect on stuck low
fault net “out1” during the current run would cause it to be a
possible detect (if the possible detect threshold is set to 5).
"carry_possible_counts=0” means possible counts do not
contribute to the next pattern when "fsim/iterate" or “fsim/samepattern-iterate” is used.
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$fs_options
($fs_options)
"process_command = 'command' "
this option specifies the location of the HyperFault
executable for the slave process. When specified on the
master process, the slave process will inherit the
"process_command = 'command' " unless it is specified on
the slave. If this option is omitted, the location of
HyperFault is the full path to the executable used to start the
master process. For example, if the command used to start
the master process is "hyperflt", then the default command to
start the slave processes is "path_name_hyperflt", where
path_name_hyperflt is the full path name to HyperFault on
the master machine. If the path name to the HyperFault
executable is different on the slave machine, then the full
path name to the executable on the slave machine must be
specified.
"process_nfs_prefix = 'prefix' "
(Unix only) this option specifies the root directory of the host
network for Unix, allowing you to specify the full directory
path name to any file on the network. This option is only
useful if the file system for the master process is not
accessible to the slave process (i.e., the master’s file system
is not mounted on the slave computer). When specified on
the master process, the slave process will inherit the prefix
unless it is specified on the slave. The master process
ignores this option.
For example, if your current directory is
/hyperfault/examples, the hostname is simucad, and the
prefix is /net, HyperFault will use
/net/simucad/hyperfault/examples as the path name for
finding files for the slave processes.
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$fs_options
($fs_options)
"retry_possible_detects=n"
This option allows possible detects to remain active in the
event they become a hard detect, or they can be re-injected
during the “fsim/iterate” or “fsim/same-pattern-iterate”
commands if the fault is among those currently selected. A
value of 0 (default) for “n” means a fault which becomes a
possible detect will be dropped from further processing. A
value of 1 for “n” means a fault which becomes a possible
detect will have the opportunity to become a hard detect by
doing two things:
After being detected as possible, the fault remains active.
During "fsim/iterate" or “fsim/same-pattern-iterate”, a
previous possible detect will be re-injected if the fault is
among those currently selected.
"process_mount_point = 'mount' "
(NT only) the process_mount_point specifies an unused drive
letter on the slave computer. For example:
“process_mount_point = ‘R:’”
where “R:” is the name of the unused drive on the slave
computer.
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$fs_options
($fs_options)
"nt_net_use = 'slave_drive master_drive m_password master_user' "
(NT only) this option
specifies the link between the slave drive and the master
drive on Windows NT.
slave_drive - this represents any unused drive letter on the
slave machine. This drive letter must be the same drive letter
specified by the "process_mount_point” option, for example
“R:”.
master_drive - this represents the full network path to the
drive on the master machine where the design is located. For
example, \\\\MAINE\\D specifies that MAINE is the
“Computer Name” for the master machine, and D is the drive
letter where the design is located on the master machine.
Notice that each of the backslashes (“\”) has to be escaped
with another backslash.
m_password - this represents the password for the master
machine. The password is case sensitive.
master_user - this represents the “Workgroup” name and user
name on the master machine. For example,
/user:simucad\george specifies that the “Workgroup” name
is “simucad” and the user logon name is “george”.
An example of the "nt_net_use" option is:
$fs_options("nt_net_use = 'r: \\\\maine\\d password
/user:simucad\\george' ");
When the Graphical User Interface is used to run distributed
fault simulation, a mount command to mount an unused drive
letter, such as "process_mount_point='R:' " is issued. The
letter “R” could be any unused drive letter on the slave
computer. The command “r: \\maine\d password
/user:simucad\george” then links drive "R" on the slave
computer to the drive on the master computer that has the
files for the design, in this example the "D" drive of
computer “maine”. When the slave computer reads and
writes to drive "R", it really is reading and writing to the "D"
drive on the master computer "maine".
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$fs_options
Application Notes:
1)
The combined results from the distributed fault simulation can be obtained from the
Reports/Fault menu selection.
2)
If problems occur when trying to use distributed fault simulation, see the log file for the
master process and for the slave processes. For a batch run, the log file for the master
process can be specified with the “-l” command line argument. The log file for the slave
processes is defined by the "process_name = 'name' " option. For batch distributed fault
simulations, below are some situations that may help you debug the log file:
a)
Symptom: The master process runs fine. However, the slave process is not started
and there is no log file for the slave process.
Solution: The slave process may not be able to locate the HyperFault executable to
run HyperFault. The location of the HyperFault executable for the slave process is
specified by the "process_command = 'command' " option.
b)
Symptom: The master process runs fine. The slave log file only shows the
HyperFault executable starting and the program banner for HyperFault.
Solution: You may have tried to use the Unix “<<” symbol on the command line to
specify standard input as the input for HyperFault. To correct this, use the “-f” option
on the HyperFault command line to specify a command file, i.e.:
hyperflt -f faultdis
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$fs_options
(Application Notes)
2)c) Symptom: The master process runs fine. The slave log file starts HyperFault, inputs all of
the files, and then states there are errors for the “fsim” command and does not run fault
simulation.
Solution 1: Run hyperflt.exe on the slave machine to ensure that it has access to all of
the libraries.
Solution 2: Put a -“!errors” in your command file to view the errors. The problem
may be caused by using the "process_nfs_prefix = 'prefix' " option when the file
system for the master process is already available to the slave process. The solution
for this case would be to remove the "process_nfs_prefix = 'prefix' " option, as it is not
needed.
d)
Symptom: Zero faults are detected.
Solution 1: You may be missing the `timescale in the file that has the $fs_strobe
system task.
Solution 2: The $fs_strobe may be using test nodes that are outside of the $fs_dut
system task, or the test nodes are not connected as a port to the $fs_dut system task.
For an example for distributed fault simulation, see “Example For Distributed Fault Simulation” on
page 3-34.
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$fs_strobe
5.3 Test Nodes ($fs_strobe system task)
The $fs_strobe system task causes the names that are listed as test nodes to be strobed during fault
simulation. Strobing compares the good circuit results with the faulted circuit results.
$fs_strobe ( name, name, ... , name );
$fs_strobe
name of system task for listing the test nodes.
name
one or more wires.
Application Note:
1)
Strobing occurs at the end of the simulation timepoint.
2)
Using the following behavioral code to strobe the test nodes is not recommended:
always @out $fs_strobe(out);
The problem is the always block is only triggered if “out” changes in the reference circuit.
Therefore, when “out” changes in the faulted circuit, the test node may not have been
strobed. Triggering the always block on a signal that is independent of the faulted circuit,
such as a clock, will strobe the test nodes independent of changes in the test nodes for the
faulted circuit:
always @clock $fs_strobe(out);
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$fs_strobe
($fs_strobe)
Examples:
1)
An example for using $fs_strobe in an initial block is shown below. This example creates an
offset of 500 ns, and then strobes test nodes out1 and out2 every 200 ns:
`timescale 1ns / 1ns
module test;
reg clock, b, enable;
wire out1, out2;
notif1_1 x1 (b, enable, out1);
nand2
x2 (clock, b, out2);
initial
begin
#500
forever
#200 $fs_strobe (out1, out2);
end
endmodule
2)
The below example shows test node “test” being strobed every nanosecond:
‘timescale 1ns/1ns
wire test;
always #1
$fs_strobe (test);
3)
The below example shows two $fs_strobe system tasks that happen to use a common test
node “testa”:
reg a, b;
wire out1, out2;
wire testa = a;
wire testb = b;
always @(posedge clock)
$fs_strobe (out1, out2, testa);
always @(enable)
$fs_strobe (testa, testb);
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‘enable_portfaults
‘disable_portfaults
5.4 Port Faults (‘enable_portfaults)
The ‘enable_portfaults compiler directive allows faults to be applied to the ports for modules
suppressed by the ‘suppress_faults compiler directive. The ‘disable_portfaults compiler directive
turns off port faulting for suppressed modules.
‘enable_portfaults
module definitions ...
‘disable_portfaults
‘enable_portfaults
name of compiler directive to enable port faults.
‘disable_portfaults
name of compiler directive to disable port faults (default).
Application Note:
1)
When a ‘suppress_faults compiler directive is placed before a module description, all faults
are suppressed except the port faults at the top level of the module. Port faults of modules
instantiated from within the topmost module are suppressed, unless an ‘enable_portfaults
compiler directive is placed before the module. The ‘enable_portfaults compiler directive
applies that directive to all source (including other files) that is subsequently read in, until a
‘disable_portfaults directive is encountered.
Example:
1)
The below example shows how ‘suppress_faults and ‘enable_portfaults are used with a
library cell:
‘suppress_faults
‘enable_portfaults
module nand2 (in1, in2, out);
input in1, in2;
output out;
nand x2 (out, in1, in2);
endmodule
‘disable_portfaults
‘nosuppress_faults
Hyperfault User's Manual
2001.1xx
System Tasks • 5-18
Simucad Proprietary
‘suppress_faults
‘nosuppress_faults
5.5 Suppressing Faults (‘suppress_faults)
HyperFault suppresses the application of faults on module items that fall within the
‘suppress_faults and ‘nosuppress_faults compiler directives.
‘suppress_faults
module definitions ...
‘nosuppress_faults
‘suppress_faults
name of compiler directive to suppress the application of faults.
‘nosuppress_faults name of compiler directive to allow the application of faults
(default).
Application Notes:
1)
HyperFault deletes all faults between a ‘suppress_faults compiler directive and a
‘nosuppress_faults directive (unless ‘enable_portfaults is encountered).
Example:
1)
The below example shows how ‘suppress_faults and ‘enable_portfaults are used with a
library cell:
‘suppress_faults
‘enable_portfaults
module nand2 (in1, in2, out);
input in1, in2;
output out;
nand x2 (out, in1, in2);
endmodule
‘disable_portfaults
‘nosuppress_faults
Hyperfault User's Manual
2001.1xx
System Tasks • 5-19
Simucad Proprietary
6. Fault Simulation Commands
6.1 Overview
The syntax for the fault simulation commands uses upper case to show keywords, and bolding to
show the minimum syntax for specifying the keyword. Lower case denotes user specified syntax.
Hyperfault User's Manual
Fault Simulation Commands • 6-1
Simucad Proprietary
ACTIVITY
6.2 Activity Report For Nodes
The ACTIVITY command pre-grades the test vectors for fault simulation by reporting nodes that
have no activity (level transitions) during a logic-simulation for the test vectors. The logic
simulation is much faster to run than fault simulation.
The ACTIVITY command can also be used as an HDL code coverage report. This section of the
Activity report lists the number of times that each line of HDL code was executed as specified by
the MXTRAN and MNTRAN keywords.
To obtain a node activity report, enter:
TYPE
STORE
ACTIVITY [t1 TO t2] [ / keywrd=val, keywrd..]
TYPE
STORE
...
optionally directs the activity report to standard output or to a disk file.
ACTIVITY
generates a node activity report.
t1 TO t2
represent the minimum and maximum time point values for reporting node
activity. This time point range must be within the logic simulation time point
range. If the time points are not specified, the logic simulation times are used.
(The TO keyword is optional).
keywrd
represents an optional keyword used to define a condition or specify a value. The
first keyword must be preceded by a slash. Allowed keywords are:
BLOCK
reports the activity only for nodes that are included within fault blocking
(see “Excluding Faults” on page 1-21).
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-2
Simucad Proprietary
ACTIVITY
(Activity Report For Nodes)
(keyword)
MNTRAN=val
specifies the lower limit for reporting node activity. Only nodes which
have known level transitions greater than or equal to this minimum limit
will be reported. (Default: MNTRAN=0)
MXTRAN=val
specifies the upper limit for reporting node activity. Only nodes which
have known level transitions less than or equal to this maximum limit will
be printed. (Default: MXTRAN=0)
val
represents the user-specified numerical value for MNTRAN or MXTRAN.
NOHIST
suppresses output of the activity versus time histogram.
NOSUM
suppresses output of the activity summary.
NOTAB
suppresses output of the node activity table.
Application Notes:
1)
An ACTIVITY report can be very useful for developing input test patterns to detect
circuit faults for fault simulation. The number of level transitions at a node indicates an
input test pattern's effectiveness. Faults at nodes which make no level transitions cannot
be detected.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-3
Simucad Proprietary
ACTIVITY
(Activity Reports For Nodes)
(Application Notes:)
2)
The “t/s ACTIVITY” command can be used to generate the following reports:
An activity table that lists the node names and their number of transitions (changes in
level). The only nodes listed are those whose transition count falls between the minimum
and maximum number of reported transitions specified by the ACTIVITY report
“MNTRAN” and “MXTRAN” values. Registers are not listed, unless they are used to
create an wire that is internal to the HyperFault program, such as a register that is an
input to a gate will create an internal wire for HyperFault that actually drives the gate.
The activity table lists the transition count and the node-name for each node. The
"Legend" for the "Transition Count" column shows that a value is listed when the node
has known (definite) transitions from a high to low or low to high. The value is enclosed
by parenthesis if the node had possible transitions. A "H" is listed if the node toggled
between an unknown level and a high level. A "L" is listed if the node toggled between
an unknown level and a low level. A "U" is listed if the node is always at an unknown
level.
An activity summary that lists totals for the number of nodes at each level of activity
count.
An activity histogram that shows known and potential level transitions versus time.
3)
A “known” (definite) transition is defined as a change from a Low to High level or High to
Low level, even if it goes through an intermediate Unknown level. A “possible” transition is
defined as a change from a High or Low level to the Unknown level or High-Z; or, from the
Unknown level or High-Z back to a High or Low level.
4)
In the activity histogram, the number of known transitions is displayed first for each bar of
the histogram as a column of stars ("*"), and then the number of possible transitions is shown
above the known transitions on each bar as a column of carats ("^"). For example, if the
height of the column of stars for the known transitions on a bar started at zero ended at 100,
then there were 100 known transitions for that bar. If the height of the column of carats for
the number of possible transitions started at 100 and ended at 159, then there were 59
possible transitions for that bar.
Examples:
1) To store the Activity report to a file for nets that do not toggle:
disk foo.out // specify file “foo.out” for the activity report
store activity // write the activity report to file “foo.out”
Hyperfault User's Manual
Fault Simulation Commands • 6-4
Simucad Proprietary
ACTIVITY
(Activity Reports For Nodes)
(Examples:)
2) To store the Activity report to a file to report all of the nets that toggle:
disk test_toggle.out // specify file “test_toggle.out” for the activity report
store activity / mxtran=99 // write the activity report to file “test_toggle.out”
3) The following simple circuit will be used as an example for the activity report:
module foo;
reg in, in_U, in1_0;
wire out_L, out_H, out_U, out1_0;
not (out_L,in); buf (out_H,in); buf (out_U,in_U); buf (out1_0,in1_0);
initial
begin
$display("\t\ttime \tin \tin_U \tin1_0 \tout_L \tout_H \tout_U \tout1_0");
in = 1'bx; in_U = 1'b1;
in1_0 = 1'b1;
#10 in = 1'b1; in_U = 1'bx; in1_0 = 1'bx;
#10 in = 1'bx; in_U = 1'b1; in1_0 = 1'b0;
#10 in1_0 = 1'bx;
#10 in1_0 = 1'b1;
#10 $finish;
end
always @(in or in_U or in1_0 or out_L or out_H or out_U or out1_0 )
$display($time,"\t",in , "\t",in_U , "\t",in1_0 , "\t",out_L ,
"\t",out_H , "\t",out_U , "\t",out1_0);
endmodule
`ifdef silos
!mkeep (foo
// save only the part of the design that is faulted
!control .sav=1
// save only what is specified to be saved (“!mkeep”)
!sim
!activity
// report all signals that do not toggle
!activity / mxtran=99
// report all signals
!error
!exit
`endif
Hyperfault User's Manual
Fault Simulation Commands • 6-5
Simucad Proprietary
ACTIVITY
(Activity Reports For Nodes)
(Examples:)
3) Below is the simulation output for the example:
Simulation Ouput for example on Activity report
!sim
Highest level modules (that have been auto-instantiated):
(foo foo
6 total devices.
Linking ...
8 nets total: 8 saved and 0 monitored.
67 registers total: 67 saved.
Done.
time
in
in_U
in1_0 out_L out_H
0
x
1
1
x
x
10
1
x
x
x
x
10
1
x
x
0
1
20
x
1
0
0
1
20
x
1
0
x
x
30
x
1
x
x
x
30
x
1
x
x
x
40
x
1
1
x
x
40
x
1
1
x
x
out_U
1
1
x
x
1
1
1
1
1
out1_0
1
1
x
x
0
0
x
x
1
26 State changes on observable nets in 0.10 seconds.
260 Events/second.
Simulation stopped at the end of time 50.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-6
Simucad Proprietary
ACTIVITY
(Activity Reports For Nodes)
(Examples:)
3) The below report is for the “!activity” command in the example:
Activity Table for nets that do not toggle
Min Transitions (MNTRAN) 0
Max Transitions (MXTRAN) 0
(
2)
H
(foo(\in<wc>
(
2)
U
(foo(\in_U<wc>
(
2)
H
(foo(out_H
(
2)
L
(foo(out_L
(
2)
U
(foo(out_U
Nets were reported that
did not toggle.
Net “in<wc>” is a net
created by HyperFault to
model input “in” (a
register). The “H” means
that the first transition
was from unknown to
high. The “(2)” means
net “in<wc>” had 2
possible transitions from
unknown to high to
unknown.
The “U” means that the
first transition was from
high to unknown, or low
to unknown. The “(2)”
means net “in_U>” had 2
possible transitions.
The “L” means that the
first transition was from
unknown to low. The
“(2)” means net “out_L”
had 2 possible
transitions.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-7
Simucad Proprietary
ACTIVITY
(Activity Reports For Nodes)
(Examples:)
3) The below report is for the “!activity/mxtran=99” command in the example:
Activity Table for nets that do toggle
Min Transitions (MNTRAN) 0
Max Transitions (MXTRAN) 99
TRANSITION
COUNT
(
(
2)
2)
(
(
(
2)
2)
2)
NODE-NAME
2
(foo(\in1_0<wc>
H
U
2
H
L
U
(foo(\in<wc>
(foo(\in_U<wc>
(foo(out1_0
(foo(out_H
(foo(out_L
(foo(out_U
Hyperfault User's Manual
Nets were reported that
did toggle (mxtran=99).
Net “in1_0<wc>” is a
net created by
HyperFault to model
input “in1_0” (a
register). The “2” means
the net had two
transitions between high
and low levels.
Fault Simulation Commands • 6-8
Simucad Proprietary
FAULTS
6.3 Fault Simulation Report
After fault simulation has been performed, the FAULTS command can be used to generate a report
on the fault simulation.
To generate a fault simulation report, enter:
TYPE
STORE
FAULTS [ / keywrd, keywrd ]
TYPE
STORE
...
(optional) directs the fault summary to standard output
or to a disk file.
FAULTS
generates a fault summary output and histogram. The output will cover the time
period specified on the FSIM command.
keywrd
represents an optional keyword defining the specific type of fault information
desired. The allowed keywords are:
DETECT
Lists a table of all the hard, hypertrophic, and possible detected
faults and the detection time points.
HARD
Lists a table of the hard detected faults and detection time points.
HYTRO
Lists a table of the hypertrophic detected faults and detection
time points.
OSCIL
Lists a table of the oscillating faults and detection time points.
POSS
Lists a table of the possible detected faults and detection time
points.
(continued on next page)
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Fault Simulation Commands • 6-9
Simucad Proprietary
FAULTS
(Fault Simulation Report)
(keywrd
represents an optional keyword defining the specific type of fault information
desired. The allowed keywords are)
SOFT
Lists undetected faults with a non-zero soft detect count (see the
Notes for the FAULTS command).
UNDET
Lists a table of the undetected faults. Undetected faults include
the oscillating faults, and the soft detected faults. The list of
undetected faults can be read back into subsequent fault
simulation runs to fault grade new stimulus (see the Notes for
the FAULTS command).
TOTAL
List the cumulative fault simulation results for iterative fault
simulation (the “fsim/iterate” or “fsim/same-pattern-iterate”
commands). The default for the fault report is to list and
summarize only faults selected in the current run.
HIST
Produces the detection versus time histogram.
SUM
Produces the fault summary.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-10
Simucad Proprietary
FAULTS
(Fault Simulation Report)
Application Notes:
1)
The “t/s FAULTS” command can be used to generate the following reports:
a detailed table of detected and undetected faults that are sorted by the type of fault (i.e.
stuck-low).
a fault summary that provides a table of the number of nodes faulted, the number of hard
detections, possible detections, hypertrophic detections, and undetected faults.
a fault histogram that plots hard, hypertrophic, and possible faults detected versus time.
(continued on next page)
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Fault Simulation Commands • 6-11
Simucad Proprietary
FAULTS
(Fault Simulation Report)
Fault Report
// Output Stuck Low
Type of fault reported.
//(88 faults) resulting in detections:
Number of detected
faults for this type of
fault.
//"!fault/hard hytro poss undet ".
Types of faults for this
listing of the Faults
report.
Output stuck at low
faults to be listed.
.SLOW
+ %time%=5220
"stimulate.dm.G_25_4.T1"
Detected fault at
time=52220 simulation
time units.
+
"stimulate.dm.G_25_4.T2"
Undetected fault.
"stimulate.dm.G_35_n.T1"
Undetected fault with
soft detect count of “4”.
+
%soft%=4
+
%R%=3
+
"stimulate.dm.G_37_n.T1"
"stimulate.dm.G_35_n.T1.1"
The %R% makes the
fault unique if the fault
report is read back into
HyperFault.
The “.1” at the end of the
fault name is added by
HyperFault to show the
port number. The first
port starts with “0”.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-12
Simucad Proprietary
FAULTS
(Fault Simulation Report)
Application Notes:
2)
Hard detects, hypertrophic detects, and possible detects are listed with the same
“%time%=time_value” in the “FAULTS/DET” report. To separate these types of faults use
the report options “hard”, “hytro”, and “poss”. .
3)
Soft detects and oscillating detects are listed with the undetected faults in the
“FAULTS/UNDET” report. Soft detects are denoted with “%soft%=value”, where value is
the number of soft detects. To list the soft detects separately, use the “soft” report option.
4)
All of the fault report options (except for “sum” and “hist”) can be used to store the names of
faults so they can be read in for a subsequent fault simulation. An example to store the
undetected faults so they can be read back in to fault grade a new set of test vectors is:
disk fault.out
// sets the report file name to “fault.out”
store faults / undet // writes the undetected faults to “fault.out”
// to be read back in to HyperFault.
Examples:
FAULT
sto fault /detec
Hyperfault User's Manual
Fault Simulation Commands • 6-13
Simucad Proprietary
FCONTROL
6.4 Fault Simulation Control Parameters
The FCONTROL command enables you to modify the parameters that control fault simulation.
The general format of the FCONTROL command is:
FCONTROL
.CHECKPOINT_INTERVAL=time
.FMEM=val
+
.FBUILDSAVE
.RETRYPOSS=val
+
.FDCSAVE
.HYPERTROPHIC=val%
+
.FITR=val
.NPDET=val
+
.CARRY_POSSIBLE_COUNTS=val
.TRISTATEDET
.UNTESTABLE=val
FCONTROL
command to modify the fault simulation control parameters.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-14
Simucad Proprietary
FCONTROL
(Fault Simulation Control Parameters)
.CHECKPOINT_INTERVAL=time
When this option is specified, HyperFault will update the
fault dictionary file with sufficient information to re-start
the fault simulation run without loss of data from a
crashed run. The fault dictionary file will be updated
every “time” seconds, where “time” is specified on the
“checkpoint_interval” option. When a checkpoint occurs,
HyperFault will write to the standard output window.
An example of using the “checkpoint_interval” option is:
to checkpoint the fault simulation at least every hour,
specify "fcontrol .checkpoint_interval=3600 ". To restart
the fault simulation from the last checkpoint in the event
of a crash, enter the “fsim” command that was used to start
the crashed run, and append “/ recover" to the “fsim”
command. For example:
before crash
to recover
fsim
fsim/recover
fsim 0 10k
fsim 0 10k/recover
fsim/recover
fsim/recover
The option "/recover" causes HyperFault to read the fault
dictionary file, and initialize itself from the crashed run,
instead of starting from scratch. So, in the initial run,
don't use "/recover", or you won't have an initial run, just a
recovered one! Note that in the event of a crash for the
run that is already recovering, you don't have to change
anything.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-15
Simucad Proprietary
FCONTROL
(Fault Simulation Control Parameters)
.CARRY_POSSIBLE_COUNTS=val Soft detect counts are brought forward from prior runs
when "carry_possible_counts=1” is specified (default).
For example, when "fsim/iterate" or “fsim/same-patterniterate” is used, if a stuck low fault on net “out1” has four
soft detects from the previous fault simulation run, then
one soft detect on stuck low fault net “out1” during the
current run would cause it to be a possible detect (if the
possible detect threshold is set to 5).
"carry_possible_counts=0” means possible counts do not
contribute to the next pattern when "fsim/iterate" or
“fsim/same-pattern-iterate” is used.
.FBUILDSAVE
reduces fault simulation time for iterative fault simulation
when the fsim/iterate or the fsim/same-pattern-iterate
command is used. The FBUILDSAVE command may
increase memory usage. To monitor the memory usage
see “Fault Monitor” on page 6-20.
.FDCSAVE
reduces fault simulation time for multiple fault simulation
passes of concurrent faults. The FDCSAVE command
will prevent the re-initializing of the design and the rereading of any SDF files at the beginning of each pass.
The FDCSAVE command may increase memory usage.
To monitor the memory usage see “Fault Monitor” on
page 6-20.
.FITR
changes the maximum iterations during fault simulation.
Stuck-fault oscillations will be reported when an
oscillation occurs or the cumulative iterations for
convergence exceed the iteration limit. Caution should be
used when increasing FITR, as this may mask other
serious problems and can greatly increase execution time
(for more information, see “Oscillations During Fault
Simulation” on page 1-38).
(Default: .FITR=50)
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-16
Simucad Proprietary
FCONTROL
(Fault Simulation Control Parameters)
.FMEM=val
defines the number of concurrent faults simulated for each pass.
When the “$fs_options(“max_memory=value”);” system task is used
(see “Fault Simulation Options ($fs_options system task)” on page 53), the “fcontrol .fmem=val” command limits the number of
concurrent faults per pass to “val”. When the
“$fs_options(“faults_per_pass=n” option is specified it overrides the
“fcontrol .fmem=val” command. Maximum allowed value is 8,000
faults per pass.
(Default: .FMEM=100; Max. Value: .FMEM=8,000)
.HYPERTROPHIC=val
specifies the percentage of the design that the fault affects before the
fault is declared as a hypertrophic detection and dropped (for an
alternative specification, see “hypertrophic=’n’ ” for “Fault
Simulation Options ($fs_options system task)” on page 5-3). For
most fault simulations, relatively few faults cause most of the
memory usage and the run time duration. By assuming that these
faults will be detected and dropping them early in the fault simulation
run, the advantage is to reduce the fault simulation run time and
memory usage. Hypertrophic faults are considered as detected for the
fault monitor (FMON command) report listings of “Total Faults
Detected”, “Actual Detected Faults”, and “Actual Detection Rate”.
Hypertrophic faults appear in the fault report in the “Fault Summary
Table” under the heading "Hypertrophic Detection". In the
specification "hypertrophic=val ", “val” can be an integer number
from 0 to 100 (decimal values will be truncated).
(Default: .HYPERTROPHIC = 5)
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-17
Simucad Proprietary
FCONTROL
(Fault Simulation Control Parameters)
.NPDET
assigns the threshold value for reporting possible detects on a test
node during fault simulation. A “soft” detect occurs at each strobe
time that the test node for the faulted circuit is an unknown level, and
the level for the same test node in the good circuit is low or high, and
only if the test node in the faulted circuit has wiggled (been at low or
high) since the last strobe time. The soft detect count for a fault is
incremented a maximum of 1 at each strobe time, regardless of the
number of test nodes that satisfy this criteria during strobing. When
the number of soft detects equals the threshold limit, the fault is
considered a possible detect and dropped. Setting .NPDET to zero
will turn off possible detect reporting.
(Default: .NPDET=5;
.RETRYPOSS=val
Max. Value: .NPDET=2000000000)
allows possible detects to remain active in the event they become a
hard detect, or they can be re-injected during the “fsim/iterate” or
“fsim/same-pattern-iterate” commands if the fault is among those
currently selected. A value of 0 (default) for “val” means a fault
which becomes a possible detect will be dropped from further
processing. A value of 1 for “val” means a fault which becomes a
possible detect will have the opportunity to become a hard detect by
doing two things:
After being detected as possible, the fault remains active.
During "fsim/iterate" or “fsim/same-pattern-iterate”, a previous
possible detect will be re-injected if the fault is among those
currently selected.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-18
Simucad Proprietary
FCONTROL
(Fault Simulation Control Parameters)
.TRISTATEDET
enables fault detection when a High-Z state is at a test node:
reference circuit test node
faulted circuit test node
status
Z
0 or 1
detected
0 or 1
Z
detected
Z
Z
undetected
.UNTESTABLE
includes untestable faults (faults with no connection to a test node) in the fault
simulation statistics if the value is set to “1”, or excludes them if the value is
set to “0” (default). Note: untestable faults are not simulated, they are
included in the statistics as undetected and appear in the dictionary file as
"UT" faults. The fault monitor report (FMON command) will report the
untestable faults if the “!fcontrol .untestable=1” command is used.
val
represents the numerical value assigned to the control parameter.
Example:
!fcontrol .tristatedet
Hyperfault User's Manual
Fault Simulation Commands • 6-19
Simucad Proprietary
FMON
6.5 Fault Monitor
The FMON command enables you to monitor the progress of fault simulation in the Output
window as the fault simulation executes.
To monitor the fault simulation, enter:
FMON [.DETAIL]
FMON
indicates that the fault simulation is to be monitored.
.DETAIL
optionally lists each fault as it is detected and also lists the oscillating faults. For
each detected fault the memory usage is listed. Below is an example listing of a
detected fault from the FMON .DETAIL command:
hard detect @100
3416 bytes(1696096) .shigh test.u4
where “hard detect” represents a “hard” fault detection has occurred, “@100” is
the time of detection, “3416 bytes” is the amount of memory in bytes used for the
detected fault, “(1696096)” is the total memory used by the fault simulator at the
time of detection, “.shigh” is the type of fault (output stuck at high), and “test.u4”
is the name of the detected fault. See the “Fault Simulation Report” on page 6-9
for a complete summary of fault simulation results.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-20
Simucad Proprietary
FMON
(Fault Monitor)
Application Notes:
1)
The fault monitor displays a summary table that provides the following information for each
type of stuck fault and the total for all faults:
maximum number of possible faults;
number of non-redundant faults;
percentage of random faults to be selected;
number of faults to be simulated.
During fault simulation, the fault monitor also sends messages to standard output to provide
a running summary of the fault simulation progress and detection rate.
2)
After fault simulation completes, the fault monitor report will display two values for the lines
in the Output window that show the “xx% Detection”, “Total Faults Detected”, “Actual
Detected Faults”, and “Actual Detection Rate”. The first value is for the current fault
simulation. When the “fsim/iterate” or the “fsim/same-pattern-iterate” command is used, the
second value is the cumulative total of the present run and the previous run.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-21
Simucad Proprietary
FMON
(Fault Monitor)
Fault Report
// Output Stuck Low
Type of fault reported.
//(88 faults) resulting in detections:
Number of detected
faults for this type of
fault.
//"!fault/hard hytro poss undet ".
Types of faults for this
listing of the Faults
report.
Output stuck at low
faults to be listed.
.SLOW
Detected fault at
time=52220 simulation
time units.
+ %time%=5220
"stimulate.dm.G_25_4.T1"
+
"stimulate.dm.G_25_4.T2"
Undetected fault.
"stimulate.dm.G_35_n.T1"
Undetected fault with
soft detect count of “4”.
+
%soft%=4
Examples:
FMON
!fmon .detail
Hyperfault User's Manual
//use the “!” when entering FMON from a file.
Fault Simulation Commands • 6-22
Simucad Proprietary
FSIM
6.6 Fault Simulation Specification
The FSIM command performs a concurrent fault simulation (for more information, see
“Concurrent Fault Simulation” on page 1-11).
To initiate a fault simulation, enter:
FSIM [ / DICT_ONLY INITIAL=time ITERATE options LIST QUIT
options RECOVER SAME-PATTERN-ITERATE
SEED=seed ]
FSIM
performs the fault simulation. The options available for the "!fsim" command,
e.g. "recover", "quit" etc. can be placed directly on the command line. Any
options on the "!fsim" command itself will be processed first, then options from
the command line are processed. This feature simplifies automatic restart, as it is
not necessary to edit the command file to add "recover" options to a prior "!fsim"
command, i.e.:
"hyperflt +fsim/recover" "hyperflt \"+fsim/quit at 5\" -f faultsim"
DICT_ONLY (optional) specifies that only the faults listed in the dictionary file will be
reprocessed with the “fsim/iterate” and “fsim/same-pattern-iterate” commands.
INITIAL
(optional) specifies the time that faults will be injected. Units can specified for
the time value, such as “10ns” specifies ten nanoseconds. Time dependent fault
injection provides the capability of injecting faults after initialization, or before
the first test vector. When a test is built for a certain area of the chip, the test
often contains initialization vectors necessary to activate the area of the chip
under test. Injecting the faults prior to the initialization may have multiple bad
effects:
The potential for slowing the fault simulation during the initialization.
The potential for false detections during the initialization. Such as, the
initialization period in the test vectors could have a power-up sequence, which
could cause faults to be detected during initialization of the power-up instead
of when simulating the chip itself.
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Fault Simulation Commands • 6-23
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FSIM
(Fault Simulation Specification)
ITERATE
(optional) specifies incremental fault simulation. Incremental fault simulation
provides a cumulative summary of the fault simulation results across more than
one fault simulation run. The “fsim/iterate” command can be used for distributed
fault simulation and for uni-processor fault simulation. When the “fsim/iterate”
command is used, the fault monitor report (fmon command) will display two
values for the many of the items listed by the fault monitor. The first value is for
the current fault simulation. The second value is the cumulative total of the
present run and all previous runs whose results are stored in the fault dictionary
file.
Incremental fault simulation may be used to fault grade the design block by block,
and to fault grade new test vectors against only the undetected faults from
previous fault simulations. This saves time by only running the new stimulus on
the user specified faults, such as all of the undetected faults. The first “fsim”
command will run fault simulation on all of the faults specified by the user.
Subsequent “fsim/iterate” commands will run fault simulation only on the
selected faults from the preceding fault simulations. Note, for distributed fault
simulation, each iterative fault simulation must be run as a separate distributed
fault simulation run. The fault dictionary file will store the information between
the distributed fault simulation runs.
The "!fsim/iterate" command can use the following options to incrementally
update across the types of detected faults. This reduces the run time. Options
available for the “!fsim/iterate” command are:
HARD
Hard detected faults.
HYTRO
Hypertrophic detected faults.
OSCIL
Oscillating faults.
POSS
Possible detected faults.
SOFT
Undetected faults with a non-zero soft detect count.
UNDET
Undetected faults.
An example of using the “fsim/iterate” command is:
!fsim / iterate poss soft undet
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Fault Simulation Commands • 6-24
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FSIM
(Fault Simulation Specification)
(ITERATE) When running incremental fault simulation, the “fsim/iterate” command uses
the below table to update the status of a fault.
New Detection
Hard
Poss
Hytro
Soft
Oscil
Undet
Hard
Hard
Hard
Hard
Hard
Hard
Hard
Poss
Hard
Poss
Poss
Poss
Poss
Poss
Hytro
Hard
Poss
Hytro
Hytro
Hytro
Hytro
Soft
Hard
Poss
Hytro
Soft
Soft
Soft
Oscil
Hard
Poss
Hytro
Soft
Oscil
Oscil
Undet
Hard
Poss
Hytro
Soft
Oscil
Undet
Previous
Detection
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Fault Simulation Commands • 6-25
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FSIM
(Fault Simulation Specification)
SAME-PATTERN-ITERATE
(optional) specifies iterative fault simulation. Iterative fault
simulation replaces the faults selected from a previous run with their new
detection status from the current run. This is useful for determining if a type of
detected fault, such as the hypertrophic faults, would really have been a hard
detect (see “Example for Iterative Fault Simulation” on page 3-31). Normally, the
designer would use incremental fault simulation (see “Example for Incremental
Fault Simulation” on page 3-28 or fsim/iterate command) for accumulating the
fault simulation results for each set of test vectors or each part of the design. The
“fsim/same-pattern-iterate” command is usually not run until after the fault
grading of all the sets of test vectors is completed. The “fsim/same-patterniterate” command can be used for distributed fault simulation and for uniprocessor fault simulation. When the “fsim/same-pattern-iterate” command is
used, the fault monitor report (fmon command) will display two values for the
many of the items listed by the fault monitor. The first value is for the current
fault simulation. The second value is the cumulative total of the present run and
all previous runs whose results are stored in the fault dictionary file.
The “fsim/same-pattern-iterate” option can be used to verify if hypertrophic
detects become hard detects when testing for hypertrophic faults is turned off (set
the $fs_options(“hypertrophic=’100’ ”); system task). Then rerun the fault
simulation with the command “!fsim / same-pattern-iterate hytro”. Options
available for the “!fsim/iterate” command on the types of faults are:
HARD
Hard detected faults.
HYTRO
Hypertrophic detected faults.
OSCIL
Oscillating faults.
POSS
Possible detected faults.
SOFT
Undetected faults with a non-zero possible detect count.
UNDET
Undetected faults.
An example of using the “fsim/same-pattern-iterate” command is:
"!fsim/same-pattern-iterate poss soft undet "
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Fault Simulation Commands • 6-26
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FSIM
(Fault Simulation Specification)
(SAME-PATTERN-ITERATE) When running iterative fault simulation, the “fsim/samepattern-iterate” command uses the below table to update
the status of a fault.
New Detection
Hard
Poss
Hytro
Soft
Oscil
Undet
Hard
Hard
Hard
Hard
Hard
Hard
Hard
Poss
Hard
Poss
Hytro
Soft
Oscil
Undet
Hytro
Hard
Poss
Hytro
Soft
Oscil
Undet
Soft
Hard
Poss
Hytro
Soft
Oscil
Undet
Oscil
Hard
Poss
Hytro
Soft
Oscil
Undet
Undet
Hard
Poss
Hytro
Soft
Oscil
Undet
Previous
Detection
LIST
(optional) writes a list of all possible faults to the fault dictionary file without
running a fault simulation. The “Reports/Fault” menu selection, or the
“fault/undet” report can then be used to list all of the possible faults for the
design.
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Fault Simulation Commands • 6-27
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FSIM
(Fault Simulation Specification)
QUIT
(optional) specifies the time and date that fault simulation will stop and be
restarted. When fault simulation stops, HyperFault will execute the shell
command if there is a shell command after the quit option (possibly to restart the
fault simulation at a later date), and then immediately exit. Any HyperFault
commands that are after the “fsim/quit” command are ignored. The quit option
can be used to run fault simulations at night and on weekends, and stop the fault
simulations during the day so the machines can be used for other purposes.
After a fault simulation has been stopped, it can be restarted by using a shell
command for the appropriate operating system. For example on Unix, if you
wanted to run the fault simulation until 6am, stop, and then restart the fault
simulation at 8pm, you would put the following command (on one line) in the “-f”
file for the fault simulation:
-"!fsim/quit at 6 then \"echo \\"(cd <working_directory> ; ./hyperflt -la
+fsim/recover -f faultsim)\\" | at 8PM\""
The above command will run repeatedly in the evenings between 8PM and 6AM
until the fault simulation is complete. Note the Unix "at" command will send the
User notification of operation by mail. For information on the Unix “at”
command to restart the fault simulation, enter “man at” at the Unix prompt.
As a test, the following line will put the simulator in an infinite loop, running
every minute:
-"!fsim/quit at 1 today then \"echo \\"(cd <work> ; ./hyperflt -la +fsim/recover
-f faultsim)\\" | at now + 1 minute\""
For information on the NT “at” command to restart on NT, from the NT status bar
select “Start/Help/Windows NT Commands / at.
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Fault Simulation Commands • 6-28
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FSIM
(Fault Simulation Specification)
(QUIT)
The QUIT option has the following features:
"!fsim/quit at <hour>"
This will stop fault simulation tomorrow if the hour has
already passed, and today if the hour is still to come.
"!fsim/quit at <hour> today"
This will stop fault simulation at the hour
today, and issue an error message if the hour has
already passed.
"!fsim/quit at <hour> tomorrow"
This will stop fault simulation at the hour
specified on tomorrow.
"!fsim/quit at <hour> on <Month>/<Day>/<Year>"
This will stop fault
simulation at the hour, month, day and year specified.
"!fsim/quit at <hour> then \"<shell command>\""
This will stop fault
simulation at the hour specified, execute any remaining
commands, exit HyperFault, and then issue a shell
command.
The remaining shell command options perform as previously stated:
"!fsim/quit at <hour> today then \"<shell command>\""
"!fsim/quit at <hour> tomorrow then \"<shell command>\""
"!fsim/quit at <hour> on <Month>/<Day>/<Year> then \"<shell command>\""
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Fault Simulation Commands • 6-29
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FSIM
(Fault Simulation Specification)
RECOVER
(optional) specifies that fault simulation will be resumed based on saved
information from a previous run. Fault simulation information is saved at time
intervals specified by the “$fs_options(“checkpoint_interval=time”);” system
task, or when fault simulation completes. If a machine crashes during distributed
fault simulation, the “FSIM/RECOVER” command will only re-simulate the
machine that crashed.
SEED
(optional) redefines the random number seed value. This keyword must be
preceded by a slash (for more information, see “Statistical Fault Simulation” on
page 1-28).
seed
represents a one to nine digit numerical value. This is the “seed” value used to
initiate the random-number sequence. This seed value should be a large odd
number. (Default: SEED=1111111)
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Fault Simulation Commands • 6-30
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FSIM
(Fault Simulation Specification)
Application Notes:
1)
Before fault simulation can be performed, at least one of the commands specifying the type
of faults (VOLOW, VOHIGH, VILOW, VIHIGH, VRESLOW, VRESHIGH, VREISLOW
or VREISHIGH must be specified and at least one $fs_strobe system task must be specified.
2)
Fault simulation can be initiated without a prior logic simulation.
3)
In the Output window, the “FMON” command reports a summary table at the start of fault
simulation and the statistics for fault simulation as it runs. Faults can be reported as they are
detected with the “FMON .DETAIL” command. The .DETAIL option also reports the
memory used by each fault. At the fault simulation's conclusion, the elapsed CPU time is
displayed in the Output window.
4)
Each pass of concurrent faults will cease processing whenever a $stop or a $finish system
task is processed for the reference circuit.
5)
When a fault is detected, the time of detection is recorded and the fault is dropped.
6)
When the iteration limit set by the “FCONTROL .FITR” command has been exceeded for a
fault, the fault is considered as oscillating and is reported as undetected and dropped .
7)
When HyperFault generates “random” faults for statistical fault simulation, it uses a
“pseudo-random” algorithm. That is, the same network with the same fault percentage and
default seed value will always generate the same series of random faults. If you change the
default seed value, the program will generate a different set of random faults. This can
provide a useful check for statistical fault simulation results.
8)
Spike checking is disabled during fault simulation.
9)
Note that only one “fsim / options” command can be used for each distributed fault
simulation run. For example, you can have a distributed fault simulation run that uses either
the “!fsim” command or the “!fsim / iterate” command, but not a distributed fault simulation
run that uses both commands.
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Fault Simulation Commands • 6-31
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FSIM
(Fault Simulation Specification)
Examples:
1)
For the below example, the “!” mark is used to specify the fault simulation command in a
file:
!fsim
2)
For the below example, the “SEED=7777777” changes random sample:
FSIM
/ SEED=7777777
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HyperCov
6.7 HyperCov: Fault Coverage by Blocks
HyperCov reports in tabular format the fault coverage of individual blocks in a design hierarchy.
HyperCov is a separate program from HyperFault, and must be run from the Unix or Windows
system prompt.
One of the advantages of using HyperCov is it reports coverage of design sub-blocks. This can
reveal possible *skewing* in the coverage of the sub-blocks. For example, a HyperFault run may
show 90% coverage for the entire design composed of two blocks, “A” and “B”. However,
HyperCov can be used to reveal that sub-block “A”, containing only 20% of the faults has only
60% coverage while sub-block “B”, containing 80% of the faults, has 98% coverage.
The command line arguments to run HyperCov at the system prompt are:
hypercov [-a | -b | -f ] [-lnn] [-tnnnn] dictionaryFileName [ VerilogPath
[VerilogPath ...] ]
hypercov
name of the HyperCov program. This is entered at the system prompt.
-b
Report fault coverage by blocks. (default) When using the “-b” option,
HyperCov reports the total number of faults in a block, the last timepoint
that a fault was detected, and the hierarchical name of the instance, i.e.:
3@11620
stimulate.dm.G_27_2
HyperCov then provides a fault summary for the faults in the block,
showing the type of fault versus the type of detection (see the example on
the pages that follow).
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Fault Simulation Commands • 6-33
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HyperCov
-f
Report faults ordered alphabetically. Each fault is specified by a line with
the following format:
<Type> <VerilogFaultName> <DetectionType> <Time@DetectNode>
For example:
I1
testfixture.demo.Q0.CK
DS
119000@testfixture.Out0
Where: <Type> is taken from the following table:
"O0"
output stuck low
"O1"
output stuck high
"I0"
input stuck low
"I1"
input stuck high
<VerilogFaultName> is the hierarchical name of the fault.
<DetectionType> is taken from the following table:
"DS"
HARD
"PO"
POSSIBLE
"HY"
HYPERTROPHIC
"OS"
OSCILLATING
"UD"
UNDETECTED
"SO"
SOFT
"UT"
UNTESTABLE
"EQ"
EQUIVALENT
<Time@DetectNode> indicates the time of detection followed by an '@'
character and the verilog name of the detection node. If this field has no
'@' character, it represents the detection count for a soft ("SO") fault
detection. This field is absent for equivalent ("EQ"), untestable ("UT"),
and undetected ("UD") faults. Equivalent faults refer to the first preceding
line specifying a fault whose DetectionType is not "EQ".
-a
Report fault coverage by block (-b) accompanied by faults in the block (-f).
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HyperCov
-lnn
Report <nn> levels of fault coverage from the specified "VerilogPath" or
from the top of the design hierarchy.
-tnnnn
All faults after <nnnn> simulation time are counted as undetected.
DictionaryFileName
The name of the dictionary file written by HyperFault.
VerilogPath
Verilog Hierarchical Name of a block in the design hierarchy (quoted if
name contains blanks). When you specify a module instance name,
HyperCov will report on that instance, and everything below it in the
hierarchy.
Example:
hypercov
-a
faultsim.dictionary
Partial Report from HyperCov for “-a” option
Number of Faults, greastest
detection time, and instance
name for block.
2@820 stimulate.dm.G_26_2_0
Type
Total
Count
%
Hard
Count
%
Possible
Count
%
Hypertrophic
Count
%
Oscillating
Count
%
Undetected
Count
%
SLOW
0
0
0
0
0
0
0
0
0
0
0
0
SHIGH
0
0
0
0
0
0
0
0
0
0
0
0
ISLOW
0
0
0
0
0
0
0
0
0
0
0
0
ISHIGH
2
100
1
50
0
0
0
0
0
0
1
50
TOTAL
2
100
1
50
0
0
0
0
0
0
1
50
I1
stimulate.dm.G_26_2_0.D0
DS
I1
stimulate.dm.G_26_2_0.D3
UD
820@stimulate.vendpepsi
“I1” means input stuck at high fault. The next field is the name of the fault. “DS” means
hard detected fault, “UD” means undetected fault, the “820” is the time of detection, and
the “stimulate.vendpepsi” is the name of the test node that the fault was detected at.
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Fault Simulation Commands • 6-35
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VIHIGH
6.8 Verilog Input-Stuck High Fault Specification
The VIHIGH command is used to specify input-stuck-High faults in Verilog HDL naming syntax
for fault simulation.
Input-stuck High faults are specified as follows:
VIHIGH [.PCT=pct]
VIHIGH [.ALL]
VIHIGH name name name ...
VIHIGH
indicates that input-stuck-High faulted nodes are to be defined.
.PCT
indicates that the percentage value of Stuck-High nodes will be used for fault
simulation.
pct
represents a value from 0.1% to 100% indicating the percentage of nodes that will
be randomly selected to have faults. If a value greater than 90% is specified, the
program will use 100%. The default value is 0%.
.ALL
indicates that all of the inputs are to be faulted. Equivalent to “.PCT=100”.
name
represents the name of a specific node which is to have an input-stuck fault
simulated.
Examples:
!VIHIGH .ALL
!VIHIGH .PCT=20%
!VIHI CNTR1.DFF46.OX3 CNTR1.DFF45.OX3 CNTR1.DFF44.OX3
+ CNTR1.DFF46.OX3 M.4.A2 SET22 BLOCK.REF2.INT11
+ BLOCK.REF3.INT11
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Fault Simulation Commands • 6-36
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VILOW
6.9 Verilog Input-Stuck Low Fault Specification
The VILOW command is used to specify input-stuck-Low faults in Verilog HDL naming syntax
for fault simulation.
Input-stuck at Low faults are specified as follows:
VILOW [.PCT=pct]
VILOW [.ALL]
VILOW name name name ...
VILOW
indicates that input-stuck-Low faulted nodes are to be defined.
.PCT
indicates that the percentage value of stuck-Low nodes will be used for fault
simulation.
pct
represents a value from 0.1% to 100% indicating the percentage of nodes that will
be randomly selected to have faults. If a value greater than 90% is specified, the
program will use 100%. The default value is 0%.
.ALL
indicates that all of the inputs are to be faulted. Equivalent to “.PCT=100”.
name
represents the name of a specific node which is to have an output-stuck fault
simulated.
Examples:
VILOW .ALL
VILOW .PCT=20%
!VIL CNTR1.DFF46.OX3 CNTR1.DFF45.OX3 CNTR1.DFF44.OX3
+ CNTR1.DFF46.OX3 M.4.A2 SET22 BLOCK.REF2.INT11
+ BLOCK.REF3.INT11
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Fault Simulation Commands • 6-37
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VOHIGH
6.10 Verilog Output-Stuck High Fault Specification
The VOHIGH command is used to specify output-stuck-High faults in Verilog HDL naming
syntax for fault simulation.
Output-stuck faults are specified as follows:
VOHIGH [.PCT=pct]
VOHIGH [.ALL]
VOHIGH name name name ...
VOHIGH
indicates that output-stuck-High faulted nodes are to be defined.
.PCT
indicates that the percentage value of Stuck-High nodes will be used for fault
simulation.
pct
represents a value from 0.1% to 100% indicating the percentage of nodes that will
be randomly selected to have faults. If a value greater than 90% is specified, the
program will use 100%. The default value is 0%.
.ALL
indicates that all of the outputs are to be faulted. Equivalent to “.PCT=100”.
name
represents the name of a specific node which is to have an output-stuck fault
simulated.
Examples:
!VOHIGH .ALL
!VOHIGH .PCT=20%
!VOHI CNTR1.DFF46.OX3 CNTR1.DFF45.OX3 CNTR1.DFF44.OX3
+ CNTR1.DFF46.OX3 M.4.A2 SET22 BLOCK.REF2.INT11
+ BLOCK.REF3.INT11
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Fault Simulation Commands • 6-38
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VOLOW
6.11 Verilog Output-Stuck Low Fault Specification
The VOLOW command is used to specify output-stuck-Low faults in Verilog HDL naming syntax
for fault simulation.
Output-stuck faults are specified as follows:
VOLOW [.PCT=pct]
VOLOW [.ALL]
VOLOW name name name ...
VOLOW
indicates that output-stuck-Low faulted nodes are to be defined.
.PCT
indicates that the percentage value of stuck-Low nodes will be used for fault
simulation.
pct
represents a value from 0.1% to 100% indicating the percentage of nodes that will
be randomly selected to have faults. If a value greater than 90% is specified, the
program will use 100%. The default value is 0%.
.ALL
indicates that all of the outputs are to be faulted. Equivalent to “.PCT=100”.
name
represents the name of a specific node which is to have an output-stuck fault
simulated.
Examples:
VOLOW .ALL
VOLOW .PCT=20%
!VOL CNTR1.DFF46.OX3 CNTR1.DFF45.OX3 CNTR1.DFF44.OX3
+ CNTR1.DFF46.OX3 M.4.A2 SET22 BLOCK.REF2.INT11
+ BLOCK.REF3.INT11
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VREISHIGH
6.12 Input-Stuck-At High Fault Specification Using Regular Expressions
The VREISHIGH command uses regular expressions to specify input-stuck-at High faults. Using
regular expressions to name faults lets the user specify any instance in the hierarchy of a design,
and fault only the nets that are at that instance and below.
Input-stuck-at High faults are specified as follows:
VREISHIGH “regular_expression” “regular_expression” ...
VREISHIGH
indicates that “input-stuck-at-High” faults are to be defined by using regular
expressions.
regular_expression
represents a regular expression. For more information on regular
expressions, see “Regular Expressions” on page 1-24.
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Fault Simulation Commands • 6-40
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VREISHIGH
(Input-Stuck-At High Fault Specification Using Regular Expressions)
Example:
test_bench
top_of_design
instance1
instance2
instance3
For the above design, the command to name the input-stuck-at-High faults in instance3 and
below would be:
vreishigh “test_bench\.top_of_design\.instance3\..*”
If the same command was entered from a file it would have to be preceded by an exclamation
mark:
!vreishigh “test_bench\.top_of_design\.instance3\..*”
To enter the same command from a command file, the command would also have to be
enclosed in double quotes and preceded by a minus sign:
-“!vreishigh \”test_bench\.top_of_design\.instance3\..*\” “
For the above design, the command to name the input-stuck-at-High faults in instance1 and
instance3 would specify both regular expressions separated by a space:
vreishigh “test_bench\.top_of_design\.instance1\..*” “test_bench\.top_of_design\.instance3\..*”
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Fault Simulation Commands • 6-41
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VREISLOW
6.13 Input-Stuck-At Low Fault Specification Using Regular Expressions
The VREISLOW command uses regular expressions to specify input-stuck-at Low faults. Using
regular expressions to name faults lets the user specify any instance in the hierarchy of a design,
and fault only the nets that are at that instance and below.
Input-stuck-at Low faults are specified as follows:
VREISLOW “regular_expression” “regular_expression” ...
VREISLOW
indicates that “input-stuck-at-Low” faults are to be defined by using regular
expressions.
regular_expression
represents a regular expression. For more information on regular
expressions, see “Regular Expressions” on page 1-24.
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Fault Simulation Commands • 6-42
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VREISLOW
(Input-Stuck-At Low Fault Specification Using Regular Expressions)
Example:
test_bench
top_of_design
instance1
instance2
instance3
For the above design, the command to name the input-stuck-at-low faults in instance3 and
below would be:
vreislow “test_bench\.top_of_design\.instance3\..*”
If the same command was entered from a file it would have to be preceded by an exclamation
mark:
!vreislow “test_bench\.top_of_design\.instance3\..*”
To enter the same command from a command file, the command would also have to be
enclosed in double quotes and preceded by a minus sign:
-“!vreislow \”test_bench\.top_of_design\.instance3\..*\” “
For the above design, the command to name the input-stuck-at-low faults in instance1 and
instance3 would specify both regular expressions separated by a space:
vreislow “test_bench\.top_of_design\.instance1\..*” “test_bench\.top_of_design\.instance3\..*”
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Simucad Proprietary
VREIXSHIGH
6.14 Excluded Input-Stuck-At High Fault Specification Using Regular Expressions
The VREIXSHIGH command uses regular expressions to exclude input-stuck-at High faults.
Using regular expressions to exclude faults lets the user specify any instance in the hierarchy of a
design, and exclude only the nets that are at that instance and below.
Input-stuck-at High faults are excluded as follows:
VREIXSHIGH “regular_expression” “regular_expression” ...
VREIXSHIGH
indicates that “input-stuck-at-High” faults are to be excluded by using
regular expressions.
regular_expression
represents a regular expression. For more information on regular
expressions, see “Regular Expressions” on page 1-24.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-44
Simucad Proprietary
VREIXSHIGH
(Excluded Input-Stuck-At High Fault Specification Using Regular Expressions)
Example:
test_bench
top_of_design
instance1
instance2
instance3
For the above design, the command to exclude the input-stuck-at-High faults in instance3
and below would be:
vreixshigh “test_bench\.top_of_design\.instance3\..*”
If the same command was entered from a file it would have to be preceded by an exclamation
mark:
!vreixshigh “test_bench\.top_of_design\.instance3\..*”
To enter the same command from a command file, the command would also have to be
enclosed in double quotes and preceded by a minus sign:
-“!vreixshigh \”test_bench\.top_of_design\.instance3\..*\” “
For the above design, the command to exclude the input-stuck-at-High faults in instance1
and instance3 would specify both regular expressions separated by a space:
vreixshigh “test_bench\.top_of_design\.instance1\..*” “test_bench\.top_of_design\.instance3\..*”
Hyperfault User's Manual
Fault Simulation Commands • 6-45
Simucad Proprietary
VREIXSLOW
6.15 Excluded Input-Stuck-At Low Fault Specification Using Regular Expressions
The VREIXSLOW command uses regular expressions to exclude input-stuck-at Low faults. Using
regular expressions to exclude faults lets the user specify any instance in the hierarchy of a design,
and exclude only the nets that are at that instance and below.
Input-stuck-at Low faults are excluded as follows:
VREIXSLOW “regular_expression” “regular_expression” ...
VREIXSLOW
indicates that “input-stuck-at-Low” faults are to be excluded by using
regular expressions.
regular_expression
represents a regular expression. For more information on regular
expressions, see “Regular Expressions” on page 1-24.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-46
Simucad Proprietary
VREIXSLOW
(Excluded Input-Stuck-At Low Fault Specification Using Regular Expressions)
Example:
test_bench
top_of_design
instance1
instance2
instance3
For the above design, the command to exclude the input-stuck-at-low faults in instance3 and
below would be:
vreixslow “test_bench\.top_of_design\.instance3\..*”
If the same command was entered from a file it would have to be preceded by an exclamation
mark:
!vreixslow “test_bench\.top_of_design\.instance3\..*”
To enter the same command from a command file, the command would also have to be
enclosed in double quotes and preceded by a minus sign:
-“!vreixslow \“test_bench\.top_of_design\.instance3\..*\” “
For the above design, the command to exclude the input-stuck-at-low faults in instance1 and
instance3 would specify both regular expressions separated by a space:
vreixslow “test_bench\.top_of_design\.instance1\..*” “test_bench\.top_of_design\.instance3\..*”
Hyperfault User's Manual
Fault Simulation Commands • 6-47
Simucad Proprietary
VRESHIGH
6.16 Output-Stuck-At High Fault Specification Using Regular Expressions
The VRESHIGH command uses regular expressions to specify output-stuck-at High faults. Using
regular expressions to name faults lets the user specify any instance in the hierarchy of a design,
and only fault the nets that are at that instance and below.
Output-stuck-at High faults are specified as follows:
VRESHIGH “regular_expression” “regular_expression” ...
VRESHIGH
indicates that “output-stuck-at-High” faults are to be defined by using
regular expressions.
regular_expression
represents a regular expression. For more information on regular
expressions, see “Regular Expressions” on page 1-24.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-48
Simucad Proprietary
VRESHIGH
(Output-Stuck-At High Fault Specification Regular Expressions)
Example:
test_bench
top_of_design
instance1
instance2
instance3
For the above design, the command to name the output-stuck-at-High faults in instance3 and
below would be:
vreshigh “test_bench\.top_of_design\.instance3\..*”
If the same command was entered from a file it would have to be preceded by an exclamation
mark:
!vreshigh “test_bench\.top_of_design\.instance3\..*”
To enter the same command from a command file, the command would also have to be
enclosed in double quotes and preceded by a minus sign:
-“!vreshigh \“test_bench\.top_of_design\.instance3\..*\” “
For the above design, the command to name the output-stuck-at-high faults in instance1 and
instance3 would specify both regular expressions separated by a space:
vreshigh “test_bench\.top_of_design\.instance1\..*” “test_bench\.top_of_design\.instance3\..*”
Hyperfault User's Manual
Fault Simulation Commands • 6-49
Simucad Proprietary
VRESLOW
6.17 Output-Stuck-At Low Fault Specification Using Regular Expressions
The VRESLOW command uses regular expressions to specify output-stuck-at Low faults. Using
regular expressions to name faults lets the user specify any instance in the hierarchy of a design,
and only fault the nets that are at that instance and below.
Output-stuck-at Low faults are specified as follows:
VRESLOW “regular_expression” “regular_expression” ...
VRESLOW
indicates that “output-stuck-at-Low” faults are to be defined by using
regular expressions.
regular_expression
represents a regular expression. For more information on regular
expressions, see “Regular Expressions” on page 1-24.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-50
Simucad Proprietary
VRESLOW
(Output-Stuck-At Low Fault Specification Using Regular Expressions)
Example:
test_bench
top_of_design
instance1
instance2
instance3
For the above design, the command to name the output-stuck-at-Low faults in instance3 and
below would be:
vreslow “test_bench\.top_of_design\.instance3\..*”
If the same command was entered from a file it would have to be preceded by an exclamation
mark:
!vreslow “test_bench\.top_of_design\.instance3\..*”
To enter the same command from a command file, the command would also have to be
enclosed in double quotes and preceded by a minus sign:
-“!vreslow \“test_bench\.top_of_design\.instance3\..*\” “
For the above design, the command to name the output-stuck-at-low faults in instance1 and
instance3 would specify both regular expressions separated by a space:
vreslow “test_bench\.top_of_design\.instance1\..*” “test_bench\.top_of_design\.instance3\..*”
Hyperfault User's Manual
Fault Simulation Commands • 6-51
Simucad Proprietary
VREXSHIGH
6.18 Excluded Output-Stuck-At High Fault Specification Using Regular Expressions
The VREXSHIGH command uses regular expressions to exclude output-stuck-at High faults.
Using regular expressions to exclude faults lets the user specify any instance in the hierarchy of a
design, and exclude only the nets that are at that instance and below.
Output-stuck-at High faults are excluded as follows:
VREXSHIGH “regular_expression” “regular_expression” ...
VREXSHIGH
indicates that “output-stuck-at-High” faults are to be excluded by using
regular expressions.
regular_expression
represents a regular expression. For more information on regular
expressions, see “Regular Expressions” on page 1-24.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-52
Simucad Proprietary
VREXSHIGH
(Excluded Output-Stuck-At High Fault Specification Using Regular Expressions)
Example:
test_bench
top_of_design
instance1
instance2
instance3
For the above design, the command to exclude the output-stuck-at-High faults in instance3
and below would be:
vrexshigh “test_bench\.top_of_design\.instance3\..*”
If the same command was entered from a file it would have to be preceded by an exclamation
mark:
!vrexshigh “test_bench\.top_of_design\.instance3\..*”
To enter the same command from a command file, the command would also have to be
enclosed in double quotes and preceded by a minus sign:
-“!vrexshigh \“test_bench\.top_of_design\.instance3\..*\” “
For the above design, the command to exclude the output-stuck-at-high faults in instance1
and instance3 would specify both regular expressions separated by a space:
vrexshigh “test_bench\.top_of_design\.instance1\..*” “test_bench\.top_of_design\.instance3\..*”
Hyperfault User's Manual
Fault Simulation Commands • 6-53
Simucad Proprietary
VREXSLOW
6.19 Excluded Output-Stuck-At Low Fault Specification Using Regular Expressions
The VREXSLOW command uses regular expressions to exclude output-stuck-at Low faults.
Using regular expressions to exclude faults lets the user specify any instance in the hierarchy of a
design, and exclude only the nets that are at that instance and below.
Output-stuck-at Low faults are excluded as follows:
VREXSLOW “regular_expression” “regular_expression” ...
VREXSLOW
indicates that “output-stuck-at-Low” faults are to be excluded by using
regular expressions.
regular_expression
represents a regular expression. For more information on regular
expressions, see “Regular Expressions” on page 1-24.
(continued on next page)
Hyperfault User's Manual
Fault Simulation Commands • 6-54
Simucad Proprietary
VREXSLOW
(Excluded Output-Stuck-At Low Fault Specification Using Regular Expressions)
Example:
test_bench
top_of_design
instance1
instance2
instance3
For the above design, the command to exclude the output-stuck-at-low faults in instance3
and below would be:
vrexslow “test_bench\.top_of_design\.instance3\..*”
If the same command was entered from a file it would have to be preceded by an exclamation
mark:
!vrexslow “test_bench\.top_of_design\.instance3\..*”
To enter the same command from a command file, the command would also have to be
enclosed in double quotes and preceded by a minus sign:
-“!vrexslow \“test_bench\.top_of_design\.instance3\..*\” “
For the above design, the command to name the output-stuck-at-low faults in instance1 and
instance3 would specify both regular expressions separated by a space:
vrexslow “test_bench\.top_of_design\.instance1\..*” “test_bench\.top_of_design\.instance3\..*”
Hyperfault User's Manual
Fault Simulation Commands • 6-55
Simucad Proprietary
XILOW / XIHIGH
6.20 Excluded Input-Stuck Fault Specification
The XILOW and XIHIGH commands can be used to exclude input-stuck faults from fault
simulation. These commands are useful for excluding oscillating faults reported during previous
fault simulations (for more information, see “Oscillations During Fault Simulation” on page 1-38).
Excluded input-stuck faults are specified as follows:
XILOW name/input name/input ...
XIHIGH name/input name/input ...
XILOW
indicates that “input-stuck-Low” faults are to be excluded from fault simulation.
XIHIGH
indicates that “input-stuck-High” faults are to be excluded from fault simulation.
name/input
represents a module instance name and its input port name which is to be
excluded from fault simulation.
Application Notes:
1)
When a percentage of input-stuck faults is selected, excluded faults are removed from the
total fault base before the random selection of input-stuck faults is performed.
2)
If a device has more than one input with the same name, all of the named inputs will be
excluded.
Example:
!XIHIGH (GZED(REF2(NOT5/M2A-2 (GZED(REF3(NOT5/M2A-3
+ (GZED(REF4(NOT5/M2A-4
+ (CNTR2(DFF22(G24/(CNTR2(DFF22(L21
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Fault Simulation Commands • 6-56
Simucad Proprietary
XLOW / XHIGH
6.21 Excluded Output-Stuck Fault Specification
The XLOW and XHIGH commands can be used to exclude output-stuck faults from fault
simulation. These commands are useful for excluding oscillating faults reported during previous
fault simulations (for more information, see “Oscillations During Fault Simulation” on page 1-38).
Excluded output-stuck faults are specified as follows:
XLOW name name name ...
XHIGH name name name ...
XLOW
indicates that output-stuck-Low faulted nodes are to be excluded from fault
simulation.
XHIGH
indicates that output-stuck-High faulted nodes are to be excluded from fault
simulation.
name
represents the name of a specific node which is to be excluded from fault
simulation.
Application Note:
1)
When a percentage of output-stuck faults is selected, excluded faults are removed from the
total fault base before the random selection of output-stuck faults is performed.
Examples:
!XHI (CNTR1(DFF46(OX3 (CNTR1(DFF45(OX3 (CNTR1(DFF44(OX3
+ (CNTR1(DFF46(OX3 M.4.A2 SET22 (BLOCK(REF2(INT11
+ (BLOCK(REF3(INT11
Hyperfault User's Manual
Fault Simulation Commands • 6-57
Simucad Proprietary
PLI
7. Verilog HDL Extensions
7.1 HyperFault PLI Interface
HyperFault dynamically interfaces the user written or vendor supplied Programming Language
Interface (PLI) routines with the HyperFault executable at runtime. Interfacing the PLI routines at
run time has the following advantages:
The user does not have to create a new HyperFault executable or have a different executable
for each set of vendor supplied PLI routines.
Dynamically linking the PLI routines at runtime is faster than having to recompile and create
a new executable each time.
Upgrading to new versions of HyperFault is simple because there is no need to recompile and
create a new executable.
7.1.1 HyperFault PLI Interface on the PC
The PLI can be used with HyperFault on Windows NT version 4.0 and greater. Contact Simucad for
an updated list of supported platforms. You may also need a "C" compiler, such as the MS Visual
C++ compiler, to compile any user written PLI routines and to create a “.dll” file to link with
HyperFault. To use PLI on the PC platform:
Create one or more “.dll” files that contain the object code for the PLI. The object code must
have been compiled for the type of platform you are using. For example, object code from
the Sun will not work on the PC.
The HyperFault “pliload” command is used to specify the “.dll” files for HyperFault at
runtime. The “pliload” command is cumulative so that one or more “pliload” commands is
allowed before starting simulation. The “pliload” command can be entered in the Command
window for the Main toolbar, from the HyperFault command line, or from a file.
pliload mypli.dll
example for entering the pliload command
in the Command window for the Main
toolbar.
hyperflt.exe myfile.v -“!pliload mypli.dll” example for entering the pliload command at
the command line.
module foo;
…
endmodule
`ifdef hyperflt
!pliload mypli.dll
`endif
Hyperfault User's Manual
entering the pliload command from a file.
Verilog HDL Extensions • 7-1
Simucad Proprietary
PLI
(HyperFault PLI Interface on the PC)
For more information, see the “README.TXT” file in the PLI subdirectory for the
HyperFault installation.
For an example of using PLI with HyperFault, see file “pli01.spj” in the PLI subdirectory for
the HyperFault installation, or contact Simucad.
7.1.2 HyperFault PLI Interface on the Workstation
The PLI can be used with HyperFault on the Sun and HP workstations supported by HyperFault.
Contact Simucad for an updated list of supported platforms. To use PLI on the workstation:
Create one or more “.so” files that contain the object code for the PLI. For example, to
create a “.so” file on Solaris, enter the following load command.
ld -o mylib.so -dy -G *.o
The HyperFault “pliload” command is used to specify the “.so” files for HyperFault at
runtime. The “pliload” command is cumulative so that one or more “pliload” commands is
allowed before starting simulation. The “pliload” command can be entered at the in the
Command window for the Main toolbar, from the HyperFault command line, or from a file.
pliload mypli.so
example of entering the pliload command at the in the
Command window for the Main toolbar.
hyperflt.exe myfile.v -“!pliload mypli.so” example of entering the pliload command at
the command line.
module foo;
…
endmodule
`ifdef hyperflt
!pliload mypli.so
entering the pliload command from a file.
`endif
For more information, see the “README.TXT” file in the PLI subdirectory for the
HyperFault installation.
For an example of using PLI with HyperFault, see file “pli01.spj” PLI subdirectory for the
HyperFault installation, or contact Simucad.
(continued on next page)
Hyperfault User's Manual
Verilog HDL Extensions • 7-2
Simucad Proprietary
PLI
7.1.3 List of Implemented PLI Routines
The HyperFault Simulation Environment uses the IEEE 1364 “Standard Hardware Description
Language Based on the Verilog Hardware Description Language” manual as the specification for
the PLI. Many of the "tf_" PLI routines for linking user "C" programs to HyperFault have been
implemented. The user "C" programs could be used for modeling a circuit or for creating test
vectors. Selected "acc_" PLI routines have also been implemented. Contact Simucad for the list of
implemented PLI routines.
Hyperfault User's Manual
Verilog HDL Extensions • 7-3
Simucad Proprietary
SDF
7.2 Standard Delay Format
HyperFault supports the Standard Delay File (SDF) format. SDF is a text file that contains the
instance names and delay values necessary to back-annotate delays into a Verilog HDL
description. SDF is usually generated by another tool such as a place and route tool.
The $sdf_annotate system task is used to specify the SDF file (do not input the SDF file). The
format specification for the $sdf_annotate system task is:
$sdf_annotate(“file_name”, module_instance);
where:
file_name
represents any valid file path and file name specification.
module_instance represents the name of the module instance. The hierarchy of this instance is
used for back annotation. The names in the SDF file are relative paths to the
module_instance or full paths with respect to the entire Verilog HDL
description. For example, if you use the module_instance name “top.dff1”
then the instance names in the SDF file are relative to “top.dff1”. If you omit
module_instance, HyperFault uses the module containing the call to the
$sdf_annotate system task as the module_instance for annotation.
When you run the simulation, you will see the following lines in the Output window for
HyperFault that shows the SDF file is read in:
Beginning '$sdf_annotate("file")' into the hierarchy at 'testbench.design'
Done $sdf_annotate.
Where “file” is the name of your SDF file, and “testbench.design” is the hierarchical name of your
design. When errors or warnings occur during readin, there will be an additional message.
Note: If you have selected the “Functional simulation” check box in the “Project Settings” dialog
box for HyperFault, then the back annotation of SDF delays is disabled and the SDF file is not
readin to HyperFault.
For examples on using SDF, see the example on the next page, and see project fltsim.spj (fault
simulation example) in the examples subdirectory for the installation.
(continued on next page)
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Verilog HDL Extensions • 7-4
Simucad Proprietary
SDF
(Standard Delay Format)
For the below example and diagram, if the SDF file contained the following instance name:
(INSTANCE name2.name4)
(DELAY
(ABSOLUTE
(IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420))
then the $sdf_annotate system task to specify the SDF file and its relative position in the design’s
hierarchy would be:
module testbench;
initial $sdf_annotate(“filename.sdf”, testbench.name1);
…
endmodule
When HyperFault reads file “filename.sdf” to update the design, the path “testbench.name1” is
concatenated with path “name2.name4” to form path “testbench.name1.name2.name4”. Signals
“IN0” and “OUT” are then updated as specified in the above example.
Diagram of the Design Hierarchy for the SDF Example
Test bench
module testbench;
Top level of design
design name1(ports);
mod1 name2(ports);
mod2 name4(IN0, OUT);
mod2 name3(ports);
mod1 name5(ports);
SDF file is updating this instance.
Hyperfault User's Manual
Verilog HDL Extensions • 7-5
Simucad Proprietary
Stimulustable
7.3 Expected Values and Stimulustable
The IEEE Verilog specification does not describe any syntax for tabular representation of input
data, nor expected value information. The stimulustable statement is a HyperFault enhancement
which provides tabular format for input data. The stimulustable statement can also combine
expected value information with the tabular format for input data.
7.3.1 BNF
stimulustable <id> ;
table <# delay-expression>? <probe> <,<probe>>* ;
<delay-constant>? <data>+ ;
<delay-constant>? <data>+ ;
.........
endtable
endstimulustable
probe
::= <data-format>? <variable> <(variable)?@ <strobe>>?
if <data-format> is omitted then %h is assumed.
data-format::= %h
||= %o
||= %b
For replacing an existing stimulus table after prep:
stimulustable <id> ;
table <# delay-expression>? ;
<delay-constant>? <data>+ ;
<delay-constant>? <data>+ ;
.........
endtable
endstimulustable
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Verilog HDL Extensions • 7-6
Simucad Proprietary
Stimulustable
7.3.2 Stimulustable
“stimulustable” is a behavioral statement, e.g.
for (i=1; i<=8; i = i+1) // repeat 8 times the input pattern
stimulustable
...
endstimulustable
There is no limit to the number of stimulustable statements. They are not required to be located in
top-level modules. The syntax for the stimulustable keywords must be lower case. Such as, the
keyword "table" must be lower case. Variable names are upper/lower case sensitive.
Any number of input or expected value columns may appear in a stimulustable. Each input column
is identified by a variable which is driven by the data in the column. Each expected value column
is identified by an @ sign. The variable on the left side of an @ sign is verified against the data in
the column. The variable on the right side of the @ sign is used as a strobe. Variables can be a
wire, register, memory element, integer or real variable of any width. They can have any valid
Verilog name.
In the example below for stimulustable s1, register variable in1 and memory element in2 are
driven by the data in the table. Wire out1 is verified against the data in the table whenever the
variable strobe1 is high. To prevent possible race conditions, the rising or the falling edge of the
strobe signal “strobe1” should not coincide with a change in the expected output for “out1”.
!control .ext=stim
`timescale 1ns/100ps
module test;
reg [7:0] in1, in2[1:0];
wire[7:0] out1 = ~in1 | in2[0];
reg strobe1;
initial strobe1 = 0;
always @out1 begin #0.1 strobe1 = 1; #0.1 strobe1 = 0; end
initial
begin
#5;
stimulustable s1;
table #1.2
in1, in2[0],
out1@strobe1;
00 00 ff;
0e 0a f6;
ff ff 00;
endtable
endstimulustable
end
endmodule
Hyperfault User's Manual
Verilog HDL Extensions • 7-7
Simucad Proprietary
Radix
7.3.3 Radix
Data in the table can be in hexadecimal (%h is the default), octal (%o), or binary (%b) for register
data-types, and integer or floating point for integer and real data types. There must be one or more
blank spaces between the radix symbol and the variable name it refers to, such as %h in2. Each
row of values in the table is terminated by a semicolon “;”. Blank spaces and tabs (not carriage
returns) can be used to delineate the values between different variables, however, white space is
not allowed between the values for a vector variable. An example for specifying the radix is
shown below:
table #1.2 %b in1, in2, out@strobe;
00000000 00 ff;
00001110 0a f6;
11111111 ff 00;
For single bit wires, SILOS state symbols may be used to enter states other than 1, 0, x, z. See
“Symbol Modification For Output” on page 8-44.
7.3.4 Delay Time
The delay time for a constant increment of time (delta time) between application of subsequent
table lines can be specified as a single expression:
table #delta .... ;
When the delta delay is specified on the table header, then the first table line is applied
immediately upon execution of the stimulustable statement.
The delay time can also be specified on each table line. When no # sign is specified on the table
header, then the delay values are added to the simulation time as the stimulustable is read. The
delay is applied prior to the application of the table line. The time units for the delay value can be
specified by preceding the module containing the stimulustable statement with a `timescale
statement. Below is an example:
`timescale 1ns / 1ns
#10
table
1.2
1.6
2.1
in1,
00
0e
ff
in2,
00
0a
ff
// time=10
out@strobe;
ff;
// time=11.2
f6;
// time=12.8
00;
// time=14.9
(continued on next page)
Hyperfault User's Manual
Verilog HDL Extensions • 7-8
Simucad Proprietary
Delay Time
(Delay Time)
If two ## signs are specified on the table header, then the delay values are relative to the time the
stimulus table is started (very much like delay values in a fork/join statement). For example:
#10
table
1.2
1.6
2.1
##
00
0e
ff
// time=10
in1, in2, out@strobe;
00 ff;
// time=11.2
0a f6;
// time=11.6
ff
00;
// time=12.1
To have each delay value represent absolute time, start the stimulustable at time=0. For example:
initial begin
stimulustable s1;
table ## in1, in2, out@strobe;
1.2
00 00 ff;
// time=1.2
1.6
0e 0a f6;
// time=1.6
2.1
ff
ff
00;
// time=2.1
Note that mixing of both delay styles in the same stimulus is not allowed.
Hyperfault User's Manual
Verilog HDL Extensions • 7-9
Simucad Proprietary
Memory
7.3.5 Memory Utilization
Data specified in tables is not stored in RAM, so as to reduce memory used when there is a large
pattern.
7.3.6 Strobe
Expected value information is conditioned by a strobe. When the strobe is high, the variable must
agree with the data in the column as follows:
1 <==> 1
0 <==> 0
x <==> don’t care
z <==> High impedance strength (0,1, or x)
The expected value check is engaged when the stimulustable statement begins execution, and
persists through one strobe cycle following the conclusion of the stimulustable statement. During
engagement of the expected value check, a high (positive) strobe is required to check that the
variable agrees with the expected value data. To prevent possible race conditions, the rising or the
falling edge of the strobe signal should not coincide with a change in the expected output signal in
the stimulustable.
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Memory
For example, in stimulustable s1 (shown below) variable strobe1 strobes out1 every 0.2
nanoseconds. This is faster than the input values change (every 1.2 nanoseconds) for variables in1
and in2. When the second entry in the table is executed the calculated value for out1 (f6) does not
equal its expected value. The violation is recorded at the next high pulse for variable strobe1 and
then is not recorded again until after the next entry in the table occurs.
!control .ext=stim
`timescale 1ns/100ps
module test;
reg [7:0] in1, in2[1:0];
wire[7:0] out1 = ~in1 | in2[0];
reg strobe1;
initial strobe1 = 0;
always @out1 begin #0.1 strobe1 = 1; #0.1 strobe1 = 0; end
initial
begin
#5;
stimulustable s1;
table #1.2
in1, in2[0],
out1@strobe1;
00 00 ff;
0e 0a f6;
ff ff 00;
endtable
endstimulustable
end
endmodule
Using the disable statement to disable the block containing the stimulustable statement
immediately terminates expected value checking.
Each expected value column has one strobe, however multiple columns may each have different
strobes.
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I/O Pad
7.3.7 I/O Pad
The stimulustable can be used to model a bi-directional I/O pad. In the example below for
stimulustable s1, variable enable controls the bi-directional I/O pin bi_pad. When enable is high
(1), pin bi_pad acts as an output pin and expected value checking is performed every time strobe1
goes high. The stimulustable also ignores any values in the table for pin “bi_pad” when “enable”
is high. When enable is low (o), pin bi_pad acts as an input pin and the stimulustable applies the
values in the table for pin bi_pad as input stimulus. Expected value checking is ignored for pin
bi_pad when enable is low.
chipside
bi_pad
enable
out
!control .ext=stim
`timescale 1ns/100ps
module test;
wire chipside, bi_pad, enable, out;
buf(chipside, bi_pad);
// buf(out, in);
bufif1(bi_pad, chipside, enable); // bufif1(out, in, enable);
buf(out, chipside);
reg strobe1;
initial strobe1 = 0;
always @bi_pad begin #8 strobe1 = 1; #1 strobe1 = 0; #1; end
initial
begin
#5;
stimulustable s1;
table #10 chipside, enable, out@strobe1, bi_pad(enable)@strobe1;
1 1 1 1; // output cycle
0 1 0 0; // output cycle
1 0 1 1; // input cycle
0 0 0 0; // input cycle
endtable
endstimulustable
end
endmodule
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Expected Value Error
7.3.8 Expected Value Error
Expected value errors trigger a global register named ExpectedValueError. This register is
simultaneously set with specific information about the expected value violated.
The ExpectedValueError variable can be accessed either:
from the data file to cause immediate interaction with the simulation, e.g.
always @ExpectedValueError $stop;
from the $monitor system task or the HyperFault probe command the variable prints a terse
string indicating the stimulus name and column name violated, e.g.
$monitor($time,,ExpectedValueError);
To obtain all violations at a single time-point:
probe iter ExpectedValueError
To obtain time points for which there is at least one violation:
probe ExpectedValueError
Note other variables may simultaneously be probed, e.g.
probe out,,ExpectedValueError
When the ExpectedValueError signal is displayed in the Data Analyzer, the value for the
ExpectedValueError signal is “none” when there is no violation, and “x” when there is a violation.
The “Scan T1 Right” and the “Scan T1 Left” buttons on the Analyzer Toolbar can be used to scan
to expected value violations. If the ExpectedValueError signal shows a series of contiguous
“none” values, then the rising and falling edge of the strobe signal may be coincident with the
changes for the expected value signal in the stimulustable. For example, the rising and falling edge
of the strobe signal “strobe1” does not coincide with expected output signal “out1” in the next
example.
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Expected Value Error
The below example shows how to use the ExpectedValueError variable with $monitor:
!con .ext=stim
//title example with $monitor
`timescale 1ns/100ps
module test;
reg [7:0] in1, in2[1:0];
wire[7:0] out1 = ~in1 | in2[0];
reg strobe1;
initial strobe1 = 0;
always @out1 begin #0.1 strobe1 = 1; #0.1 strobe1 = 0; end
initial
begin
$timeformat(-9,3,"ns",-15);
$monitor("%t",$realtime,, ExpectedValueError);
#5;
stimulustable s1;
table #1.2
in1,
in2[0], out1@strobe1;
00 00 ff;
0e 0a f6;
ff
ff
00;
endtable
endstimulustable
#10 $finish;
end
endmodule
The output from the $monitor is shown below:
6.300ns :s1 out1 fb != f6:
6.400ns
7.500ns :s1 out1 ff != 00:
7.600ns
For the first line:
6.300ns :s1 out1 fb != f6:
The “6.300ns” is the time the difference occurred, the “s1” is the instance name for the
stimulustable, the “fb” is the simulation value for variable “out1”, and the “f6” is the expected
value for “out1”.
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Incremental Update
7.3.9 Expected Value Error Storage
The expected values are stored in variables that use the root name of the variable whose value is
checked with an <expected><number> appended to the name. These variables can be accessed
with the probe or print commands, or viewed in the Data Analyzer.
7.3.10 Incremental Update
“stimulustable” data can be incrementally replaced without having to re-input all the files in the
design. This allows quick iteration of different stimulus/expected-value patterns. The incremental
stimulustables can be specified at any time after preprocessing (the “!prep” command). When
specifying the incremental stimulustables, each incremental stimulustable must be specified outside
of any module, and the variable names can not be put on the table line. The name of the
stimulustable is used to determine which stimulustable is updated.
The file below, “test.v”, shows the top level module with a stimulustable that is simulated until the
“$finish” is encountered:
File “test.v”:
!con .ext=stim
`timescale 1ns/100ps
module main;
reg [8:0] r9;
reg
r1;
initial
begin
stimulustable s1;
table #10 %b r9,
000000000
000010000
111111111
100000001
endtable
endstimulustable
#10 $finish;
end
endmodule
r1;
1;
0;
x;
0;
!sim
`include “test1.v”
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Incremental Update
The next file, “test1.v” shows the new stimulustable values. To simulate the new values, use
`include to input file “test1.v”. Notice that the delta delay value was changed from “#10” for the
first version of stimulustable “s1” to “#20” for the second version of stimulustable “s1”. The
command “!sim 0 2100m” will restart the simulation at time=0 and simulate until the “$finish” in
file test.v:
File “test1.v”:
stimulustable s1;
table #20;
001100000
011010000
111111111
100010001
endtable
endstimulustable
0;
x;
x;
1;
!sim 0 2100m
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Behavioral to Tabular
7.3.11 Changing Behavioral Stimulus to a “stimulustable” Format
Using a stimulustable statement instead of behavioral stimulus has the following advantages:
The stimulustable is input in chunks so it requires less memory.
To change behavioral stimulus to a stimulustable format, you can simulate the behavioral stimulus
with HyperFault and then store the results from the “probe” command as a file of tabular ones and
zeros. The file can then be edited to remove the title for the “probe” command report. Each line of
tabular values in the file must end with a semicolon “;”. To add a semicolon at the end of each
line, put a “;” at the end of the probe state, i.e.:
!store probe in1,,in2,,bi1_,,bi2_,”;”
For example, for file “stimulus.v”:
`timescale 1ns / 100ps
module foo;
reg in1, in2;
reg bi1_, bi2_;
wire bi1 = bi1_; // bi-directional inputs
wire bi2 = bi2_; // bi-directional inputs
initial
begin
in1=0; in2=0;
bi1_=0; bi2_=0;
#10 in1=1; bi1_=1;
#10 bi2_=1'bz;
#10 $finish;
end
endmodule
The following commands would be used from a file to simulate the stimulus:
`include “stimulus.v”
!control .savsim=2
!sim
!disk stim.v
!scope foo
!store probe in1,,in2,,bi1_,,bi2_,”;”
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Behavioral to Tabular
Next, edit file “stim.v” and remove the report header for the probe report and any messages from
the probe report.
Then, include file “stim.v” into a stimulustable statement:
!control .ext=stim
`timescale 1ns / 100ps
module foo;
reg in1, in2;
reg bi1_, bi2_;
wire bi1 = bi1_; // bi-directional inputs
wire bi2 = bi2_; // bi-directional inputs
initial
begin
`timescale 100ps / 100ps // timescale for stimulustable
stimulustable s1;
table ## in1, in2, bi1_, bi2_;
`include “stim.v”
endtable
endstimulustable
`timescale 1ns / 100ps // respecify the circuit’s timescale
#10 $finish;
end
endmodule
When converting behavioral stimulus to tabular stimulus, you need to ensure that timescale for the
tabular stimulus is correct. The units for the time values from the “probe” command are equal to
the smallest resolution for the simulation. This may require a `timescale compiler directive before
the stimulustable statement so that the delay values are scaled correctly. In the above example, the
resolution of the “`timescale 1ns/100ps” compiler directive for the circuit is “100ps”, so a
“`timescale 100ps/100ps” compiler directive must be used before the stimulustable statement.
Notice that the stimulustable for the above example also uses the “##” delay notation, so that the
time values are relative to the time that the stimulustable statement is started.
Notice also that you may need to be careful when applying the stimulus for “inout” (bi-directional)
pins in the circuit. The “inout” pins “bi1” and “bi2” are defined as the left hand side of continuous
assignments. For this circuit, the stimulustable values should be applied to the registers “bi1_” and
“bi2_”. Otherwise, registers “bi1_” and “bi2_” will remain at an Unknown level and will continue
to drive wires “bi1” and “bi2” to an Unknown level due to the continuous assignments.
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HyperFault Extensions
7.4 “hyperflt” and “hse” keywords
HyperFault has reserved keywords “hyperflt” and “hse” that are always true. The “hse” keyword
allows the user to test if the GUI is being used for HyperFault. The “hyperflt” keyword allows the
user to enclose HyperFault specific code or commands within a `ifdef / `else / `endif compiler
directive so that it will be available for HyperFault but not other Verilog simulators, e.g.:
`ifdef hyperflt
initial $stopsave();
initial #1000000 $resetstartsave();
`endif
7.5 Extensions to Turn-off, Reset, and Turn-on Saving
For fault simulation, the simulation history save file is automatically disabled and not used.
However, when running a logic simulation from HyperFault to debug a design, the $stopsave
system task can be used to turn off saving to the save file. This can be used to keep the save file
size fixed during the portion of the simulation that is of no interest for the designer.
The $resetstartsave system task can be used to reset the save file and then start saving the
simulation history. After the simulation is complete, the simulation history that has been saved
after resetting the save file will be available for display with the Data Analyzer.
The below example stops saving at time=0, and starts saving at time=1000000:
`ifdef silos
initial $stopsave();
initial #1000000 $resetstartsave();
`endif
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HyperFault Extensions
7.6 HyperFault Extensions to Verilog HDL
HyperFault has a switch to issue syntax errors for extensions to the IEEE P1364 Standard Verilog
HDL Language Reference Manual. The default setting for the switch is to check for IEEE
compliance. To allow all extensions, enter “!control .ext=all” before inputting your model. The
parameters to allow individual extensions are reported in the syntax error for each extension. On
the pages that follow is a sample list of extensions that will be flagged as syntax errors:
7.6.1 Global Variables:
example:
wire xx;
module ... endmodule
HyperFault command to allow this extension:
!control .ext=gvar
(For more information, see section A.1 of the Verilog HDL Reference on-line help file)
7.6.2 Global tasks and functions:
example:
function
...
endfunction
module
...
endmodule
HyperFault command to allow this extension:
!control .ext=gft
(For more information, see section A.1 of the Verilog HDL Reference on-line help file)
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7.6.3 Functions with multiple outputs:
example:
function xx(in, out2);
input in;
output out2;
HyperFault command to allow this extension:
!control .ext=fmout
(For more information, see section 9.3.1 of the Verilog HDL Reference on-line help file)
7.6.4 Functions without any inputs:
example:
x = funct();
HyperFault command to allow this extension:
!control .ext=fzero
(For more information, see section 9.3.4 of the Verilog HDL Reference on-line help file)
7.6.5 Tasks and functions with ports declared like a module:
example:
task foo(in1,in2);
HyperFault command to allow this extension:
!control .ext=formals
(For more information, see sections 9.2.1 and 9.3.1 of the Verilog HDL Reference on-line
help file)
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HyperFault Extensions
7.6.6 Procedural assignment to wires:
example:
module foo;
wire w;
initial w = 1;
HyperFault command to allow this extension:
!control .ext=paw
(For more information, see section 8.2 of the Verilog HDL Reference on-line help file)
7.6.7 Continuous assignments to register and memory variables:
example:
reg r;
assign r = in;
HyperFault command to allow this extension:
!control .ext=aar
(For more information, see sections 5.1 and 11.1 of the Verilog HDL Reference on-line
help file)
7.6.8 Continuous assignments using intra-assignment/non-blocking delays:
example:
module foo;
wire o, o1;
assign o = #4 i;
assign o1 <= #4 i;
HyperFault command to allow this extension:
!control .ext=assign
(For more information, see section 5.1 of the Verilog HDL Reference on-line help file)
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HyperFault Extensions
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7.6.9 Default state value for UDP:
The "default" keyword for the UDP specifies the state value for the UDP's output when UDP input
levels and transitions do not match any of the entries in the UDP table. When the "default"
keyword is not used, the UDP default output state is "x".
example:
primitive udp1 (out, in);
output out;
input in;
table
// in out
0 : 1;
default: 0;
endtable
endprimitive
HyperFault command to allow this extension:
!control .ext=udpdefault
(For more information, see section 7.1 of the Verilog HDL Reference on-line help file)
7.6.10 UDP additional states for High-Z on inputs or output:
example:
for row states other than “0,x,1”, such as:
Z : 1;
<?HV> : 1;
HyperFault command to allow this extension:
!control .ext=udpstate
(For more information, see section 7.1 of the Verilog HDL Reference on-line help file)
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HyperFault Extensions
7.6.11 UDP edge for High-Z:
example:
for edges to High-Z, such as
(0Z) : 1;
HyperFault command to allow this extension:
!control .ext=udpstate
(For more information, see section 7.1 of the Verilog HDL Reference on-line help file)
7.6.12 UDP Multiple Edges in a Row:
example:
(01) (01): 1;
HyperFault command to allow this extension:
!control .ext=udpstate
(For more information, see section 7.5 of the Verilog HDL Reference on-line help file)
7.6.13 Non-Constant Specify Block Delays:
example:
for non-constant specify block delay, such as
(in => out) = delay_var;
HyperFault command to allow this extension:
!control .ext=ncsd
(For more information, see section 13.1 of the Verilog HDL Reference on-line help file)
7.6.14 Parameter for Specify Block Delays:
example:
for parameter used for specify block delay, such as
parameter dly=8
(in => out) = dly;
HyperFault command to allow this extension:
!control .ext=psd
(For more information, see section 13.1 of the Verilog HDL Reference on-line help file)
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HyperFault Extensions
(HyperFault Extensions to Verilog HDL)
7.6.15 Stimulustable Extension:
example:
for using the stimulustable statement, such as
stimulustable ... endstimulustable statement
HyperFault command to allow this extension:
!control .ext=stim
7.6.16 “input/output/inout” declarations after the variable's declaration:
example:
module foo (in);
wire in;
input in;
HyperFault command to allow this extension:
!control .ext=inout
(For more information, see section 12.1 of the Verilog HDL Reference on-line help file)
7.6.17 Using registers as module inputs:
example:
module xx(in);
input in;
reg in;”
HyperFault command to allow this extension:
!control .ext=rsink
(For more information, see section 12.4.6 of the Verilog HDL Reference on-line help file)
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HyperFault Extensions
(HyperFault Extensions to Verilog HDL)
7.6.18 Duplicate variable definitions:
example:
module foo;
wire a;
wire a;
HyperFault command to allow this extension:
!control .ext=dvd
(For more information, see section 3.1 of the Verilog HDL Reference on-line help file)
7.6.19 Parameter used for sizing numbers:
example:
module foo;
reg[7:0] xx;
parameter size=8;
initial
xx = size'b010;
HyperFault command to allow this extension:
!control .ext=psize
(For more information, see section 2.3 of the Verilog HDL Reference on-line help file)
7.6.20 Null statements:
example:
module foo;
initial
begin ;
HyperFault command to allow this extension:
!control .ext=nstmt
(For more information, see sections 8.7.1 of the Verilog HDL Reference on-line help file)
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HyperFault Extensions
(HyperFault Extensions to Verilog HDL)
7.6.21 Timing checks without edge specifications for selected variables:
example:
$recovery( CLR, ...
HyperFault command to allow this extension:
!control .ext=neref
(For more information, see section B.9.6 of the Verilog HDL Reference on-line help file)
7.6.22 More precision in “$timeformat” than “`timescale”:
HyperFault command to allow this extension:
!control .ext=tfmt
(For more information, see section B.5.2 of the Verilog HDL Reference on-line help file)
7.6.23 Missing port connections are set to ground for VCS compatibility:
HyperFault command to allow this extension:
!control .skip=.gnd
Note: Wires which are otherwise floating still remain HiZ, regardless of "!control .skip".
7.6.24 VCS compatibility extension for comma at the end of the port list, i.e.: module (xx(a,):
HyperFault command to allow this extension:
!control .ext=portcomma
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8. Additional Commands
8.1 Command Syntax
Usually, only the first two characters are required when specifying a command. A few commands
(e.g. FAN, PRE, PRO) require three letters to prevent ambiguity.
8.2 Stopping Processes
To discontinue or stop an interactive process when running HyperFault, such as during a large
report that is output to the terminal, enter:
•
“Ctrl-C”: simultaneously hold down the “Ctrl” key and the “C” key on the keyboard for the
Unix command-line version of HyperFault.
•
“Esc” key on the keyboard for all Windows versions.
•
“STOP” button on Toolbar for all Windows versions.
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Commands In Files
8.3 Commands in Files
HyperFault commands can be entered at the “Ready:” prompt or from a file. Commands entered
from a file must be directly preceded (without any white space) by a “!” or a “.”. Preceding a
command by “!” will cause the command to be echoed to standard output as it is executed.
Usually, only the first two characters are required when specifying a command. A few commands
(e.g. PRE, PRO) require three letters to prevent ambiguity.
An example of is shown below. For this example, file “test.v” will automatically simulate to the
$finish and report any error messages. Enclosing HyperFault commands with a “ ‘ifdef hyperflt”
compiler directive allows you to maintain Verilog compatibility (the keyword “hyperflt” is defined
as true by default in HyperFault).
File “test.v”:
//title simple circuit
module foo;
reg clock;
initial
begin
clock = 0;
#10 clock = 1;
#10 $finish;
end
endmodule
‘ifdef hyperflt
!sim
!errors
‘endif
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Commands In Files
Commands are executed immediately upon being encountered in the data. Therefore, the order in
which the commands are placed may be important (e.g., !PREP before !SIM ).
You should use the ‘include compiler directive when inputting a file from another file. In the
previous example, remove the HyperFault commands from the file “test.v” and put them in file
“test1.v” (shown below) with an ‘include compiler directive to include file “test.v” (for additional
information see ‘include in the Verilog HDL Reference on-line help file).
File “test1.v”
‘include “test.v”
‘ifdef hyperflt
!sim 200
!errors
‘endif
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Command-line Options
8.4 Command-line Options
You can use Verilog style command line arguments for HyperFault. The command line arguments
can be entered from the Command Line Arguments box in the Project Settings dialog box (see
“Project Settings Menu Selection” on page 4-15), or, from the command line if you are running a
batch simulation. Available command line arguments are:
-c: This option compiles the source files and then exits.
-f file_name: This option instructs HyperFault to get the command line arguments from
a file. HyperFault has the ability to nest the command files. For example, command file
“logicsim”,
hyperflt -f logicsim
could contain the name of another command file “logicsim1” that has additional “-“
command line arguments.
HyperFault style commands can be entered in a command file by enclosing the command
with double quotes -“!hyperfault_command”, i.e. -“!control .sav=2”.
-k file_name: This option saves the text that has been entered from standard input to a
file.
-l file_name: This option writes the standard output from HyperFault to a log file and
also to standard output. An “exit” or “quit” command must be encountered for
HyperFault to terminate.
-la : This option appends the standard output from HyperFault to a log file instead of
over writing the log file, and also to standard output. This option must appear before the
"-l <fn>" option.
-r save_file_name: This option restores HyperFault to the last saved logic simulation
state from a previous HyperFault save command.
-s: This option causes HyperFault to enter the interactive mode after executing any
commands that have been input to HyperFault.
-u : This option converts every name to upper case.
-v file_name: This option specifies a library file name.
-w : Specifying -w means that HyperFault will not display any warning messages.
-y directory_path: This option specifies a directory of library files.
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Command-line Options
+libext+extension1+extension2…: This option names the file name extensions for
library files in the directory specified by the “-y” option. An example of specifying the
library path and extension would be:
-y c:\silos3\examples\library +libext+.v
+libnonamehide: This option causes HyperFault to read in the module and UDP
definition names as they are written in the file without appending character strings.
+librescan: Search all the library files again for undefined modules.
+libverbose: This option prints information about the opening of files and the resolution
of module and UDP definitions during the scanning of libraries.
+define+text_macro_name=macro_text : This option allows you to specify `define
macros from the command line. The “text_macro_name” is the macro identifier, and the
“macro_text” is the text substitution. Double quotes (“ ”) must be used around the
macro_text if the macro_text contains whitespace. For example:
hyperflt.exe +define+sdf=test.sdf
is equivalent to:
`define sdf test.sdf
and:
hyperflt.exe +define+declare=“reg a;”
is equivalent to:
`define declare reg a;
+delay_mode_distributed command line argument specifies the distributed delay mode
for all modules in the source description. This means that the distributed delays for gates
connecting the module input to the module output will always be used as the pin-to-pin
delay for the module input to output. For examples of distributed delays, see Chapter 13
on specify blocks in the Verilog LRM on-line help file.
+delay_mode_path command line argument specifies the path delay mode for all
modules in the source description. This means that the path delays specified in the
specify blocks for delays from the module input to the module output will always be used
as the pin-to-pin delay for the module input to output. For examples of path delays, see
Chapter 13 on specify blocks in the Verilog LRM on-line help file.
+delay_mode_unit command line argument sets all gate and specify block delays to one.
+delay_mode_zero command line argument sets all gate and specify block delays to zero.
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Additional Commands • 8-5
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Command-line Options
+fault_vcd: This option activates the Value Change Dump (VCD) feature for fault
simulation. The vcd file is created during the 1st pass.
+incdir+directory1+directory2…: If HyperFault can not find a file name that is specified
on the user’s `include in the current directory, then HyperFault will search the directories
specified by the +incdir command line option for the file.
•
+ignore_sdf_interconnect_delay: specifies that SDF INTERCONNECT delays will not
be used. This can be useful for reducing the runtime and memory usage for fault
simulation.
•
+ignore_sdf_port_delay: specifies that SDF PORT delays will not be used. This can be
useful for reducing the runtime and memory usage for fault simulation.
+mindelays: This option selects the minimum delay specification for delays
(min:typ:max).
+typdelays: This option selects the typical delay specification for delays (min:typ:max).
(Default: +typdelays)
+maxdelays: This option selects the maximum delay specification for delays
(min:typ:max).
•
+no_default_variables: This option issues an error message when a variable is used
without first specifying the type of variable that it is. Since "wire" is the default type for
variables, this assists the user with finding variables that were automatically set to wire
where a register was intended..
+nodoldisplay: This option suppresses all messages from $display, $write, etc. system
tasks to standard output. This can be used to prevent these messages from cluttering the
log file during fault simulation.
+nolibfaults: Automatically inserts `suppress_faults and `enable_portfaults, and
`nosuppress_faults and `disable_portfaults around every module in a library file. The
library file can be specified using the -y and -v command line options, the !library
command, or the "Project Files" dialog box.
+no_pulse_msg: The command line option “+no_pulse_msg” turns off the +pulse
messages. This does the same thing as the “+pulse_quiet” command line option.
+notimingchecks: This option disables all timing checks, improving speed and reducing
memory used.
+no_tchk_msg: This option suppresses timing check violation messages. Timing checks
are still processed, but no messages are printed to standard output if there is a timing
check violation.
+nowarntfmpc: This option suppresses the warning message for a mismatch in the
number of port connections.
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Additional Commands • 8-6
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Command-line Options
+plusargs: You can enter “+” command-line arguments that are project specific, such
“+compare”, “+sdf”, .etc. For example, suppose you wanted to specify the SDF file only
when you entered “+sdf” from the command line. Then your test bench may look like:
module test_bench;
initial
if ( $test$plusargs( “sdf”))
$sdf_annotate(“test.sdf”);
endmodule
// only execute if “+sdf” is an argument
+pulse_r/<n> and +pulse_e<n> command line arguments specify a range of pulse widths
that will propagate to the path destination. For +pulse_r<n>, “n” specifies a number in
the range 0-100. This will reject any pulse whose width is less than “n” percent of the
module path delay. For +pulse_e/<n>, “n” specifies a number in the range 0-100. This
will flag as an error and drive unknown (“x”) any path pulse whose width is less than “n”
percent of the module path delay, but whose width is greater than pulse_r. For more
information, see PATHPULSE$ in the IEEE 1364 Verilog HDL manual.
+pulse_quiet command line argument suppresses warning messages generated by pulse_e
command line argument.
+suppressredef: This option will suppress the warning message for redefinition of
`define macros.
+suppressfloat: This option will suppress the warning message for floating nodes, which
may be caused by a gate input not having a driver, or by declaring a variable as a wire
and then never assigning a value to it.
•
+timing_checks: This option turns on all timing checks for fault simulation. This will
slow down the fault simulation and increase the memory used by fault simulation.
•
+width_mismatches: This option will issue a warning message if the widths for variables
in an expression or assignment are inconsistent, i.e.: .
wire [3:0] a4;
wire [2:0] a2;
assign a4 = a2 & a4; // caught
assign a4 = a2;
// caught
assign a4 = a2 & a2; // caught
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Additional Commands • 8-7
Simucad Proprietary
Command-line Options
+xl_order specifies a switch so that the order of evaluation for always blocks is the same
order as for Verilog-XL. This switch may be useful for obtaining the same simulation
results as Verilog-XL. This option must be parsed before any modules are parsed. This
option automatically enters "`define xl_order 1". An example would be the order of
evaluation for:
always @posedge clock …..
always @posedge clock …..
HyperFault also supports the following command-line option:.
-nospec
The -nospec command-line option eliminates all specify blocks. Eliminating the specify blocks
will reduce the memory used and increase the simulation speed. However, eliminating the specify
block delays may cause race conditions and non-convergence due to zero delays. If this happens,
the rise and fall delays for all gates (whose delays are not explicitly specified) can be set to "1"
with the following HyperFault command:
-“!delay .default =1,1”
HyperFault also allows system commands to be entered from the command line, i.e. -"!system \"ls
-lt\""
For library searching, HyperFault also supports the `uselib compiler directive. The format for
`uselib is:
`uselib file=filename dir=directory_name
where:
filename is the full path name for a file containing one or more module definitions that are
searched to complete unresolved instantiations.
directory_name is the full path name for a directory of files whose names are a concatenation
of the name of a module definition and a file extension, such as “dff.v”.
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Additional Commands • 8-8
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Command-line Options
Some examples of `uselib are:
The below example uses `define to specify macros for the `uselib. This makes it easier to
change the library paths.
`define asic1 dir=c:\actel\lib\vlog libext=.v
`define asic2 file=d:\library\udp.v
`uselib `asic1 `asic2
The below example uses specifies the same `uselib without using a `define. Notice that the
“libext” keyword for the library file name extensions is required when specifying a directory
“dir” specification for a directory of library files.
`uselib file=\test\lib\udp.v dir=\test\lib2 libext=.v
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Additional Commands • 8-9
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BUSCON
8.5 Bus Contention Report
The BUSCON command reports the logic simulation time points at which more than one “tri”,
“triand”, “trior”, “trireg”, “tri0”, or “tri1” net type, or an enabled unidirectional device (“bufif1”,
“bufif0”, “notif1”, “notif0”, “nmos”, “pmos”, “rnmos”, and “rpmos” devices) are simultaneously
driving a node (a bus contention).
To obtain a bus contention report, enter:
TYPE
STORE
BUSCON [ t1 TO t2 ]
TYPE
STORE
...
(optional) directs the bus contention report to standard output,
or to a disk file.
BUSCON
generates a summary table of any contentions that have occurred between two
time points.
t1 TO t2
represent the minimum and maximum time point values over which contention is
to be checked. These time values must be within the logic simulation time point
range. If not specified, the simulation time points will be used. The keyword
“TO” is optional.
Application Notes:
1)
Contentions are reported only for nodes where two or more enabled unidirectional devices,
or “tri”, “triand”, “trior”, “trireg”, “tri0”, and “tri1” net types, form a wired connection (often
used to form a bus). Bi-directional transistors, non-enabled gates and gates without enable
lines are ignored by the BUSCON report.
2)
For each contention, the BUSCON command reports the starting and ending time points, the
starting and ending node states, and the names of the enabled unidirectional devices or “tri”,
“triand”, “trior”, “trireg”, “tri0”, and “tri1” net types connected to the node.
(continued on next page)
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Additional Commands • 8-10
Simucad Proprietary
BUSCON
(Bus Contention Report)
Examples:
TYPE BUSCON 2K 100K
nst busco
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Additional Commands • 8-11
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CHGLIB
8.6 Encrypting Library Files
The CHGLIB command changes files of Verilog HDL modules and HyperFault macro definitions
from sequential access libraries to random access libraries. The CHGLIB command can also be
used to encrypt and secure library files.
CHGLIB [ / ENCRYPT] [ / SECURE=feature] [ / NODEMOLIMIT] output_file infile1 ...
CHGLIB
converts or encrypts library files to random access.
ENCRYPT
the resulting library file is unreadable except by the HyperFault program.
Readable comments can be added by editing the encrypted library file before the
first “#” character. Use of this option is controlled by a security license feature
issued by Simucad.
SECURE=feature
the resulting library file is unreadable except by the HYPERFAULT
program. When HYPERFAULT attempts to access the resulting library file, the
user must have the “feature” listed in the license file “silos.lic” for
HYPERFAULT. The “SECURE” option does not require the “ENCRYPT”
option to encrypt the file. The “SECURE” option can also be used with the
“NODEMOLIMIT” option.
NODEMOLIMIT the resulting library file is unreadable except by the HYPERFAULT program.
This is a special option that allows the demo version of HYPERFAULT to read a
library file of more than 200 gates. Use of this option is controlled by a security
license feature issued by Simucad.
output_file
name of the output library file to be created by the CHGLIB command.
infile1 ...
name(s) of one or more input files to be converted to random access and
encrypted.
Application Note:
1)
Using the CHGLIB command will not necessarily result in a increase in speed, as
HYPERFAULT automatically indexes a library file that is sequential access the first time it
is used.
Examples:
chglib cmos12.lib cmos12.dat cmos13.dat cmos14.dat
chglib /encode chip.library chip.dat
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Additional Commands • 8-12
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CONTROL
8.7 Control Parameters For Logic Simulation
The “CONTROL” command enables you to modify the parameters that control logic simulation.
The general format of the CONTROL command is:
CONTROL
+
+
+
+
+
.COMMENT=c
.DISABLECACHE
.EUNK=val
.NONCON
.SAVSIM=val
.TPS=qual
.CUSTREPORT
.DMIN
.MXITR=val
.RECIRCULATE
.SKIP=val
.XL_ORDER=val
.DISK=val
.DMAX
.MXDCI=val
.SAVCELL=val
.SYNONYM=val
val
represents the numerical value assigned to the control parameter.
c
represents a single character.
string
represents the prompt string.
CONTROL
indicates that the default simulation control parameters are to be modified.
.COMMENT
specifies the comment character. (Default: .COMMENT=$)
.CUSTREPORT specifies that the save-file will be used in a Custom Report. (Default: not
specified)
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CONTROL
(Control Parameters For Logic Simulation)
.DISABLECACHE turns off the caching mechanism for the Data Analyzer. Turning off the
caching may reduce the RAM memory used by HyperFault, however, it may
make the Data Analyzer slower. The cache is used to “remember” in RAM
memory the simulation data that you have viewed with the Data Analyzer. For
example, if you do a zoom full, then every change for the displayed signals is
stored in memory. If you then zoom in or zoom out for these signals, the redraw
time is much faster. If you add additional signals to the Data Analyzer, then the
logic simulation data for the new signals has to be read from the logic simulation
history save file on disk.
.DISK
assigns the approximate limit of disk storage in bytes that the logic simulation
save-file can use. When the disk storage limit is exceeded, the logic simulation
will terminate (see note 1). (Default: .DISK=100M)
.DMAX
specifies that the maximum delay value will be used when parsing the netlist (see
notes 2 and 3).
.DMIN
specifies that the minimum delay value will be used when parsing the netlist (see
notes 2 and 3).
.EUNK
defines the conductance for bi-directional transistors and unidirectional transfer
gates when there is an Unknown level on the enable: “on” when .EUNK=1, “off”
when .EUNK=0 or “Unknown” when .EUNK=*. (See note 4) (Default:
.EUNK=*)
.NONCON
when nonconvergence is detected, the default is for HyperFault to issue a warning
message, pick a possible solution if this is possible, and continue simulation. If
the “CONTROL .NONCON” command is entered before logic initialization
begins, then if nonconvergence is detected, HyperFault will issue an error
message and stop the logic simulation.
.MXDCI
assigns the maximum allowed iterations for each pass during LINIT. (See note 5)
(Maximum: .MXDCI=9999) (Default: .MXDCI=100)
.MXITR
assigns the iteration limit to reach convergence for each logic simulation time
point. (See note 5) (Maximum: .MXITR=999) (Default: .MXITR=300)
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CONTROL
(Control Parameters For Logic Simulation)
.RECIRCULATE=val
this option specifies the maximum time interval for saving the
simulation history results. When the simulation time exceeds this interval, the
new simulation results are saved and the earliest simulation results are discarded
so that the save file interval and file size on disk stay relatively constant, very
much like a FIFO. The interval can be specified in time units, such as “100ns” for
100 nanoseconds, i.e: !control .recirculate=100ns.
.SAVCELL
Causes HyperFault to not save (“.SAVCELL=0”) or to save (“.SAVCELL=1”)
the logic simulation history for variables listed between the ‘celldefine and
‘endcelldefine compiler directives. Caution: Saving all variables between
‘celldefine and ‘endcelldefine compiler directives may slow down logic
simulation and create larger save files on disk. (Default: .SAVCELL=0)
.SAVSIM
sets the logic simulation save option to determine which simulation node state
changes are saved on the “SAVE” disk file. The .savsim option must be specified
before logic simulation begins. (Default: .SAVSIM=0)
.SAVSIM=0
specifies that no simulation node values are to be saved. This has
limited use, as no data is available.
.SAVSIM=1
specifies that node simulation values (logic-type, integer-type
and double-type) are to be saved only for nodes named in the
TABLE, PLOT, GNAME, TESTER, KEEP, MKEEP, HEX and
OCT commands. Output results can be obtained only for the
saved nodes. This option decreases simulation disk file size and
reduces execution time.
.SAVSIM=2
specifies that all logic-type simulation node states are to be saved
for all nodes in the circuit. This option prevents saving integer
and floating-point values.
.SAVSIM=3
specifies that all (logic-type, integer-type and double-type)
simulation node values are to be saved. Output values can be
retrieved for any network node.
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Additional Commands • 8-15
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CONTROL
(Control Parameters For Logic Simulation)
.SYNONYM
Causes HyperFault to retain the hierarchical node names (synonyms) in addition
to the “real” node name for the upper-most level that the node is connected to in
the hierarchy. When all synonyms are saved, HyperFault will recognize the
hierarchical name as well as the “real” name to each node in the design. Caution:
Saving all synonyms may slow down input parsing and memory usage may go up.
(Default: .SYNONYM=1)
.SYNONYM=0
don’t save synonyms.
.SYNONYM=1
save all synonyms.
.SKIP
Causes HYPERFAULT to set a skipped port to a level. The default level is HighZ unknown. An allowed level is ground for compatibility with VCS (!control
.skip=.gnd). . (Default: .SKIP=.gnd)
.TPS
specifies the default command for redirecting report outputs to standard output or
disk file. Allowed qualifiers are: TYPE, STORE.
.XL_ORDER=val specifies a switch so that the order of evaluation for always blocks is the same
order as for Verilog-XL, where “val” is “1” for “xl_order” being “on” (the same
as Verilog-XL) and “0” for xl_order being “off” (default). This switch may be
useful for obtaining the same simulation results as Verilog-XL. This option must
be parsed before any modules are parsed. An example would be the order of
evaluation for:
always @posedge clock …..
always @posedge clock …..
Application Notes:
1)
When the disk storage limit (set by “.CONTROL .DISK”) is exceeded during logic
simulation, the simulation will stop. A message will be displayed showing the last
simulation time point. To continue the simulation, you can increase the disk limit and reenter the “SIMULATE” command. Another method would be to report the simulation
results, enter “RESET SAVFILE” to clear the disk file “save.sim” (saves the simulation
history) and then continue from the last simulation time point. “RESET ERRORS” must be
entered before continuing the simulation.
(continued on next page)
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Additional Commands • 8-16
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CONTROL
(Application Notes:)
2)
.DMAX and .DMIN will not both affect the same simulation. The one that is specified last
will remain in effect for all netlist parsing and subsequent SIMULATE commands. The
.DMAX or .DMIN scaling factor should be specified before inputting the netlist so that the
netlist is parsed correctly.
3)
The .DMIN or .DMAX scaling factor that is in effect during logic simulation will scale the
delay times during subsequent fault simulations.
4)
If “.CONTROL .EUNK=*” has been defined and there is an Unknown level on the gate's
enable, MOS transistors will have an uncertain conductance and interval logic will be used
to resolve their source and drain (see Interval Logic: Resolving Uncertain Strength at a Node
in the Logic Simulation chapter). Transfer gates also have an uncertain conductance and
their output will be resolved using interval logic. For tri-state gates, the output level will be
set to Unknown. The output strength will be defined by the gate definition for a tri-state gate.
5)
When the iteration limit is exceeded for “.CONTROL .MXDCI” or “.CONTROL .MXITR”,
a nonconvergence error stops execution. Nonconvergence may be due either to circuit path
length or problems with designs involving feedback. To eliminate oscillations caused by
problems involving feedback, the circuit design must be corrected. When nonconvergence is
due to path length, increasing the iteration limit should enable the circuit to converge. In
general, each node in the serial path length requires one iteration to propagate a signal.
Arbitrarily increasing the iteration limits is not recommended as it may dramatically increase
the execution time necessary to identify oscillating nodes.
6)
The “NONCONV” command can be used to identify which parts of the circuit have caused a
logic initialization or logic simulation to stop executing.
Examples:
!con .mxd=200 .mxp=200
CON .DISK=2M .MXOSC=30 .EUNK=*
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Additional Commands • 8-17
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DELAY
8.8 Default Device Delay Times
Normally, if a device has no delay specification, the delay times default to zero. The DELAY
command allows you to globally redefine the default values.
Default delay times are specified as follows:
DELAY .DEFAULT = d1, d2
DELAY
indicates a default delay time specification.
.DEFAULT
indicates that the default times for all unspecified delays are to be assigned.
Normally, the default delays are d1=d2=0.
d1
represents the nominal rise delay time where:
“d1” must be an integer between 0 and 10000.
d2
represents the nominal fall delay where:
“d2” must be an integer between 0 and 10000.
Examples:
!DEL .DEF = 16,5
!del
.default=0, 0
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Additional Commands • 8-18
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DISK
8.9 Disk File Name Reassignment
The DISK command enables you to change the default file name for the “STORE” command.
To change the “STORE” disk file name, enter:
DISK
filename
DISK
changes the “STORE” disk file name. If no file name is specified, the program
will tell you the name of the present default disk file name.
filename
represents the name of the disk file to which STOREd output will be written.
(Default: filename= “store.out”)
Application Notes:
1)
Whenever a DISK command is specified, any STOREd data will be written to that disk file
until another file name is specified.
2)
Each time a STORE command is specified, any existing data on the “DISK” file in effect
may be overwritten (default), appended or a new cycle will be created.
3)
The file name can be unlimited in length, but must conform to the file name syntax of your
operating system. For the UNIX operating system, the file name is case sensitive.
4)
The “FILE .STO=“ command can also be used to change the default file name.
Examples:
DISK sim.results
DI PATTERN.INP
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Additional Commands • 8-19
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ERRORS
8.10 Error Summary
When the program indicates that errors occurred during read-in, preprocessing or simulation, you
should enter the “t/s ERRORS” command to determine their error level and type. For input errors,
the line number and the input file name will also be reported.
To check the errors, enter:
TYPE
STORE
ERRORS [ / LEVEL=value ]
TYPE
STORE
...
(optional) directs the error messages to standard output
or to a disk file.
ERRORS
reports any error and warning messages.
LEVEL
(optional) indicates that only those errors with a severity level equal to “value”
are to be output. If not specified, all errors will be output.
value
represents a value from 1 to 5.
Examples:
STOR ERROR / LEVEL=2
ty er
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Additional Commands • 8-20
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EXCLUDE
8.11 Exclude Saving Simulation Node States
The EXCLUDE command specifies nets whose state values will not be saved during logic
simulation. To exclude registers, see “Exclude Saving Module Instance Variable Values” on page
8-25.
The format for the EXCLUDE command is:
EXCLUDE name
name ... name
EXCLUDE
specifies nets whose state values will not be saved during logic simulation.
name
represents the name of a net whose state changes will not be saved during logic
simulation.
Application Notes:
1)
The KEEP command can be used to specify nets whose logic simulation states are to be
saved. The MKEEP and MEXCLUDE commands will keep and exclude all variables
(including registers and memory variables) within a module or macro instance.
2)
The effects to the KEEP and EXCLUDE commands are cumulative. When an identical net
name is specified in more than one KEEP or EXCLUDE command, the last KEEP or
EXCLUDE command will determine if the logic simulation states for that net are saved.
3)
The KEEP, EXCLUDE, MKEEP and MEXCLUDE commands can be used with the
“CONTROL .SAVSIM=1” command option to save logic simulation state values.
Examples:
CONTROL .SAVSIM=1
EXCLUDE (REG15(QBAR A15
.exclude (m1(bit0 (m1(bit1
+ (m1(bit4 (m1(bit5 (m1(bit6 (m1(bit7 (driver
+ (iobuf(pin34
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Additional Commands • 8-21
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EXIT
8.12 Exiting The Program
The “EXIT” command is used for normal exit of HyperFault.
To exit the program, enter:
EXIT
EXIT
commands the HyperFault program to stop execution and exit normally.
Example:
EXI
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Additional Commands • 8-22
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FILE
8.13 File Name Specification
The FILE command enables you to redefine the default file names used for the SAVE, STORE and
BATCHFILE commands.
The format for the FILE command is:
FILE
[.SAV=filename]
[.STO=filename]
+
[.MODE=.APPEND] [.MODE=.OVERWRITE]
[.BAT=filename]
FILE
redefines the file name defaults.
.SAV
changes the file name prefix “save” to a user specified name for all of the save
files, including the save.dictionary file.
.STO
changes the file name for subsequent STORE commands.
.BAT
changes the default BATCHFILE command file name.
.MODE
specifies whether a report STOREd will either append to the existing .STO file
(or DISK command file) or overwrite the .STO file. (Default:
.MODE=.OVERWRITE)
filename
represents the redefined name of the file. A file name can be unlimited in length.
However, the name must conform to the syntax of your operating system.
Application Notes:
1)
The “FILE .SAV” command must be entered before using a FSIM command. Do not specify
a file name extension; the program will automatically provide the correct extensions.
(Default: filename=SAVE)
2)
The “FILE .STO” command is equivalent to the DISK command. (Default:
filename=STORE.OUT or STORE OUTPUT)
3)
A file name specified on a subsequent BATCHFILE command will override the “FILE
.BAT” command.
Example:
file .sav=run5
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Additional Commands • 8-23
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KEEP
8.14 Keeping Simulation Node States
The KEEP command specifies wires whose state values will be saved during logic simulation. To
save state values to registers, see “Keeping Module Instance Simulation Variable Values” on page
8-26.
The format for the KEEP command is:
KEEP name
name ... name
KEEP
specifies wires whose state values will be saved during logic simulation.
name
represents the name of a wire whose state changes will be kept during logic
simulation.
Application Notes:
1)
The EXCLUDE command can be used to specify wires to be excluded from the saved logic
simulation results.
2)
The MKEEP and MEXCLUDE commands will keep and exclude all variables (including
registers and memory variables) within a module or macro instance.
3)
The effects to the KEEP and EXCLUDE commands are cumulative.
4)
The KEEP, EXCLUDE, MKEEP and MEXCLUDE commands can be used with the
“CONTROL .SAVSIM=1” option.
Examples:
CONTROL .SAVSIM=1
KEEP (MAC15(REG08 (MAC1(MEM(ADDR01
.keep (m1(bit0 (m1(bit1 (m1(bit2 (m1(bit3
+ (m1(bit4 (m1(bit5 (m1(bit6 (m1(bit7
+ (iobuf(pin34
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MEXCLUDE
8.15 Exclude Saving Module Instance Variable Values
The MEXCLUDE command excludes the internal variable values from being saved during logic
simulation for module instances and macro expansions and any variable that is hierarchically
below the excluded module instance or macro expansion.
The format for the MEXCLUDE command is:
MEXCLUDE mname
mname ... mname
MEXCLUDE
specifies module instances and macro expansions that will not have their internal
variables and any variable that is hierarchically below the excluded module
instance or macro expansion saved during logic simulation.
mname
represents the name of a module instance or macro expansion.
Application Notes:
1)
The MKEEP command can be used to specify module instances and macro expansions for
which the logic simulation state values to all variables are saved.
2)
The effects to the MKEEP and MEXCLUDE commands are cumulative.
3)
The KEEP, EXCLUDE, MKEEP and MEXCLUDE commands can be used with the
“CONTROL .SAVSIM=1” option.
Examples:
CONTROL .SAVSIM=1
MKEEP (mac1(a
MEXCLUDE (mac1(a(c
!mexclude (m1(bit0 (m1(bit1 (m1(bit2 (m1(bit3
+ (m1(bit4 (m1(bit5 (m1(bit6 (m1(bit7 (driver
+ (iobuf(pin34
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Additional Commands • 8-25
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MKEEP
8.16 Keeping Module Instance Simulation Variable Values
The MKEEP command saves the logic simulation state values for all variables in the specified
module instances and macro expansions, and the state values for all variables hierarchically below
each specified module instance and macro expansion.
The format for the MKEEP command is:
MKEEP mname
mname ... mname
MKEEP
specifies module instances and macro expansions whose logic simulation state
values will be saved for all variables in the specified module instance and macro
expansion, and for all variables hierarchically below each specified module
instance and macro expansion.
mname
represents the name of a module instance or macro expansion.
Application Notes:
1)
The MEXCLUDE command can be used to specify module instances and macro expansions
whose internal variables will not be saved during logic simulation.
2)
The effects to the MKEEP and MEXCLUDE commands are cumulative.
3)
The KEEP, EXCLUDE, MKEEP and MEXCLUDE commands can be used with the
“CONTROL .SAVSIM=1” option.
Examples:
CONTROL .SAVSIM=1
MKEEP (mac1(a(b
.mkeep (m1(bit0 (m1(bit1 (m1(bit2 (m1(bit3
+ (m1(bit4 (m1(bit5 (m1(bit6 (m1(bit7 (driver
+ (iobuf(pin34
Hyperfault User's Manual
Additional Commands • 8-26
Simucad Proprietary
NOCONV
8.17 Nonconvergence Summary
The “t/s NOCONV” command generates a report of any nonconverged nodes and their oscillating
states for the time point that nonconvergence occurred for logic simulation.
To obtain a nonconvergence summary for nodes and devices, enter:
TYPE
STORE
NOCONV [ / INPUT ITER=val ]
TYPE
STORE
...
(optional) directs the nonconvergence table to standard output
or to a disk file.
NOCONV
reports the oscillating states for nonconverged nodes.
INPUT
(optional) reports the states for all inputs of devices which drive the oscillating
nodes.
ITER=val
(optional) specifies the iteration number to the 1st of eight states for each node
reported for nonconvergence. The default iteration for ’val’ is computed such that
the last of the eight states reported corresponds to the last iteration simulated
before no convergence halted the logic simulation.
(continued on next page)
Hyperfault User's Manual
Additional Commands • 8-27
Simucad Proprietary
NOCONV
(Nonconvergence Summary)
Application Notes:
1)
The “t/s NOCONV” command can be used to identify which parts of the circuit have caused
a logic initialization or logic simulation to nonconverge.
2)
The “t/s NOCONV” command reports the following information:
names of the unresolved devices and nodes.
the “type” of device and node as either a “.type” data keyword, “NODE” for a wired
connection with at least one bi-directional device or “BUS” for a wired connection
between two or more unidirectional enabled gates.
the node state values for the nonconvergence time point. State values reported are
preceded by a “...” to indicate possible previous states.
3)
Nonconvergence only occurs when gate delays are zero. Zero-delays occur during logic
initialization , which forces delays to be zero; or, during zero-delay logic simulation ; or,
when either zero delay or no delay is specified for devices (the default delay for Verilog
HDL devices is zero).
4)
When the iteration limit is exceeded while resolving node states at a time point, a
nonconvergence error stops execution. Nonconvergence may be due either to the circuit
path length or problems with designs involving feedback. The circuit design must be
corrected to eliminate oscillations caused by problems involving feedback. When
nonconvergence is due to path length, increasing the iteration limit should enable the circuit
to converge. In general, each node in the serial path length requires one iteration to
propagate a signal.
5)
The maximum iterations per pass for logic initialization can be redefined by the “CONTROL
.MXDCI” command. The maximum iterations at a time point for logic simulation can be
redefined by the “CONTROL .MXITR” command. Arbitrarily increasing these parameters
is not recommended as it may dramatically increase the execution time necessary to identify
oscillating nodes.
(continued on next page)
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Additional Commands • 8-28
Simucad Proprietary
NOCONV
(Nonconvergence Summary)
(Application Notes:)
6)
The maximum number of passes for logic initialization is defined by the “CONTROL
.MXPAS” command. When this limit is exceeded, the error message specifies the required
number of passes to complete logic initialization. To reduce the number of passes and
execution time, use “.INIT” to preset the state for critical nodes. Although arbitrarily setting
“CONTROL .MXPAS” to a large value will very likely converge a circuit that is
theoretically solvable, this is not recommended as the problem is usually due to incorrect
circuit design.
Examples:
ty noc
nocon /iter=43
Hyperfault User's Manual
Additional Commands • 8-29
Simucad Proprietary
PREPROC
8.18 Preprocessing Data
Normally, data preprocessing is automatically performed prior to initialization, logic simulation, or
fault simulation (i.e., when the SIMULATE or FSIM commands are given). However, you may
wish to use the PREPROC command to check for syntax errors without simulating.
To preprocess data, enter:
PREPROC
Application Notes:
1)
During data preprocessing, the program resolves and checks all gate input connections,
calculates fan-out connections and creates implicit nodes. Generally, the data is reformatted
for more efficient simulation.
2)
Once preprocessing has been performed, additional topological data cannot be entered.
3)
Note that at least the first three letters of this command must be specified (i.e. PRE).
4)
If serious errors occur during a phase of the preprocessing, you should correct the errors
before proceeding. If the errors were corrected interactively, enter “RESET ERRORS” and
then reissue the PREPROC command to continue preprocessing.
Hyperfault User's Manual
Additional Commands • 8-30
Simucad Proprietary
probe
8.19 Probing Node States
The probe command reports the value of variables and expressions in tabular format for logic
simulation.
The format for the probe command is:
STORE
STORE
STORE
probe
probe ITER
probe STEP dt
t1 t2 “format” (expression), expression ...
t1 t2 “format” (expression), expression ...
t1 t2 “format” (expression), expression ...
STORE
(optional) directs the probe output to a disk file. Use the DISK command to
specify the file name for the stored output.
probe
reports the value of variables and expressions in tabular format. (Default:
report the “on change” values)
STEP dt
(optional) causes the values to be reported between time “t1” to time “t2” at
intervals of “dt”.
ITER
(optional) causes values of variables and expressions to be reported for each
iteration at a time point.
t1 t2
(optional) represents an optional time point range over which the values will be
reported. When “t1” and “t2” are not specified the probe command will use the
simulation time values or the time values specified on the last probe command.
format
(optional) specifies the format for reporting the expressions. Any of the format
specifications for $display and $monitor are allowed (Default radix: %h)
expression
specifies any legal Verilog HDL expression. The parentheses around the first
specified expression are not required when it is just a single variable. Full
hierarchical path names can be used, otherwise the module instance selected by
the “SCOPE” command will be used. A “,,” can be used instead of a name to
insert a blank column in the report. When an “@” sign is used in front of any
expression, then values are reported when those expressions change.
(continued on next page)
Hyperfault User's Manual
Additional Commands • 8-31
Simucad Proprietary
probe
(Probing Node States)
Examples:
A typical way the probe command can be used is to declare the scope for a module instance,
and then list variables in the module that you want to report on. Using two commas between
variables would leave a blank column between variables:
scope main
pro a,,b,,c
// declare module instance “main”.
// blank column between variables.
The probe command can be used to report the value for any expression, such as, you could use
the following probe command to report the value for the assignment “out= (a+b) | (c+d)” for
each change of variable “clock”:
probe @clock,, “out=“, (a+b) | (c+d)
The STORE command can be used to store the probe report to a file:
store probe a,b
// stores the probe report to a file.
Some additional examples for the probe command are listed below:
probe main.i1.a
// report variable “a” inside instance “main.i1”
probe “output result = %o”, out
// use string and octal radix formats.
probe 0 100 %o{a,b,c}
// report concatenated variables as octal
store probe %b a[0:2], %h a[3:6] // vary the radix for reporting values.
Hyperfault User's Manual
Additional Commands • 8-32
Simucad Proprietary
QUIT
8.20 Quitting Execution
The QUIT command enables you to terminate an unwanted session without that session affecting
any active SAVE files.
To quit program execution, enter:
QUIT
Application Notes:
1)
The QUIT command aborts execution of the program and all program results since the last
SAVE command are lost.
Hyperfault User's Manual
Additional Commands • 8-33
Simucad Proprietary
RESET
8.21 Resetting Selected Data
The RESET command can be used to reset (i.e. delete) selected data information for the command
line version of HyperFault. For the graphical interface version, the HyperFault Simulation
Environment, use the Load/Reload Files button.
The form of the command is:
ALL
ERRORS
OUTPUTS
PATTERN
SAVFILE
RESET
RESET
resets selected program counters and/or flags as specified by the below options.
ALL
resets everything (as if you just began execution). The program will not issue a
warning.
ERRORS
deletes data error flags and messages up through level 4. This can be used to
continue a simulation after errors have been corrected, and to clear unnecessary
warning and error messages.
SAVFILE
resets the logic simulation save file data to eliminate disk storage.
(continued on next page)
Hyperfault User's Manual
Additional Commands • 8-34
Simucad Proprietary
RESET
(Resetting Selected Data)
Application Notes:
1)
For RESET OUTPUTS, new output commands can be entered from the menu selections or
input from a file.
2)
Before using “RESET SAVFILE”, reports should be generated and/or the SAVE files
should be copied to tape. After “RESET SAVFILE”, logic simulation can be continued from
the last simulation time point but output reports are not available for logic simulation results
prior to the last simulation time point.
Examples:
RES ERR
res savfile
Hyperfault User's Manual
Additional Commands • 8-35
Simucad Proprietary
SCOPE
8.22 Scope For Printing Module Variables
The SCOPE command declares the module instance used when the PRINT or probe commands
reports the values for variables and expressions in a module.
The format for the SCOPE command is:
SCOPE instance_name
SCOPE
declares the module instance used by the PRINT or probe command.
instance_name represents the instance name for the module whose variables will be reported by
the PRINT or probe commands.
Example:
SCOPE main.cpu.cache
Hyperfault User's Manual
Additional Commands • 8-36
Simucad Proprietary
SIMULATE
8.23 Logic Simulation Specification
Logic simulation can be performed by entering the SIMULATE command.
To initiate the logic simulation, enter:
SIMULATE t1 [ TO t2 ]
SIMULATE
performs time-response logic simulation that can use both finite and zero delay
specifications. Preprocessing (PREPROC) and logic initialization will be
automatically performed if they have not been previously.
t1 TO t2
represent the values of the first and last simulation time points (see note 1 below).
The keyword “TO” is optional.
Application Notes:
1)
When specifying the logic simulation time point range, the following items apply:
specifying neither t1 nor t2 or setting t2 to an arbitrary large number will cause
HyperFault to simulate until “$stop” or “$finish” is encountered in the netlist. You can
stop the simulation by clicking-on the “STOP” button or pushing the “Escape” key (Esc)
on the keyboard for the PC and “Ctrl-C” on Unix.
specifying a single time point indicates that simulation will be incrementally continued
for that amount of time. At time=0, this will start the simulation from time=0 for the
specified amount of time.
Specifying t1 and t2, with t1=0, runs the simulation from time=0 to time=t2.
Specifying t1 and t2, with t1 greater than zero, continues the simulation from the last
specified time point.
Specifying “TO t2” will continue the simulation until time=t2. This can be useful to
continue a simulation that was halted due to a breakpoint.
(continued on next page)
Hyperfault User's Manual
Additional Commands • 8-37
Simucad Proprietary
SIMULATE
(Logic Simulation Specification)
(Application Notes:)
2)
The SIMULATE command will automatically invoke the PREPROC command (if
PREPROC has not already been performed) and no further topological data can be entered.
3)
Simulation can either be continued from the last time point or restarted from time=0.
4)
The SIMULATE command uses inertial delays, which do not propagate level changes that
occur faster than the gate output can change (spike condition).
Examples:
simul 0 to 22k
SIM 5KGG 10K
SIM 5K
sim 0 15k
SI TO 5K
Hyperfault User's Manual
Additional Commands • 8-38
Simucad Proprietary
SIZES
8.24 Size-Of-Data Reprint
The SIZES command reports the memory usage for HyperFault.
To report the network size information, enter:
TYPE
STORE
SIZES
TYPE
STORE
...
(optional) directs the size information to standard output
or to a disk file.
SIZES
generates memory usage information.
Application Notes:
1)
Items reported include the total number of devices, network names, etc.
2)
The memory usage may be different after read-in, preprocessing and simulation.
3)
The memory usage is also reported in the “Help/About” box.
Examples:
NSTO SIZ
TY SIZ
Hyperfault User's Manual
Additional Commands • 8-39
Simucad Proprietary
SPIKES
8.25 Spike Summary Output
The “t/s SPIKES” command allows you to view all the nodes on which spikes were made
observable during logic simulation (see “Logic Simulation Specification” on page 8-37).
To generate a node spike summary, enter:
TYPE
STORE
SPIKES [t1 TO t2]
TYPE
STORE
...
(optional) directs the spike summary to standard output
or to a disk file.
SPIKES
lists a summary table of all spikes between two time points.
t1 TO t2
represent the minimum and maximum time point values over which the spike
output is to be generated. This time point range must be within the logic
simulation time point range. If the time points are not specified, the logic
simulation times are used. (The “TO” keyword is optional.)
Application Notes:
1)
A spike occurs when the gate input level changes faster than the gate output can change.
2)
Setting the criteria for spike conditions is controlled by the +pulse_e, +pulse_r, and
+pathpulse command line arguments. For additional information, see “Command-line
Options” on page 8-4.
3)
To enable spike recording during logic simulation for the SPIKE report, use the +silos_spike
command line option. For additional information, see “Command-line Options” on page 84.
Examples:
ty spikes
NSTO SPIKES 4.2K 4.8K
Hyperfault User's Manual
Additional Commands • 8-40
Simucad Proprietary
STORE
8.26 Storing Outputs
When a command that generates a report is preceded by the STORE command, the report output
will be directed to a disk file.
To specify the STORE command, enter:
STORE
command ...
STORE
directs the output to a 132 column disk file. As a default, this file is named
“store.out”.
command
represents a command structure which defines the type of data to be output.
These commands are described within this section of the manual.
Application Notes:
1)
If a command that generates a report is not preceded by the STORE command, then the
default output device is specified by the CONTROL command.
2)
To respecify the page width for the STORE command, use the “FORMAT .STORE”
command.
3)
The default file name for the STORE command may be redefined using the “DISK”
command or the “FILE .STO” command.
Examples:
store output on change
STO NETWORK /FDD
Hyperfault User's Manual
Additional Commands • 8-41
Simucad Proprietary
STRENGTH
8.27 Strength Specification For Gates
The STRENGTH command allows you to modify the default strength types.
To respecify default strength types for gate devices, use:
STRENGTH .device/strg .device/strg …
.DEFAULT/strg
STRENGTH
indicates that default strength-types are to be assigned to unidirectional gate
devices.
.device
represents a device keyword (see note 1 below). If no “device/N”, “device/P” or
“device/strg” keyword is specified for an individual gate device, the program
defaults to a “CMOS” strength type.
DEFAULT
sets the strength for all devices that do not have the strength explicitly specified.
The default is “CMOS” strength type.
strg
represents any combination of “D”, “R” or “Z”. The first character indicates the
strength of the Low level. The second character indicates the strength of the
Unknown level. The third character indicates the strength of the High level. “D”
represents Strong strength, “R” represents Pull strength, and “Z” represents HighZ strength.
Alternatively, the characters “N”, “P” or “C” can be used by themselves to
indicate NMOS-type (DRR), PMOS-type (RRD) or CMOS-type (DRD) defaults.
(continued on next page)
Hyperfault User's Manual
Additional Commands • 8-42
Simucad Proprietary
STRENGTH
(Strength Specification For Gates)
Application Notes:
1)
The “device” keyword can be any of the combinatorial gate devices.
2)
Supply-strength cannot be defined.
Examples:
!strength .nor/n .nand/n .not/c
!strength default/ddd
Hyperfault User's Manual
Additional Commands • 8-43
Simucad Proprietary
SYMBOL
8.28 Symbol Modification For Output
The SYMBOL command allows you to use a unique symbol for each possible logic state.
To modify the output state symbols, use:
SYMBOL sc=char sc=char sc=char ...
SYMBOL
specifies that the state code symbols are to be redefined.
sc
represents one of the state-type codes for the OUTPUT, POUTPUT and probe
reports and for the .CLK and .PATTERN stimulus specifications:
state
symbols
state
default
report symbol
S0
S*
S1
SHV
Supply Low
Supply Unknown
Supply High
Supply High-Voltage
0
*
1
1
D0
D*
D1
DHV
Driving Low
Driving Unknown
Driving High
Driving High-Voltage
0
*
1
1
R0
R*
R1
RHV
Resistive Low
Resistive Unknown
Resistive High
Resistive High-Voltage
0
*
1
1
Z0
Z*
Z1
ZHV
High-Z Low
High-Z Unknown
High-Z High
High-Z High-Voltage
Z
Z
Z
Z
default
stimulus
char
0
*
1
Z
(continued on next page)
Hyperfault User's Manual
Additional Commands • 8-44
Simucad Proprietary
SYMBOL
(Symbol Modification For Output)
(sc)
char
The following symbols are used only in the output reports. No symbol can be
defined to input these states for .CLK or .PATTERN stimulus:
state
symbols
state
default
report symbol
*0
**
*1
*HV
Uncertain Low
Uncertain Unknown
Uncertain High
Uncertain High-Voltage
*
*
*
*
0D
*D
1D
HVD
Decaying Low
Decaying Unknown
Decaying High
Decaying High-Voltage
D
D
D
D
*S
Spike
S
default
stimulus
char
represents the single character you want to be used to indicate the state. The
comment character (default a “$”) cannot be used as a “char” symbol.
Application Notes:
1)
Enter the SYMBOL command before the “.PATTERN” and “.CLK” specifications are
entered to redefine symbols used for stimulus state values.
2)
The SYMBOL command can redefine node state symbols either before or after logic
simulation for the “t/s OUTPUT”, probe, and “t/s POUTPUT” reports.
(continued on next page)
Hyperfault User's Manual
Additional Commands • 8-45
Simucad Proprietary
SYMBOL
(Symbol Modification For Output)
(Application Notes:)
3)
When the same symbol is used to represent the different states (as in the defaults of 0,*,1)
for the input stimulus for a .CLK or .PATTERN specification, the program resolves the
ambiguity in the following order:
the most recent symbol specified by the most recently entered SYMBOL command is
used.
for the default symbols not specified by a SYMBOL command, the higher strength is
used and within a strength, the higher level is used.
For example, if “SYMBOL D1=+ R0=+” is entered, then the symbol “+” would mean
Resistive Low. If “SYMBOL D1=+ D*=+” is entered, then the symbol “+” would mean
Driving Unknown.
4)
Note that the Unset state symbol cannot be changed; it will always be a question mark “?”.
Examples:
SYMBOL Z0=- Z*=# Z1=+
.symbol r*=U z*=U d*=U r1=H z1=H d1=H d0=L
+ r0=L z0=L
SYM 0D=L *D=U 1D=H S0=O S*=X S1=I
!SYM D0=O D*=X D1=I *S=^
Hyperfault User's Manual
Additional Commands • 8-46
Simucad Proprietary
9. Index
$
$fs_dut
specification 5-1
$fs_options
specification 5-3
$resetstartsave system task 7-19
$stopsave system task 7-19
`
`celldefine
saving variables 4-18
`define
Project Setting menu 4-16
`enable_portfaults 1-27
specification 5-18
`suppress_faults 1-27
fault exclusion 1-27
specification 5-19
`uselib 8-8
+
+define command line option 8-5
+delay_mode_distributed command line option 8-5
+delay_mode_path command line option 8-5
+delay_mode_unit command line option 8-5
+delay_mode_zero command line option 8-5
+fault_vcd command line option 8-6
+ignore_sdf_interconnect_delay command line option
8-6
+ignore_sdf_port_delay command line option 8-6
+incdir command line option 8-6
+libext command line option 8-5
+libnonamehide command line option 8-5
+librescan command line option 8-5
+libverbose command line option 8-5
+maxdelays command line option 8-6
+mindelays command line option 8-6
+no_default_variables command line option 8-6
+no_pulse_msg command line option 8-6
+no_tchk_msg command line option 8-6
+nodoldisplay command line option 8-6
+nolibfaults command line option 8-6
+notimingchecks command line option 8-6
+nowarntfmpc command line option 8-6
+pulse_e command line option 8-7
+pulse_quiet command line option 8-7
+pulse_r command line option 8-7
+suppressfloat 8-7
Hyperfault User's Manual
+suppressredef 8-7
+timing_checks command line option 8-7
+typdelays command line option 8-6
+width_mismatches command line option 8-7
+xl_order command line option 8-8
A
abort
Escape key 4-2
STOP button 4-2
accumulate fault simulation results 1-7
activity
Activity menu selection 4-35
Activity Report For Nodes 6-2
Activity report
example 3-15
Add One Bit 4-73
Add Signal/Expression menu 4-63
Add Signals to Analyzer menu selection 4-60
Add Zero Bit 4-73
Add/Remove Breakpoint menu 4-76
analog behavioral modeling
analog waveforms 4-53
Analog Integer Display menu 4-46
Analyzer Symbol Table File 4-15
Arrange Icons menu 4-48
B
batch fault simulation example 3-39
Black Background menu 4-46, 4-47
blank lines
Data Analyzer 4-73
Break Simulation menu 4-31
breakpoints
Breakpoints menu 4-33
bus
contention report 8-10
BUSCON command
syntax definition 8-10
C
-c command line option 8-4
Cancel button
definition 4-2
Carry Soft Count Forward check box 4-24
carry_possible_counts option 5-10, 6-16
Cascade menu 4-48
case
-u command line option 8-4
celldefine
saving variables 8-15
checkpoint_interval option 5-10
Index • 9-1
Simucad Proprietary
CHGLIB command
syntax definition 8-12
Clear Signal List 4-74
click-on
explanation 3-1
Close button definition 4-2
Close menu 4-13
Code Coverage 4-35
color
signal strength 4-52
color coding
Data Analyzer 4-74
colored traces
Data Analyzer 4-74
Command Line Arguments 8-4
GUI 4-15
relative path names 4-16
command line options 8-8
commands
input
from file 8-2
required syntax 6-1
comments
respecifying comment character 8-13
concurrent fault simulation
explanation 1-11
number of concurrent faults 5-4, 6-17
context menus
main menus 4-59
continuous assignment
registers 7-22
Control command
syntax definition 8-13
CONTROL command
.COM option 8-13
.CUSTREPORT option 8-13
.DISABLECACHE option 8-13
.DISK option 8-13
.DMAX option 8-13
.DMIN option 8-13
.EUNK option 8-13
.HCHAR option 8-13
.HIST option 8-13
.MXDCI option 8-13
.MXITR option 8-13
.NONCON option 8-13
.NSCHAR option 8-13
.RECIRCULATE option 8-13
.SAVCELL option 8-13
.SAVSIM option 8-13
.SYNONYM option 8-13
.TPS option 8-13
convergence 4-39
Copy Image to Clipboard menu 4-8
Copy menu 4-6, 4-75, 4-77
Hyperfault User's Manual
Copy Scope menu selection 4-61
core dump on Unix 2-2
crash for fault simulation 5-10, 6-15
Crash Recovery Controls
fault dictionary file 4-25
custom report save file 8-13
Cut menu 4-75
D
Data Analyzer
Add Bookmark 4-67
analog & digital signals 4-53
copy waveforms to Word 4-50
Delete Bookmark 4-67
different simulations 4-54
Fonts menu 4-45
Goto Timepoint 4-65
memory caching 8-14
multiple copies 4-54
No Saved Data 4-55
Print menu 4-4
Scope 4-50
signal thickness 4-52
strength color codes 4-52
Time Scale Dialog Box 4-66
Trace Signal Inputs 4-68
Value 4-50
Data Analyzer menu 4-50
Data Tip Radix menu 4-76
Data Tips menu 4-47, 4-76
debug
Break Simulation menu 4-31
Breakpoints menu 4-33
Data Analyzer menu 4-50
Display menu 4-49
Explorer menu 4-49
Finish Current Timepoint menu 4-32
Go menu 4-30
Step menu 4-32
delay
command
syntax definition 8-18
delay
default specification 8-18
maximum/minimum delay command 8-14
preprocessing calculation 8-30
delay
min
typ
max setting 4-16
Delete Group 4-72
Delete Item/s menu 4-74
Delete menu 4-8
Detect Mismatched 1/0/Z
Index • 9-2
Simucad Proprietary
tri-state on test nodes 4-24
Device Under Test
example 3-13
GUI specifying 4-19
digital signals
Data Analyzer 4-53
disable cache
Project Setting menu 4-16
disk
command
syntax definition 8-19
Display Iteration Data 4-70
Display menu 4-49
distributed fault simulation 1-39
GUI specification 4-21
distributed fault simulation
example 3-34
distributed fault simulation installation on Unix 2-12
distributed fault simulation specification 5-3
Distributed Process Selection Tab 4-21
Drop Possible Detects check box 4-24
E
Edit menu 4-6
Enable Log File menu 4-17
encryption
CHGLIB command 8-12
error
command
syntax definition 8-20
Error menu selection 4-36
preprocessing check 8-30
reporting 8-20
reset all errors 8-34
turn off port connection warning 8-6
evaluation steps 2-1
exclude
command
syntax definition 8-21
excluding faults 1-21
excluding module instance node values 8-25
excluding simulation node states 8-21
input-stuck fault specifications 6-56
output-stuck fault specifications 6-57
exit
command
syntax definition 8-22
Exit menu 4-5
expected values 7-6
Explorer
Add Signals to Analyzer 4-60
Explorer menu 4-44
Go to Definition 4-60
Go To Module Source menu 4-44
Hyperfault User's Manual
Open Explorer menu 4-44
Explorer menu 4-49
expressions
Data Analyzer 4-69, 4-73
Watch Window 4-63
extensions
save file size 7-19
Verilog HDL extensions 7-20
extensions to Verilog HDL 4-16
F
-f command line option 8-4
fault dictionary file
crash recovery 4-25
renaming 8-23
Fault menu selection 4-37
Fault report example 3-26
Fault Sampling Tab 4-20
Fault Selection Tab 4-19
Fault Sim menu 4-28
Fault Sim Schedule
automatic stop/restart 4-24
fault simulation
$fs_dut specification 5-1
$fs_strobe specification 5-16
`enable_portfaults specification 5-18
`suppress_faults specification 5-19
accumulate detections via GUI 4-25
Activity menu selection 4-35
activity report 6-2
batch example 3-39
concurrent explanation 1-11
concurrent fault specification 5-4, 6-17
control of parameters 6-14
design flow 1-5
detected faults 1-34
developing test vectors 1-10
device under test specification 5-1
distributed 1-39
distributed setup via GUI 4-21
distributed specification 5-3
excluding faults via GUI 4-20
excluding input-stuck faults 6-56
excluding output-stuck faults 6-57
explanation 1-4
fault exclusion 1-21, 6-2
fault grading 1-9, 3-2
fault simulation specification 6-23
fault_vcd command line option 8-6
Faults report 6-9
High-Z detect 1-37, 6-19
HyperCov reporting of sub-blocks 1-42, 6-33
hypertrophic 5-9, 6-17
hypertrophic explanation 1-36
Index • 9-3
Simucad Proprietary
incremental command 6-24
initial fault injection 4-26, 6-23
input-stuck-high specification 6-36
input-stuck-low specification 6-37
iteration controls via GUI 4-25
iteration limit for oscillations 6-16
iterative command 6-26
list of commands 1-43
list of faults 6-27
maximum memory 5-7
memory utilization 1-31
monitor 6-20
oscillation exclusion 6-56, 6-57
oscillations 1-38, 6-31
output-stuck-high specification 6-38
output-stuck-low specification 6-39
port faults 1-27
possible detected faults 1-34
possible detects between runs 5-10, 6-16
quit for overnight runs 6-28
reading faults back in 6-13
recover 6-30
recover option 6-30
reduce iteration time 6-16
reduce multiple pass time 6-16
regular expressions for excluded input-stuck-at high
faults 6-44
regular expressions for excluded input-stuck-at low
faults 6-46
regular expressions for excluded output-stuck-at high
faults 6-52
regular expressions for excluded output-stuck-at low
faults 6-54
regular expressions for input-stuck-at high faults 6-40
regular expressions for input-stuck-at low faults 6-42
regular expressions for output-stuck-at high faults 648
regular expressions for output-stuck-at low faults 650
replace detections via GUI 4-25
sampling faults via GUI 4-20
save and recovery 5-10, 6-15
selecting faults via GUI 4-19
show fault simulation status 4-28
soft detect 1-35
specifying faults 1-16
specifying possible detect threshold 6-18
speed 1-40
spike checking 6-31
start fault simulation via GUI 4-28
statistical 1-28, 5-5
statistical explanation 1-12
statistical seed 6-23
statistical seed 1-28
stop fault simulation via GUI 4-28
Hyperfault User's Manual
suppressing faults 1-27
test node specification 5-16
test nodes 1-29
undetected faults 1-34
Unknown levels on enables 8-14
untestable faults 6-19
verifying results 1-41
fault simulation
distributed example 3-34
fault report example 3-26
incremental example 3-28
iterative example 3-31
statistical example 3-17
Fault Simulation Settings menu 4-19
Fault Strobing Tab 4-20
faults
accumulate detections via GUI 4-25
excluding via GUI 4-20
iteration controls via GUI 4-25
replace detections via GUI 4-25
sampling via GUI 4-20
selecting via GUI 4-19
FAULTS report command 6-9
faults_per_pass 5-4
FCONTROL command
syntax definition 6-14
file
FILE command
syntax definition 8-23
file
file name specification 8-23
output naming 8-19
File menu 4-3
Files menu 4-12
filter
expressions 4-60
Filters menu 4-26, 4-27
Finish Current Timepoint menu 4-32
FLEXlm license manager
PC 2-5
floating license
computer name on PC 2-8
host name on Unix 2-13, 2-16
hostid on PC 2-8
hostid on Unix 2-13, 2-16
PC to UNIX 2-8
floating node messages
Project Setting menu 4-16
FMON command
syntax definition 6-20
FMON command
DETAIL option 6-20
Fonts menu 4-45
FSIM command
syntax definition 6-23
Index • 9-4
Simucad Proprietary
gate
MOS
Unknown levels on enables 8-14
XFR
Unknown levels on enables 8-14
gate
strength specification 8-42
global
functions 7-20
tasks 7-20
variables 7-20
Go menu 4-30
Go to Definition menu selection 4-60
Go to Instance menu 4-76
Go To Module Source menu 4-44
Go to Module Source menu selection 4-61
Go To Scope menu 4-61
Goto Timepoint menu 4-65
groups in Data Analyzer 4-71
implicit node
created during preprocessing 8-30
incremental fault simulation
example 3-28
initial fault injection 4-26, 6-23
input
commands input from file 8-2
commands within the data file 8-2
input file order 8-3
input-stuck high specification 6-36
Input-stuck low specification 6-37
relative paths to files 4-13
symbol specification for state values 8-44
Insert Group 4-72
installation
correcting problems on NT 2-6
distributed fault simulation on Unix 2-12
requirements 2-3
windows 2-3
Instance Name Filter menu 4-62
integer and real waveform display 4-53
interactive debug
report 8-31
scope 8-36
iterate
fault simulation 6-24
Iteration menu selection 4-38
iterative fault simulation
example 3-31
H
K
hanging
behavioral level designs 4-41
HDL Code Coverage 4-35
help
on-line help 3-6
HSE
blank lines in Data Analyzer 4-73
expressions in Data Analyzer 4-73
radix in Data Analyzer 4-72
Toolbar text 3-1
hse keyword 7-19
HyperCov
fault simulation sub-block reporting 6-33
hyperflt keyword 7-19
hypertrophic fault explanation 1-36
hypertrophic fault simulation 5-9, 6-17
Hypertrophic Limit
set limit 4-23
-k command line option 8-4
KEEP command
syntax definition 8-24
Keeping simulation node states 8-24
Full Path Title menu 4-47
Functional Simulation menu 4-17
functions
global 7-20
multiple outputs 7-21
no inputs 7-21
ports 7-21
G
I
I/O Pad
stimulustable 7-12
Hyperfault User's Manual
L
-l command line option 8-4
-la command line option 8-4
library
example 4-12
file encryption 8-12
specify from menus 4-12
license
computer name on PC 2-8
host name on Unix 2-13, 2-16
hostid on PC 2-8
hostid on Unix 2-13, 2-16
PC node locked 2-5
PC to UNIX 2-8
license manager
PC 2-5
Linux installation 2-15
Index • 9-5
Simucad Proprietary
Load/Reload Input Files menu 4-27
lockup
behavioral level designs 4-41
log file
enable/disable 4-17
logic initialization
maximum iteration limit 8-14
Logic Sim menu 4-30
logic simulation
control specification 8-13
excluding selected nodes 8-21
excluding selected nodes by module 8-25
explanation 1-3
functional simulation 4-17
iteration limit 8-14
maximum/minimum delay command 8-14
node synonym names 8-16
preprocessing 8-30
renaming save file 8-23
running logic simulation 8-37
save file limit 8-14
save file reset 8-34
save file size 8-15
save variables in ‘celldefine 8-15
specification 8-37
spike report 8-40
Unknown levels on enables 8-14
xl_order command 8-16
xl_order command line option 8-8
M
Maximum File Size 4-17
memory
fault simulation utilization 1-31
Out of Memory on Unix 2-2
size of RAM on PC 2-8
size report 8-39
stimulustable 7-10
memory available on Unix 2-13
memory for fault simulation 5-7
memory usage 2-1
Data Analyzer caching 8-14
Memory Usage Controls
setting for fault simulation 4-23
menus
Arrange Icons menu 4-48
Break Simulation menu 4-31
Breakpoints menu 4-33
Cascade menu 4-48
Close menu 4-13
context menus 4-59
Data Analyzer menu 4-50
Display menu 4-49
Edit menu 4-6
Hyperfault User's Manual
Exit menu 4-5
Explorer menu 4-44, 4-49
Fault Sim menu 4-28
Fault Simulation Settings menu 4-19
File menu 4-3
Files menu 4-12
Filters menu 4-26, 4-27
Finish Current Timepoint menu 4-32
Fonts menu 4-45
Go menu 4-30
Go To Module Source menu 4-44
Load/Reload Input Files menu 4-27
Logic Sim menu 4-30
New menu 4-11
Open Explorer menu 4-44
Open menu 4-3, 4-12
Options menu 4-45
Project List Size menu 4-27
Project menu 4-11
Project Settings menu 4-15
Reload and Go menu 4-27
Reports menu 4-35
Save As menu 4-13
Save Project State menu 4-14
Status Bar 4-10
Step menu 4-32
Tabs menu 4-45
Tile menu 4-48
Title Tips menu 4-46
Toolbar 4-9, 4-10
View menu 4-9
Window menu 4-48
zoom selections 4-9
MEXCLUDE command
syntax definition 8-25
min : typ
max
Project Setting menu 4-16
min:typ:max
command 8-14
MKEEP command
syntax definition 8-26
N
Name Filter menu selection 4-60
netlist
preprocessing 8-30
size 8-39
New Group 4-71
New menu 4-11
no convergence 4-39
no saved data
project settings menu 4-18
No Saved Data 4-55
Index • 9-6
Simucad Proprietary
NOCONV command
syntax definition 8-27
nonconvergence
behavioral level designs 4-41
choosing a possible solution 8-14
command for report 8-27
gate level designs 4-39
initialization iterations 8-14
iteration limit 8-14
Nonconvergence menu selection 4-39
-nospec command line option 8-8
O
OK button
definition 4-2
Open Explorer menu 4-44
Open menu 4-3, 4-12
Options menu 4-45
order of execution switch 4-18
oscillation
fault simulation 1-38
output
file naming 8-19
output-stuck high specification 6-38
Output-stuck low specification 6-39
saving additional nodes 8-24
saving additional nodes by macro 8-26
symbol specification for state values 8-44
P
Pan to Last View menu 4-65
Pan to T1 menu 4-65
Pan to T2 menu 4-65
parentheses
fault report 1-35
Paste menu 4-75
PLI on PC 7-1
PLI on Unix 7-2
PLI overview 7-1
plusargs
command line option 8-7
Project Settings menu 4-17
portfaults
specification 5-18
ports
set missing ports to gnd 8-16
possible detect faults 1-34
possible detects
carry forward 4-24
dropping 4-24
threshold setting 4-24
preprocess
PREPROC command
Hyperfault User's Manual
syntax definition 8-30
Print menu
Data Analyzer 4-4
Print Preview menu 4-5
Print Setup menu 4-5
probe
syntax definition 8-31
probing node states 8-31
project
example for creating 3-7
Filters menu 4-26, 4-27
Project List Size menu 4-27
Project List Size menu 4-27
Project menu 4-11
Project Settings menu 4-15
Properties menu 4-62
Q
quit fault simulation for overnight runs 6-28
Quitting execution 8-33
R
-r command line option 8-4
race conditions
Display Iteration Data 4-70
radix
Data Analyzer 4-72
real and integer waveform display 4-53
recirculating save file for batch 8-15
recirculating save file for GUI 4-17
regular expressions 1-24, 4-60
fault simulation 6-40, 6-42, 6-44, 6-46, 6-48, 6-50, 652, 6-54
relative path names 4-16
relative paths to files 4-13
Reload and Go menu 4-27
Reload Groups 4-74
reports
default state symbols 8-44
fault simulation oscillation 1-38
nonconvergence 8-27
Reports menu 4-35
size information 8-39
spike report 8-40
stopping a report 8-1
storing wide output to disk file 8-41
symbol definition 8-44
reset
command 8-34
syntax definition 8-34
errors and warnings 8-34
everything (all) 8-34
preprocessing errors 8-30
Index • 9-7
Simucad Proprietary
restart fault simulation for overnight runs 6-28
Restore Project State menu 4-14
Retain simulation data file 4-17
Reverse Bit Order 4-73
S
-s command line option 8-4
same-pattern-iterate
fault simulation 6-26
save
automatically delete simulation history file 4-17
by hierarchy 4-62
control command saving 8-15
recirculating save file for batch 8-15
recirculating save file for GUI 4-17
save all variables 4-18
save file path 4-18
saving node states 8-24
saving node states by macro 8-26
simulation results 8-22
variables in `celldefine 4-18
save
turn-off, turn-on, reset 7-19
Save As menu 4-13
save file
renaming 8-23
resetting simulation results 8-34
save file
turn-off, turn-on, reset 7-19
save file size 4-17
Save Project State menu 4-14
SCOPE
syntax definition 8-36
scoping node states 8-36
SDF
$sdf_annotate system task 7-4
security code
computer name on PC 2-8
host name on Unix 2-13, 2-16
hostid on PC 2-8
hostid on Unix 2-13, 2-16
license manager PC 2-5
node locked 2-5
PC to UNIX 2-8
sharing node locked 2-5
Show Fault Sim Status menu selection 4-28
Show Groups 4-72
signal
color 4-52
signal names
hierarchical expansion of name 4-46
SIMULATE command
syntax definition 8-37
simulation
Hyperfault User's Manual
saving results 8-22
Simulation Data File Path 4-18
size limits
report 8-39
SIZE command
syntax definition 8-39
Size menu selection
memory usage 4-43
snap to edge
menu selection 4-45, 4-66
soft detect 1-35
Sort by Name menu selection 4-61
Sort by Type menu selection 4-61
specify blocks
eliminating specify blocks 8-8
variable delays 7-24
specifying faults 1-16
spike
fault simulation 6-31
output report 8-40
SPIKES command
syntax definition 8-40
Start Fault Sim menu selection 4-28
state machine symbols 4-15
statistical fault simulation 1-28, 5-5
explanation 1-12
statistical fault simulation
example 3-17
Status Bar
View menu 4-10
Step menu 4-32
stimulus
converting behavioral to tabular values 7-17
inputting tabular values 7-6
stimulustable 7-6, 7-7
extension setting 7-25
I/O Pad 7-12
stop
a process (Ctrl-C) 8-1
Stop Fault Sim menu selection 4-28
STORE command 8-19
syntax definition 8-41
Storing outputs 8-41
strength
mixed signal strength 4-52
strength
default specification for gates 8-42
Strength Color Coding menu 4-46
STRENGTH command
syntax definition 8-42
suppressing_faults
specification 5-19
SYMBOL command
syntax definition 8-44
syntax
Index • 9-8
Simucad Proprietary
for fault simulation commands 6-1
Syntax Color Coding menu 4-47
V
Tabs menu 4-45
tabular outputs
probe command 8-31
tasks
global 7-20
ports 7-21
technical support
how to access 2-18
test nodes
$fs_strobe specification 5-16
explanation 1-29
test pattern
activity report 6-2
test vectors
developing 1-9, 3-2
developing for fault simulation 1-10
Tile menu 4-48
time
Add Bookmark 4-67
Delete Bookmark 4-67
Goto Timepoint 4-65
Time Scale dialog box 4-66
timing checks
turn off messages 8-6
turn off timing checks 8-6
turn on timing checks for fault simulation 8-7
Title Tips menu 4-46
Toolbar
explanatory text 3-1
View menu 4-9, 4-10
trace
Trace Signal Inputs 4-68
Trace Color Coding menu 4-46
tristatedet option 1-37, 6-19
-v command line option 8-4
variables
global 7-20
Verilog HDL
extensions
expected values 7-6
HyperFault extensions 7-20
stimulustable 7-6, 7-7
tabular stimulus 7-17
save file size 7-19
Verilog HDL extensions
enabling 4-16
View menu 4-9
VIHIGH command
syntax definition 6-36
VILOW command
syntax definition 6-37
VOHIGH command
syntax definition 6-38
VOLOW command
syntax definition 6-39
VREISHIGH command
syntax definition 6-40
VREISLOW command
syntax definition 6-42
VREIXSHIGH command
syntax definition 6-44
VREIXSLOW command
syntax definition 6-46
VRESHIGH command
syntax definition 6-48
VRESLOW command
syntax definition 6-50
VREXSHIGH command
syntax definition 6-52
VREXSLOW command
syntax definition 6-54
U
W
-u command line option 8-4
UDP
default value 7-23
High-Z 7-23
Undo menu 4-75
Unix
distributed fault simulation installation 2-12
Unset state symbol 8-46
untestable option 6-19
upper case
-u command line option 8-4
uselib 8-8
User Registration menu 4-58
-w command line option 8-4
warning
+suppressfloat 8-7
+suppressredef 8-7
reset all warnings 8-34
turn off port connection warning 8-6
Watch Window 4-63
waveforms
color and signal strength 4-52
signal thickness 4-52
width mismatches
in expressions and assignments 8-7
Window menu 4-48
T
Hyperfault User's Manual
Index • 9-9
Simucad Proprietary
wire
procedural assignment 7-22
X
XHIGH command 6-57
XIHIGH command 6-56
XILOW command 6-56
xl_order command 8-16
xl_order command line option 8-8
XLOW command 6-57
Y
-y command line option 8-4
Z
zoom
View menu 4-9
Hyperfault User's Manual
Index • 9-10