Motivation
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Motivation
Chapter 13
Testing and Design for Testability
13.1 Motivation
Stable chip manufacturing costs
Increasing testing costs:
{ Increasing number of gates/device
{ Limited number of pins
! Increasing number of internal states
! Increasing logical and sequential depth
Example:
Testing of a combinational circuit with n inputs (10 MHz, one test per cycle)
n time for test
25
3 s
30 107 s
40
1 day
50 3.5 years
60 3656 years
Testability has to be considered in all phases of design
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Economical Considerations
13.2 Economical Considerations
13.2.1 Average Quality Level (AQL)
#DefectiveParts
aql = #AcceptedParts
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Economical Considerations
13.2.2 Correlation: Fault Coverage and Defective Parts
DL(= AQL): Number of defective circuits which have been classied as correct working
(testing with T )
Y: yield
T: fault coverage
DL = 1 ; Y 1;T
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Economical Considerations
Figure 13.1: Defect level as function of yield and fault coverage
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Design Flow: Testing
13.3 Design Flow: Testing
Figure 13.2: A typical synthesis ow
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Fundamental Denitions
13.3.1 Chip Test after Manufacturing
Manufacturing Process
#
Parametric Test (current/power dissipation)
(erroneous chips are marked with color points and removed after sawing)
#
Chip Test on Tester
13.4 Fundamental Denitions
Figure 13.3: Relationship between faults, errors and failures
fault:
physical defect, imperfection or aw which occurs in an hardware or software component
error:
manifestation of a fault (erroneous information on an hardware line or in a program,
caused by a fault)
failure:
malfunction of a system
Figure 13.4: Three-universe model of a system
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Fault Models
13.5 Fault Models
Basis: physical phenomena
Oxide defects
Missing implants
Lithographic defects
Junction defects
Metal shorts & opens
Moisture accumulation
Impurities/Contaminants
Static discharge
Figure 13.5: Examples for physical faults
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Fault Models
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Fault Models
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Fault Models
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Fault Models
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Fault Tolerant Design
13.6 Fault Tolerant Design
Fault tolerance achieved by redundancy techniques:
Duplication with Complementary Logic
Figure 13.6: Fault detection by duplication with complementary logic
Self-Checking Logic
Recongurable Array Structures
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Fault Tolerant Design
Figure 13.7: 4-by-4 array with one spare column
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Fault Tolerant Design
Figure 13.8: Recongured array
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Test Pattern Generation
13.7 Test Pattern Generation
manually
pseudo random (leads up to 60% fault coverage)
algorithmic
special test patterns for RAMs
? fault coverage sucient ?
) fault simulation
13.7.1 The D-Algorithm
Every test generation procedure has to solve the following problems
1. Creation of a change at the faulty line
2. Propagation of the change to the primary output line
In the D-Algorithm the symbols D and D are used to refer to the changes. D and D are used
as follows:
D: used if a line has the value 1 in absence of a fault and the value 0 in case of a fault
ocurrance
D: used if a line has the value 0 if no fault occurs and otherwise the value 1
The D-algorithm method for path sensitization consists of two principal phases:
1. forward drive (propagation) of an D-value to an primary output
2. backward trace (consistency operation)
These two steps are iterated for dierent propagation paths for the D-value from one dedicated
internal point i to one dedicated primary output point o until the backward trace phase is
nished without any contradiction (a test vector for a fault at i has been found) or until all
possible paths from i to o have been examined.
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Test Pattern Generation
Figure 13.9: Basic concept of D-algorithm
1. A primitive D-cube of a failure is a D-cube associated with a fault l= on the output
line l of a gate G. This produces the value D or D on l and the input lines have values
which would produce in the fault-free case.
Figure 13.10: Primitive D-cube of fault (pdcf) for two-input NAND gate
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Test Pattern Generation
2. A propagation D-cube of a failure species the propagation of changes at one (or
more) inputs of a gate G to its output l.
Figure 13.11: Propagation-D-cube (pdc) for two-input NAND gate
3. A singular cover of a gate G is a f0,1,Xg truth table representation of G
Figure 13.12: Singular cover for two-input NAND gate
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Test Pattern Generation
Figure 13.13: Singular covers for several basic logic gates
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Test Pattern Generation
Figure 13.14: Construction the singular cover of an logic module
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Test Pattern Generation
In the following the D-algorithm is illustrated for the given example from g. 13.15
Figure 13.15: Example circuit illustrating D-algorithm
Table 13.1: Propagation D-cube table
Table 13.2: Singular cover table
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Test Pattern Generation
Table 13.3: D-cube intersection table
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Test Pattern Generation
Running the D-algorithm for generating a test for line 5/0:
1. Start with D-cube for the fault 5/0:
2. The D of line 5 is automatically propagated to line 6 and 7 by cube j .
3. Now the propagation along path 6 ! 9 ! 11 is considered:
D on line 6 is propagated to line 9 by cube d. Combining d and k yields cube l:
4. If cube i is used with D instead of D, the propagation to the output can be done:
5. Now the consistency phase is started and a value for line 4 has to be found. From the
singular cover table can be seen that a 0 on line 10 implies both line 7 and line 8 to be
1. In cube m line 7 is a D (and also line 5 which is connected to 7 by j ) and this D must
now be set to 1 which is a contradiction which disables the path sensitization 5 ! 6/7
! 9 ! 11.
) Start test vector generation using another path
6. Starting the propagation along 5 ! 7 ! 10 ! 11 leads to the following cube:
7. From the singular cover table we get the information that a 1 on line 8 is the same as a
0 on line 4. Additionally it can be seen that the 0 on line 9 can be obtained by a 1 on
line 1.
8. This yields the nal cube
1110DDD10DD
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Test Pattern Generation
9. ) a test vector for line 5/0 is given by
1110
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Fault Simulation
13.8 Fault Simulation
13.8.1 Algorithms: Serial Fault Simulation
Figure 13.16: Serial fault simulation
13.8.2 Improved Algorithms
Parallel Fault Simulation
Concurrent Fault Simulation
) discussed in CAD lecture
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Design for Testability
13.9 Design for Testability
Circuit level: restriction of physically possible faults
Logic level: restrict possibilities of realizations
System level: restrict size of components and number of states
Testability:
controllability
observability
! additional chip area required
! shorter design cycle
Methods to improve controllability and observability:
ad-hoc techniques
structured approaches
Figure 13.17: Design for testability: complex gate (a) not testable with stuck-at model. (b)
fully testable with stuck-at model
13.9.1 Ad-Hoc Techniques
developed for special design
less silicon area
design automation almost impossible
partitioning (test of circuit components by use of dedicated multiplexers)
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Design for Testability
Figure 13.18: Testability: ad-hoc techniques (partitioning for testability)
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Design for Testability
Figure 13.19: Testability: ad-hoc techniques (a) insertion of register in order to limit logic
depth to a given maximum value. (b) test shift registers for PLA test (increasing PLA area).
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Design for Testability
13.9.2 Scan-Path Methods
Scan-Path:
Main idea: test of sequential network is reduced to test of combinational network
for circuits consisting of logic with some feedbacks
can be realized by reconguration of latches as shift registers (two mode of use)
Figure 13.20: Feedback logic with scanpath
Test scan-path/register function rst:
Flush test (0 : : : 010 : : : 0) or
shift test (00110011 : : : ) (each register transfer is tested by this combination: 0 ! 0,
0 ! 1, 1 ! 1 and 1 ! 0).
Cycle for testing combinational logic function:
1. Scan mode: Preload Y and set PI
2. System operation mode: Wait until inputs of Y are steady. Clock new state into Y.
3. Shift state out.
Compare PO and state values with expected responses
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Design for Testability
Advantages:
Testability of clocked circuits is improved and guaranteed at design stage
Consistent with good VLSI design practice
(rules, abstraction, modularity : : :)
Does not require special CAD
Disadvantages:
Wastes silicon
Constrains designer to design according given conditions
Additional Complexity
Overhead
' 2% for a fundamentally 'structured' design
' 30% for 'wild' logic
13.9.3 Built-In Tests
System generates test vectors by its own
Analyse and evaluation of test vectors is also automatically done
Compromise: silicon $ testability
Test Pattern Generators
Test patterns are generated inside the circuit to be tested
Short testing time, simple test programs, self-test
Example: Test pattern memories, deterministic generators, counter
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Design for Testability
Figure 13.21: Examples for built-in test pattern generators
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Design for Testability
Pseudo Random Number Generators
Figure 13.22: Pseudo random pattern generator
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Design for Testability
Example:
Figure 13.23: Example for pseudo random pattern generator
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Design for Testability
13.9.4 Evaluation of Testing Data
Evaluation of testing results inside the circuit
Counting techniques, signature analyse
Example: Counting Techniques
Figure 13.24: Counting techniques for test data evaluation
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Design for Testability
Signature Analyse
Communication technique: coding theory
Code words: data stream D, polynom P(x), division modulo 2
D =Q+ R
P
P
! Evaluation of testing data
Figure 13.25: Test data evaluation by signature analyse
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Design for Testability
Signature Analyse: Degree of Fault Recognition
1. Length of sequence: m bit ! 2m sequences possible
2. One sequence contains no faults ! number of erroneous sequences is 2m ; 1
3. Length of signature register: n bit ! 2n signatures
4. 2m sequences are mapped on 2n signatures ! number of nondetectable faults:
2m ; 1 = 2m;n ; 1
2n
5. Possibility for nondetection of erroneous sequence: number of nondetectable faults divided by number of possible faults:
m;n
N = 22m ;;11
6. ) Fault detection rate:
m;n
F = 1 ; 22m ;;1 1
F 1 ; 2n
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Design for Testability
Interpretation:
all faults recognized if m < n (trivial)
long sequences: n is important only
n = 16 bit ;! F = 99,99985%
Parallel Signature Register with k Inputs
Figure 13.26: Parallel signature register
Fault recognition rate:
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mk;n
F = 1 ; 2 2mk ;;11
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Design for Testability
13.9.5 Built-In Logic Block Observation
A BILBO register is a universal element for use in either a scanpath environment or a self-test
(signature analysis) environment.
Figure 13.27: BILBO registers: 1. full circuit 2. normal use 3. scan-path use 4. signature
analysis
Advantages:
Versatility
{ Normal operation
{ Scan-path test: enhances testability
{ Test vector generation via LFSR
{ Data compression via LFSR
{ Combined scan-path/self-test using same LFSRs
Disadvantages:
Silicon area
{ BILBO latch can be ' 50% larger than ordinary latch
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13.9.6 Example: Self-testing Circuit
Figure 13.28: Example: self-testing circuit
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