Symbol Interleaver/
Deinterleaver
MegaCore Function User Guide
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Core Version:
1.3.0
Document Version: 1.3.0 rev. 1
Document Date: June 2002
Copyright
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,
specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless
noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or
service names are the property of their respective holders. Altera products are protected under numerous U.S.
and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product, or service described
herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the
latest version of device specifications before relying on any published information and before placing orders for
products or services.
ii
UG-INTERLEAVER-1.3
Altera Corporation
About this User Guide
This user guide provides comprehensive information about the Altera®
Symbol Interleaver/Deinterleaver MegaCore® function.
Table 1 shows the user guide revision history.
f
Go to the following sources for more information:
■
■
See “Features” on page 9 for a complete list of the kit features,
including new features in this release.
Refer to the Symbol Interleaver/Deinterleaver readme file for latebreaking information that is not available in this user guide.
Table 1. User Guide Revision History
Date
Description
v1.0
First release of the user guide.
v1.1
Removed references to UMTS support and the UMTS
reference design. Provided updated instructions for
downloading the function from Altera’s web site.
August 2000, v1.2 Removed generic MegaCore introductory information.
June 2002, v1.3.0 Updated the document organization and formatting. Added
information on OpenCore Plus and DSP Builder support.
How to Find
Information
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■
■
■
Altera Corporation
The Adobe Acrobat Find feature allows you to search the contents of
a PDF file. Click the binoculars toolbar icon to open the Find dialog
box.
Bookmarks serve as an additional table of contents.
Thumbnail icons, which provide miniature previews of each page,
provide a link to the pages.
Numerous links, shown in green text, allow you to jump to related
information.
iii
About this User Guide
How to Contact
Altera
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For technical support on this product, go to
http://www.altera.com/mysupport. For additional information about
Altera products, consult the sources shown in Table 2.
Table 2. How to Contact Altera
Information Type
Technical support
USA & Canada
All Other Locations
http://www.altera.com/mysupport/
http://www.altera.com/mysupport/
(800) 800-EPLD (3753)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
(408) 544-7000 (1)
(7:30 a.m. to 5:30 p.m.
Pacific Time)
Product literature
http://www.altera.com
http://www.altera.com
Altera literature services
lit_req@altera.com (1)
lit_req@altera.com (1)
Non-technical customer
service
(800) 767-3753
(408) 544-7000
(7:30 a.m. to 5:30 p.m.
Pacific Time)
FTP site
ftp.altera.com
ftp.altera.com
Note:
(1)
iv
You can also contact your local Altera sales office or sales representative.
Altera Corporation
About this User Guide
Typographic
Conventions
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
The Symbol Interleaver/Deinterleaver MegaCore Function User Guide uses the
typographic conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown
in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
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v
About this User Guide
Glossary
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
bit error ratio (BER) The BER is the ratio of error bits to transmitted bits.
codeword A block of data to be interleaved and transmitted.
embedded array block (EAB) The building block of embedded arrays in
FLEX 10K devices. Each EAB provides 2,048 or 4,096 bits of configurable
RAM, ROM, FIFO, or dual-port RAM.
embedded system block (ESB) The embedded system block resides in the
MultiCore™ architecture of the APEX 20K. Each ESB contains 2,048
programmable bits that can be configured as product-term logic, look-up
table-based logic, or dual-port RAM, ROM, or content addressable
memory (CAM). Each ESB can be configured with up to 16 macrocells,
and can contain up to 32 product terms, XOR logic, 16 D-flipflops, and
parallel expanders.
EEC
Error correction code.
FEC
Forward error correction.
logic element (LE) The basic building block of a FLEX or APEX device. A
logic element consists of a look-up table (LUT)—i.e., a function generator
that quickly computes any function of four variables—and a
programmable register to support sequential functions.
MSPS Megasamples per second
MBPS Megabits per second
Reed-Solomon functions Reed-Solomon encoders/decoders convert a
data stream into a number of information symbols, followed by several
check, or parity, symbols.
span The numbers of rows used by an interleaver.
symbol An individual data bit; a codeword is composed of one or more
symbols.
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Altera Corporation
Contents
About this User Guide ............................................................................................................................... iii
How to Find Information .............................................................................................................. iii
How to Contact Altera .................................................................................................................. iv
Typographic Conventions ..............................................................................................................v
Glossary ........................................................................................................................................... vi
About this Core ..............................................................................................................................................9
Release Information .........................................................................................................................9
Introduction ......................................................................................................................................9
New in Version 1.3.0 ........................................................................................................................9
Features .............................................................................................................................................9
General Description .......................................................................................................................10
DSP Builder Support .............................................................................................................11
OpenCore & OpenCore Plus Hardware Evaluation .........................................................13
Performance ....................................................................................................................................13
Getting Started ............................................................................................................................................15
Software Requirements .................................................................................................................15
Design Flow ....................................................................................................................................15
Download & Install the Core ........................................................................................................16
Downloading the Symbol Interleaver/Deinterleaver MegaCore Function ..................16
Installing the Symbol Interleaver/Deinterleaver Files .....................................................17
Symbol Interleaver/Deinterleaver Directory Structure ...................................................17
Set Up Licensing .............................................................................................................................18
Append the License to Your license.dat File ......................................................................18
Specify the Core’s License File in the Quartus II Software ..............................................19
Symbol Interleaver/
Deinterleaver Walkthrough ..........................................................................................................19
Create a New Quartus II Project ..........................................................................................20
Launch the MegaWizard Plug-In Manager .......................................................................21
Choose the Algorithm & Direction ......................................................................................22
Specify the Characteristics ....................................................................................................23
Specify Memory Type & View Resource Usage ................................................................24
Using the Core with Simulink & DSP Builder ...........................................................................25
Compile & Place & Route the Design .........................................................................................25
Perform Synthesis Compilation & Post-Routing Simulation ..................................................26
Configuring a Device .....................................................................................................................27
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vii
Contents
Convolutional Interleaver Example: DVB IEEE Std. 802.14 Transmitter & Receiver ..........27
Block Interleaver Example: UMTS Transmitter & Receiver ....................................................29
Specifications ..............................................................................................................................................31
Functional Description ..................................................................................................................31
Convolutional Interleaver/Deinterleaver ..........................................................................32
Block Interleaver/Deinterleaver ..........................................................................................33
DSP Builder Feature & Simulation Support ......................................................................34
OpenCore Plus Time-Out Behavior ....................................................................................34
Core Verification ............................................................................................................................35
MegaWizard Plug-In .....................................................................................................................36
Simulation ...............................................................................................................................37
Signals ..............................................................................................................................................38
References .......................................................................................................................................39
viii
Altera Corporation
About this Core
1
About this Core
Release
Information
Table 4 provides information about this release of the Symbol
Interleaver/Deinterleaver MegaCore function.
Table 4. Symbol Interleaver/Deinterleaver Release Information
Item
Version
Description
1.3.0
Release Date
June 14, 2002
Ordering Code
IP-INLV
Product ID(s)
0013
Vendor ID(s)
6AF8 (Standard)
6AF9 (Time-Limited)
Introduction
The Altera Symbol Interleaver/Deinterleaver MegaCore function,
customized for Altera devices, works with error-correction
encoder/decoders to mitigate the effects of noise in a communications
system. You can use the Symbol Interleaver/Deinterleaver wizard
interface to implement interleaving/deinterleaving functions, including
block and convolutional interleaving.
New in Version
1.3.0
■
■
Supports OpenCore® and OpenCore Plus hardware evaluation
Has the DSP Builder Ready certification
Features
■
■
■
■
■
High-speed data rates: 120 megasamples per second (MSPS)
Supports convolutional interleaving algorithm
Supports block interleaving algorithm
Parameterized symbol width and codeword length
Compatible with discrete and streaming Reed-Solomon
encoders/decoders
Optimized for APEX™ and FLEX® devices
Internal or external memory architecture
Test-vector generation
Contains a burst error distribution analyzer
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Altera Corporation
9
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
General
Description
About this Core
Interleaving is a standard DSP function used in many communications
systems. Applications that store or transmit digital data require error
correction to reduce the effect of spurious noise that can corrupt data.
Digital communications systems designers can choose many types of
error-correction codes (EECs) to reduce the effect of errors in stored or
transmitted data. For example, Reed-Solomon encoders/decoders, which
are block-encoding algorithms, are used frequently to perform forward
error correction (FEC).
Symbol interleavers/deinterleavers can mitigate the effects of burst noise.
Typically, these functions are needed for transport channels that require a
bit error ratio (BER) on the order of 10-6. Interleaving improves the
efficiency of Reed-Solomon encoders/decoders by spreading burst errors
across several Reed-Solomon codewords.
The Altera Symbol Interleaver/Deinterleaver function uses internal or
external single-port or dual-port RAM. You can implement single-port
RAM using FLEX 10K EABs or an external RAM device; you can
implement dual-port RAM using the dual-port RAM capability of
APEX 20K ESBs or FLEX 10KE embedded array blocks (EABs), or an
external RAM device. Dual-port RAM provides a faster and smaller
implementation than single-port RAM.
The function uses a 120-MHz frequency range and supports both
continuous streaming and discrete mode, making the
interleaver/deinterleaver compatible with any type of Reed-Solomon
function.
The MegaWizard® Plug-In provided with the Symbol
Interleaver/Deinterleaver drastically reduces the design creation and
simulation cycles from several weeks to several minutes. The wizard
generates a highly optimized instance of a custom
interleaver/deinterleaver function as well as Quartus® II simulation files
that you can use to simulate the function. For example, by choosing a few
simple settings you can build an interleaving function as described in a
standard, such as DVB 802. Additionally, you can implement a custom
interleaving function by specifying the parameter values for your specific
transmission channel requirements. The flexibility of programmable logic
combined with the Symbol Interleaver/Deinterleaver MegaWizard
Plug-In allows you to build real-time systems to analyze and improve
parameter values determined by theoretical equations.
10
Altera Corporation
About this Core
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
DSP Builder Support
1
DSP Builder allows system, algorithm, and hardware engineers to share a
common development platform. The DSP Builder shortens DSP design
cycles by helping you create the hardware representation of a DSP design
in an algorithm-friendly development environment. You can combine
existing MATLAB functions and Simulink blocks with Altera DSP Builder
blocks to link system-level design and implementation with DSP
algorithm development. The DSP Builder consists of libraries of blocks as
shown in Figure 1.
Altera Corporation
11
About this Core
DSP system design in Altera programmable logic devices requires both
high-level algorithms and HDL development tools. The Altera DSP
Builder, which you can purchase as a separate product, integrates the
algorithm development, simulation, and verification capabilities of The
MathWorks MATLAB and Simulink system-level design tools with
VHDL synthesis and simulation of Altera development tools.
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
About this Core
Figure 1. DSP Builder Blocks in Simulink Library Browser
DSP Builder version 2.0.0 and higher provides modular support for Altera
DSP cores, including Symbol Interleaver/Deinterleaver. The MATLAB
software automatically detects cores that support DSP Builder and the
cores appear in the Simulink Library Browser.
f
12
For more information on using DSP Builder with Symbol
Interleaver/Deinterleaver, see “DSP Builder Feature & Simulation
Support” on page 34.
Altera Corporation
About this Core
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
OpenCore & OpenCore Plus Hardware Evaluation
1
The OpenCore Plus feature set supplements the OpenCore evaluation
flow by incorporating free hardware evaluation. The OpenCore Plus
hardware evaluation feature allows you to generate time-limited
programming files for designs that include Altera MegaCore functions.
You can use the OpenCore Plus hardware evaluation feature to perform
board-level design verification before deciding to purchase licenses for
the MegaCore functions. You only need to purchase a license when you
are completely satisfied with a core’s functionality and performance, and
would like to take your design to production.
1
f
Performance
If you are simulating a time-limited MegaCore function using
the DSP Builder and Simulink, i.e., in software, the core
operation does not time out.
For more information on OpenCore Plus hardware evaluation using
Symbol Interleaver/Deinterleaver, see “OpenCore Plus Time-Out
Behavior” on page 34 and AN 176: OpenCore Plus Hardware Evaluation of
MegaCore Functions.
Table 5 shows the Symbol Interleaver/Deinterleaver function’s
performance as calculated using the MAX+PLUS II version 9.2 software.
Table 5. Symbol Interleaver/Deinterleaver Performance
Function
Parameters
Device
Speed
Grade
LEs
Used
EABs
Used
fMAX
(MHz)
Convolutional interleaver
using FLEX 10KE EABs
Depth = 12,
FLEX 10KE
Unit Delay = 17, Symbol
Width = 8 bits (digital video
broadcast settings)
1
392
8
110
Block interleaver using
single-port RAM
Block length = 36,
Span delay = 20,
Data width = 8,
(UTRA) ITU-R RTT
-1
40
4
120
Altera Corporation
FLEX 10KE
13
About this Core
The OpenCore feature lets you test-drive Altera MegaCore functions for
free using the Quartus II software. You can verify the functionality of a
MegaCore function quickly and easily, as well as evaluate its size and
speed, before making a purchase decision. However, you cannot generate
device programming files.
Getting Started
Software
Requirements
■
A PC running the Windows 98/NT/2000 operating system
■
Quartus II version 1.0 or higher
■
DSP Builder version 2.0 or higher (optional)
Once you have purchased a license for Symbol Interleaver/Deinterleaver,
the design flow involves the following steps:
1
Altera Corporation
2
If you have not purchased a license, you can test-drive the core
for free using the OpenCore or OpenCore Plus feature. Refer to
AN 176: OpenCore Plus Hardware Evaluation of MegaCore Functions
for more information on the OpenCore Plus feature.
1.
Download and install the Symbol Interleaver/Deinterleaver
function.
2.
Set up licensing. This step is not required if you are test-driving the
core using the OpenCore feature, however, you do need to obtain
and install an OpenCore Plus license to test-drive the core using this
feature.
3.
Create a custom variation of the Symbol Interleaver/Deinterleaver
using the wizard.
4.
Implement the rest of your system using the Altera Hardware
Description Language (AHDL), VHDL, Verilog HDL, or schematic
entry.
5.
Use the Symbol Interleaver/Deinterleaver wizard-generated
simulation models to confirm your custom core’s operation.
6.
Compile your design and perform place-and-route.
7.
Perform system verification.
8.
Configure or program Altera devices with the design.
15
Getting Started
Design Flow
The instructions in this section require the following software:
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Download &
Install the Core
Getting Started
Before you can start using Altera MegaCore functions, you must obtain
the MegaCore files and install them on your PC. The following
instructions describe this process.
Downloading the Symbol Interleaver/Deinterleaver MegaCore
Function
If you have Internet access, you can download MegaCore functions from
Altera’s web site at http://www.altera.com. Follow the instructions
below to obtain the Symbol Interleaver/Deinterleaver via the Internet. If
you do not have Internet access, you can obtain the Symbol
Interleaver/Deinterleaver from your local Altera representative.
16
1.
Point your web browser to http://www.altera.com/ipmegastore.
2.
Choose Megafunctions from the Product Type drop-down list box.
3.
Choose Signal Processing (DSP) from the Technology drop-down
list box.
4.
Type Symbol Interleaver/Deinterleaver in the Keyword
Search box.
5.
Click Go.
6.
Click the link for the Altera Symbol Interleaver/Deinterleaver
MegaCore function in the search results table. The product
description web page displays.
7.
Click the Free Test Drive graphic on the top right of the product
description web page.
8.
Fill out the registration form, read the license agreement, and click
the I Agree button at the bottom of the page.
9.
Follow the instructions on the Symbol Interleaver/Deinterleaver
download and installation page to download the function and save
it to your hard disk.
Altera Corporation
Getting Started
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Installing the Symbol Interleaver/Deinterleaver Files
To install the Symbol Interleaver/Deinterleaver, perform the following
steps:
Choose Run (Start menu).
2.
Type <path name>\<filename>.exe, where <path name> is the
location of the downloaded MegaCore function and <filename> is the
filename of the function.
3.
Click OK. The Symbol Interleaver/Deinterleaver Installation
dialog box appears. Follow the on-screen instructions to finish
installation.
4.
After you have finished installing the MegaCore files, you may have
to specify the core’s library directory (typically
<path>\symbol_interleaver-v1.3.0\lib) as a user library in the
Quartus II software to access the core in the MegaWizard Plug-In
Manager. Search for “User Libraries” in Quartus II Help for
instructions on how to add these libraries.
Symbol Interleaver/Deinterleaver Directory Structure
Figure 2 shows the directory structure for the Symbol
Interleaver/Deinterleaver.
Figure 2. Symbol Interleaver/Deinterleaver Directory Structure
<path>/MegaCore/symbol_interleaver-v<version>
doc
Contains the Symbol Interleaver/Deinterleaver user guide (this document) in Adobe Acrobat
Portable Document Format (.pdf) as well as other documentation.
lib
Contains encrypted lower-level design files. After installing the MegaCore function,
you should set a user library in the Quartus II software that points to this directory.
This library allows you to access all the necessary MegaCore files.
dspbuilder
Contains the files for DSP Builder functionality.
lib_time_limited
Library folder for time-limited (OpenCore Plus) version of the core for Quartus II synthesis.
You should indicate this folder as a user library in the Quartus II software before attempting to
use the time-limited version of the Symbol Interleaver/Deinterleaver.
dspbuilder
Contains the files for DSP Builder functionality.
reference_design
Contains the reference design provided with the core.
Altera Corporation
17
2
Getting Started
1.
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Set Up
Licensing
Getting Started
You can use Altera’s OpenCore evaluation software to compile and
simulate the Symbol Interleaver/Deinterleaver MegaCore function in the
Quartus II software, allowing you to evaluate it before purchasing a
license. However, you must obtain a license from Altera before you can
generate programming files or EDIF, VHDL, or Verilog HDL gate-level
netlist files for simulation in third-party EDA tools.
After you purchase a license for Symbol Interleaver/Deinterleaver, you
can request a license file from the Altera web site at
http://www.altera.com/licensing and install it on your PC. When you
request a license file, Altera e-mails you a license.dat file. If you do not
have Internet access, contact your local Altera representative.
1
If you want to use the OpenCore Plus feature, you must request
a free license file from the licensing page of the Altera web site
(http://www.altera.com/licensing) to enable it. Your license file
is sent to you via e-mail; follow the instructions below to install
the license file.
To install your license, you can either append the license to your
license.dat file or you can specify the core’s license.dat file in the
Quartus II software.
1
Before you set up licensing for the Symbol
Interleaver/Deinterleaver, you must already have the Quartus II
software installed on your PC, with licensing set up.
Append the License to Your license.dat File
To append the license, perform the following steps:
18
1.
Close the following software if it is running on your PC:
■
■
■
■
■
Quartus II
MAX+PLUS II
LeonardoSpectrum
Synplify
ModelSim
2.
Open the Symbol Interleaver/Deinterleaver license file in a text
editor. The file should contain one FEATURE line, spanning 2 lines.
3.
Open your Quartus II license.dat file in a text editor.
4.
Copy the FEATURE line from the Symbol Interleaver/Deinterleaver
license file and paste it into a new line in the Quartus II license file.
Altera Corporation
Getting Started
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
1
5.
Do not delete any FEATURE lines from the Quartus II license
file.
Save the Quartus II license file as a text file.
1
When using editors such as Microsoft Word or Notepad,
ensure that the file does not have extra extensions appended
to it after you save (e.g., license.dat.txt or license.dat.doc).
Verify the filename at a command prompt.
2
Specify the Core’s License File in the Quartus II Software
1.
Create a text file with the FEATURE line and save it to your hard disk.
1
2.
Run the Quartus II software.
3.
Choose License Setup (Tools menu). The Options dialog box opens
to the License Setup page.
4.
In the License file box, add a semicolon to the end of the existing
license path and filename.
5.
Type the path and filename of the core license file after the
semicolon.
1
6.
Symbol
Interleaver/
Deinterleaver
Walkthrough
Altera recommends that you give the file a unique name,
e.g., <core name>_license.dat.
Do not include any spaces either around the semicolon or in
the path/filename.
Click OK to save your changes.
This walkthrough explains how to create an interleaver or deinterleaver
using the Altera Symbol Interleaver/Deinterleaver wizard and the
Quartus II software. As you go through the wizard, each page is described
in detail. When you are finished generating an interleaver or
deinterleaver, you can incorporate it into your overall project.
You can use Altera’s OpenCore evaluation feature to compile and
simulate the MegaCore functions, allowing you to evaluate the Symbol
Interleaver/Deinterleaver before deciding to purchase a license.
However, you must purchase a license before you can generate
programming files or EDIF, VHDL, or Verilog HDL gate-level netlist files
for simulation in third-party EDA tools.
Altera Corporation
19
Getting Started
To specify the core’s license file, perform the following steps:
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Getting Started
This walkthrough consists of the following steps:
■
■
■
■
■
“Create a New Quartus II Project” on page 20
“Launch the MegaWizard Plug-In Manager” on page 21
“Choose the Algorithm & Direction” on page 22
“Specify the Characteristics” on page 23
“Specify Memory Type & View Resource Usage” on page 24
Create a New Quartus II Project
Before you begin, you must create a new Quartus II project. With the New
Project wizard, you specify the working directory for the project, assign
the project name, and designate the name of the top-level design entity.
You will also specify the Symbol Interleaver/Deinterleaver user library.
To create a new project, perform the following steps:
1.
Choose Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software. You can also use the Quartus II Web Edition
software.
2.
Choose New Project Wizard (File menu).
3.
Click Next in the introduction (the introduction will not display if
you turned it off previously).
4.
Specify the working directory for your project. This walkthrough
uses the directory c:\qdesigns\symbol_interleaver-v1.3.0.
5.
Specify the name of the project. This walkthrough uses
symbol_interleaver-v1.3.0.
6.
Click Next.
7.
Click User Library Pathnames.
8.
Type <path>\symbol_interleaver-v1.3.0\lib\ (or
<path>\symbol_interleaver-v1.3.0\lib_time_limited\
to use the OpenCore Plus version) into the Library name box, where
<path> is the directory in which you installed the Symbol
Interleaver/Deinterleaver. The default installation directory is
c:\MegaCore.
9.
Click Add.
10. Click OK.
11. Click Next.
20
Altera Corporation
Getting Started
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
12. Click Finish.
You have finished creating your new Quartus II project.
Launch the MegaWizard Plug-In Manager
The MegaWizard Plug-In Manager allows you to run a wizard that helps
you easily specify options for the Symbol Interleaver/Deinterleaver. The
wizard lets you generate coefficients, make I/O settings, specify a filter
architecture, etc. Perform the following steps to launch the wizard and
begin generating a filter:
Choose MegaWizard Plug-In Manager (Tools menu).
2.
Select Create a new custom megafunction variation (default).
3.
Click Next.
4.
Expand the Signal Processing folder under Installed Plug-Ins by
clicking the + next to the name.
5.
Click Interleaver v<version> (either the standard or time-limited
version).
6.
Choose the output file type for your design; the wizard supports
AHDL, VHDL, and Verilog HDL.
7.
Type the name of the output file, e.g., interleaver. Figure 3 on
page 22 shows the wizard after you have made these settings.
8.
Click Next.
Getting Started
Altera Corporation
1.
2
21
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Getting Started
Figure 3. Choose Symbol Interleaver/Deinterleaver in the MegaWizard Plug-In
Manager
You are now ready to set the options for your custom Symbol
Interleaver/Deinterleaver.
Choose the Algorithm & Direction
Specify the type of algorithm (convolutional or block) and the direction
(interleaver or deinterleaver) and click Next. See Figure 4.
22
Altera Corporation
Getting Started
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Figure 4. Choose the Algorithm & Direction
2
Getting Started
Specify the Characteristics
Specify the characteristics of the function. As you adjust the settings, the
wizard graphically displays a block diagram of the function. Table 6
describes the options for the characteristics.
Table 6. Algorithm Characteristic Options
Function
Block (1)
Convolutional
Variable
Description
I
Number of columns.
J
Number of rows.
I
Unit delay value.
J
Number of branches.
Note:
(1)
Typically, the Reed-Solomon codeword length is the number of columns and the
number of rows is the number of codewords to interleave.
1
Altera Corporation
In a given system, you should use the same interleaving
algorithm for both the transmitter and receiver, as well as
using the same characteristics.
23
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Getting Started
You can use the list boxes in the Burst Error Distribution box to perform
burst error analysis (see Figure 5). Indicate the codeword length and the
estimated burst error length. The wizard displays the number of
codewords the burst error is spread across before interleaving and
indicates the number of Reed-Solomon check symbols required to correct
the error. The calculation assumes that two Reed-Solomon check symbols
are required to fix one symbol error per codeword. Click Next when you
are finished.
Figure 5. Specify the Characteristics
Specify Memory Type & View Resource Usage
Specify whether you want to use internal or external memory. The wizard
estimates the resources required by the function (see Figure 6). Click Next.
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Altera Corporation
Getting Started
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Figure 6. Memory & Resource Usage
2
Getting Started
Click Finish to accept your selections and generate the megafunction
variation.
Once you have created a megafunction variation, you can instantiate it
into your design. After you have finished your design, you are ready to
perform functional simulation to verify that your circuit is working
correctly.
Using the Core
with Simulink
& DSP Builder
You can use Simulink blocks, Altera DSP Builder blocks, and the Symbol
Interleaver/Deinterleaver to build a model of your design in the Simulink
software. Refer to “DSP Builder Support” on page 11, “DSP Builder
Feature & Simulation Support” on page 34, and the DSP Builder User Guide
for more information.
Compile &
Place & Route
the Design
You can use the Quartus II software to compile and place-and-route your
design. Refer to Quartus II Help for instructions on performing
compilation. After you have verified that your design is functionally
correct, you are ready to perform system verification.
Altera Corporation
25
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Perform
Synthesis
Compilation &
Post-Routing
Simulation
Getting Started
As a standard feature, Altera’s Quartus II software works seamlessly with
tools from all EDA vendors, including Cadence, Exemplar Logic, Mentor
Graphics, Synopsys, Synplicity, and Viewlogic.
1
After you have licensed the MegaCore function, you can use the
NativeLink™ feature to integrate the Quartus II software with
other EDA tools easily. See Quartus II Help for details.
The following sections describe the design flow to compile and simulate
your custom MegaCore design with the Quartus II software and a thirdparty EDA tool. To synthesize your design in a third-party EDA tool and
perform post-route simulation, perform the following steps:
26
1.
Create your Symbol Interleaver/Deinterleaver instance using the
Symbol Interleaver/Deinterleaver MegaWizard Plug-In.
2.
Create your custom design instantiating the Symbol
Interleaver/Deinterleaver function.
3.
Select Compile mode (Processing menu).
4.
Specify the Compiler settings in the Compiler Settings dialog box
(Processing menu) or use the Compiler Settings wizard.
5.
Specify the user libraries for the project and the order in which the
Compiler searches the libraries.
6.
Specify the input settings for the project.
a.
Choose EDA Tool Settings (Project menu).
b.
Select Custom EDIF in the Design entry/synthesis tool list.
c.
Click Settings.
d.
In the EDA Tool Input Settings dialog box, make sure that the
relevant tool name or option is selected in the Design
Entry/Synthesis Tool list.
7.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project menu). Use the 1993 VHDL language option.
8.
Compile your design. The Quartus II Compiler synthesizes and
performs place-and-route on your design, and generates output and
programming files.
Altera Corporation
Getting Started
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
9.
Import your Quartus II-generated output files (.edo, .vho, .vo, or
.sdo) into your third-party EDA tool for post-route, device-level, and
system-level simulation.
Configuring a
Device
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera device. If you are evaluating the MegaCore
function with the OpenCore feature, you must license the function before
you can generate configuration files.
Convolutional
Interleaver
Example: DVB
IEEE Std.
802.14
Transmitter &
Receiver
When you install the symbol interleaver/deinterleaver functions, the
installation program creates the directory
symbol_interleaver\reference_design\dvb, which contains the
reference design files for a digital video broadcast application that
conforms to IEEE Std. 802.14. This example design illustrates how to
combine and synchronize the interleaver and deinterleaver.
2
Getting Started
The system parameters, which meet IEEE Std. 802.14, are as follows:
■
■
■
Depth = 12
Unit delay = 17
Symbol width = 8
To use the reference design, perform the following steps:
1.
Create a new Quartus II project using the New Project Wizard (File
menu).
–
–
–
Specify TOP_DVB as the project name and top-level entity.
Add the design files in the
symbol_interleaver\reference_design\dvb directory to the
project.
Ensure that <path>\symbol_interleaver-v1.3.0\lib\
into the Library name box, where <path> is the directory in
which you installed the Symbol Interleaver/Deinterleaver.
2.
Choose Compile Mode (Processing menu).
3.
Choose Start Compilation (Processing menu).
4.
When compilation completes, choose Simulation Mode (Processing
menu).
5.
Choose Run Simulation (Processing menu).
You can change the parameters of the reference design by editing the
interleaver and deinterleaver variations. For example, you can doubleclick the symbols in the top_dvb.gdf file to open the variation for editing.
Altera Corporation
27
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
1
Getting Started
A system implementing both an interleaver and deinterleaver
only operates correctly if the parameter values of the interleaver
and deinterleaver are identical.
Figure 7 shows a block diagram of a system using the convolutional
interleaver/deinterleaver with a Reed-Solomon encoder/decoder.
Figure 7. Interleaver/Deinterleaver & Reed-Solomon Functions
Transmit
Reed
Solomon
Encoder
din[7..0]
din[7..0]
dout[7..0]
i_out[7..0]
sync_in
clock
sync_in
clock
sync_out
i_sync_out
Convolutional
Interleaver 12 X 17
Receive
sync_in_de
clock
din[7..0]
sync_in
dout[7..0]
dout[7..0]
clock
sync_out
sync_out
Reed
Solomon
Decoder
Convolutional
Interleaver 12 X 17
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Altera Corporation
Getting Started
Block
Interleaver
Example:
UMTS
Transmitter &
Receiver
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
When you install the symbol interleaver/deinterleaver functions, the
installation program creates the directory
symbol_interleaver\reference_design\block, which contains the
reference design files for a UMTS application. The system parameters for
this application are as follows:
■
■
Number of columns = 36
Number of rows= 20
To use the reference design, perform the following steps:
Create a new Quartus II project using the New Project Wizard (File
menu).
–
–
–
Specify TOP_UMTS as the project name and top-level entity.
Add the design files in the
symbol_interleaver\reference_design\block directory to the
project.
Ensure that <path>\symbol_interleaver-v1.3.0\lib\
into the Library name box, where <path> is the directory in
which you installed the Symbol Interleaver/Deinterleaver.
2.
Choose Compile Mode (Processing menu).
3.
Choose Start Compilation (Processing menu).
4.
When compilation completes, choose Simulation Mode (Processing
menu).
5.
Choose Run Simulation (Processing menu).
You can change the parameters of the reference design by editing the
interleaver and deinterleaver variations. For example, you can doubleclick the symbols in the top_umts.gdf file to open the variation for editing.
Altera Corporation
29
2
Getting Started
1.
Specifications
Functional
Description
Interleaving is the process of reordering the symbols in a group of
transmitted codewords such that adjacent symbols in the data stream are
not from the same codeword. The receiver reassembles the codewords
when it processes the data stream. The interleaving process helps reduce
the effects of burst errors (i.e., multiple errors in a row), because
rearranging the codeword symbols spreads the errors among multiple
codewords.
Depending on your application, you may choose to implement a
convolutional or a block interleaver/deinterleaver.
■
■
Block interleaver/deinterleavers process data in a discrete stream
and are used in applications such as GSM (i.e., mobile phones). These
functions are often used with Reed-Solomon functions or Turbo Code
encoders/decoders.
Compared to block interleavers/deinterleavers, convolutional
interleavers/deinterleavers provide reduced delay and lower memory
usage for the same distribution of errors. Figure 8 compares the data
streaming performed by the functions.
Figure 8. Data Stream Comparison
A
A1
Altera Corporation
B
B1
C
C1
Convolutional
Interleaver
Block
Interleaver
A1
A1
B1
C1
B1
C1
31
3
Specifications
Convolutional interleaver/deinterleaver functions process data in a
continuous stream, which makes them ideal for high-speed
applications that require correction for burst errors (e.g., digital video
broadcasting). Typically, these functions are used with ReedSolomon functions.
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Specifications
Convolutional Interleaver/Deinterleaver
Figure 9 illustrates convolutional interleaving and deinterleaving. The
number of branches is called the depth of the interleaver. The first branch
has no delay. Each consecutive branch introduces an additional symbol
delay. Each symbol contains a variable number of bits that you can modify
using the core’s wizard. The commutator connects to each branch in order,
for every symbol. Therefore, when a symbol enters a branch of the
interleaver, it leaves the branch via the output commutator after a variable
delay that depends on the branch index.
Figure 9. Convolutional Structure
De-Interleaver
Interleaver
(I-1)J
J
2J
2J
din
dout
dout
din
J
(I-1)J
For the deinterleaver, the delays introduced at each branch are
complementary to the interleaver. That is, once a symbol enters the branch
of the deinterleaver, it leaves the branch via the output commutator after
a variable delay that depends on the branch index. With this interleaving
structure, every symbol incurs a fixed delay through the combination of
the interleaver and deinterleaver. For synchronization purposes, the sync
bytes and inverted sync bytes must be routed to the first branch of the
interleaver, which corresponds to a null delay. In principle, the
deinterleaver is similar to the interleaver, but the branch indexes are
reversed, i.e., branch 1 incurs the largest delay. The deinterleaver
synchronization can be performed by routing the first recognized sync
byte in branch 1.
The interleaving/deinterleaving process introduces a constant delay
between the interleaver input data and the deinterleaver output data. The
delay is calculated using the following equation:
depth × symbol delay × (depth - 1) + 6
The symbol throughput is equal to the frequency of the function.
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Altera Corporation
Specifications
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
By understanding the delay principle, you can design your application to
operate on a continuous stream of codewords. To support continuous
streaming, you must use dual-port memory to implement a convolutional
interleaver/deinterleaver function. See “Performance” on page 13 for an
example of the resource usage and speed of the convolutional function.
Block Interleaver/Deinterleaver
The block interleaver/deinterleaver uses single-port SRAM memory
configured as a matrix of n rows by m columns to perform interleaving.
During the write cycle, the input symbols are written column by column;
during a read cycle, the output symbols are read row by row. The column
length is usually equal to the codeword length of the FEC encoder, while
the numbers of rows (often called the span) is the interleaver delay.
Figure 10 illustrates block function operation using a 6-symbol codeword.
Figure 10. Block Structure for a 6-Symbol Codeword
Block Interleaver Read Cycle
Block Interleaver Write Cycle
3
Specifications
din
dout
The block interleaver/deinterleaver operates in discrete mode with a
single -port memory used as a buffer. The symbol transmission consists of
an alternating sequence of write and read cycles. Each cycle delay is equal
to the buffer size, which is the block length multiplied by the span delay.
The total cumulative delay from the transmitter to the receiver can be
calculated using the following equation:
2 × number of rows × (number of columns + 4)
Altera Corporation
33
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Specifications
DSP Builder Feature & Simulation Support
You can create Simulink Model Files (.mdl) using Symbol
Interleaver/Deinterleaver and DSP Builder blocks. DSP Builder supports
the following Symbol Interleaver/Deinterleaver options:
■
■
Internal memory usage
Block mode
DSP Builder does not support convolutional mode.
After you create your model, you can perform simulation. DSP Builder
supports the simulation types shown in Table 7 for Symbol
Interleaver/Deinterleaver.
Table 7. Symbol Interleaver/Deinterleaver Simulation File Support in DSP Builder
Simulation Type
Simulation Flow
Precompiled ModelSim model
for RTL functional simulation
Not Supported
VHDL Output File (.vho) models You can generate a .vho after you have purchased a license for your
for timing simulation
MegaCore function. Refer to the “VHDL Output File (.vho)” topic in Quartus II
Help for more information.
Visual IP Models
Not Supported
Quartus II simulation
The DSP Builder SignalCompiler block generates a Quartus II simulation
vector file on-the-fly.
1
f
If you are using the time-limited version of the Symbol
Interleaver/Deinterleaver in your Model File, simulation does
not time out. The core only times out if you are performing
hardware evaluation as described in “OpenCore Plus Time-Out
Behavior” on page 34.
For more information on DSP Builder, see “DSP Builder Support” on
page 11.
OpenCore Plus Time-Out Behavior
The following events occur when the OpenCore Plus hardware evaluation
times out:
■
■
34
All address and data signals are driven to values present at time of
expiration
timed_out is driven from low to high
Altera Corporation
Specifications
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
A time-limited Symbol Interleaver/Deinterleaver runs for approximately
30 minutes for a 150-MHz clock (exactly 270,000,000,000 clock cycles of the
clock input clk).
f
Core
Verification
For more information on OpenCore Plus hardware evaluation, see
“OpenCore & OpenCore Plus Hardware Evaluation” on page 13 and
AN 176: OpenCore Plus Hardware Evaluation of MegaCore Functions.
Before releasing a version of the Symbol Interleaver/Deinterleaver, Altera
runs a comprehensive regression test that executes the wizard to create
the instance files. Next, Quartus II Vector Files (.vec) are created and the
results are compared to the MATLAB/Simulink software using the
Quartus II simulator.
The regression suite covers various parameters such as architecture
options, symbol bit widths, and FIFO depths for all branches. Figure 11
shows the regression flow.
Figure 11. Regression Flow
Compare
Results
Altera Corporation
Specifications
MATLAB
Script
3
Parameter
Sweep
Symbol
Interleaver/
Deinterleaver
Wizard
MATLAB
Simulink
Model
Synthesis
Structure
Output
File
Output
File
35
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
MegaWizard
Plug-In
Specifications
You can run the Symbol Interleaver/Deinterleaver wizard using the
MegaWizard Plug-In Manager. The wizard generates a custom
megafunction variation that you can instantiate in your design file.
Table 8 describes the options for the Symbol Interleaver/Deinterleaver
wizard.
Table 8. Symbol Interleaver/Deinterleaver Wizard Options
Option
Function
Description
Number of
columns
Block
Specifies the total length of the codeword (i.e., data symbol +
checksum symbol).
Number of
branches
Convolutional
Specifies the number of branches used by the interleaver.
Direction
Block
Convolutional
Indicates whether you wish to create an interleaver (transmitter) or
a deinterleaver (receiver).
Memory type
Block
Convolutional
Indicates whether you wish to use internal or external memory.
Convolutional interleaving uses synchronous dual-port RAM. Block
interleaving uses synchronous single-port RAM. For internal
memory, the MegaWizard Plug-In automatically instantiates the
most optimum EAB configuration.
Number of
rows
Block
Specifies the maximum number of codewords in the block
interleaver/deinterleaver memory.
Unit delay
element
Convolutional
Specifies the unit delay for each branch of the
interleaver/deinterleaver.
Symbol width
Block
Convolutional
Specifies the width of the input symbol.
Type
Block
Convolutional
Indicates whether you wish to create a block or convolutional
interleaver/deinterleaver.
When you create a new custom interleaver/deinterleaver function, the
wizard creates the following files:
■
■
■
36
AHDL Text Design File (.tdf), VHDL Design File (.vhd), or Verilog
Design File (.v) of the custom function that you can instantiate in your
system design.
Quartus II Vector File (.vec) that you can use for simulation.
Block Design File (.bdf) that you can use to include the function in a
schematic design.
Altera Corporation
Specifications
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Simulation
The wizard generates Quartus II Vector Files (.vec) that you can use to
simulate your custom interleaver/deinterleaver. After compiling your
design, you can use the Quartus II software to view the functionality and
timing as graphical timing diagrams. Figures 12, 13, and 14 show sample
timing diagrams for the Symbol Interleaver/Deinterleaver function.
Figure 12. Block Interleaver Read Cycle Timing Diagram
clock
clken
din[7..0]
205 206 207 208 209 210 211 212 213 214 215 216 217
218 219 220 221 222 223 224
sync_in
next_din
dout[7..0]
0
36
72
108 144 180
216 252
32
68
104 140 176 212
dout_valid
3
clock
clken
din[7..0]
1
0
1
2
3
4
5
6
7
8
9
10
11
sync_in
next_din
dout[7..0]
1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0
dout_valid
Figure 14. Convolutional Interleaver Timing Diagram
clock
din[7..0]
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
sync_in
clken
dout[7..0]
00
07
00
13
sync_out
Altera Corporation
37
Specifications
Figure 13. Block Interleaver Write Cycle Timing Diagram
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Signals
Specifications
The Symbol Interleaver/Deinterleaver function has the signals shown in
Table 9. Different signals are required depending on whether you
implement a block or convolutional function and whether you use
internal or external RAM.
Table 9. Symbol Interleaver/Deinterleaver Signals
Signal
Function
Memory
Type
Description
addr[]
Block
External
Memory address bus.
clk
Block
Convolutional
Internal
External
Input clock signal.
clken
Block
Convolutional
Internal
External
Active-high clock enable.
block_full
Block
External
Indicates that a block is full. block_full goes high when the
memory block is full.
block_empty
Block
External
Indicates that a block is empty. block_empty goes high when
the memory block is empty.
din[]
Block
Convolutional
Internal
Input symbol.
next_din
Block
Internal
Input enable. When next_din goes high, the next codeword
symbol input is ready to be read.
dout[]
Block
Convolutional
Internal
Output symbol.
dout_valid
Block
Internal
Output enable. When dout_enable goes high, the next
codeword symbol output is ready to be read.
read_add[]
Block
Convolutional
External
Read address bus output.
sync_in
Block
Convolutional
Internal
External
Active-high input resynchronization signal. For convolutional
functions, set the branch pointer to branch 0; for block functions,
set the branch pointer to column 0, row 0.
sync_out
Convolutional
Internal
External
Output synchronization signal. The sync_out signal goes high
on the first branch of the interleaver.
timed_out
Block
Convolutional
-
This signal only applies to time-limited versions of the core.
When the core operation times out, this signal is driven from low
to high. See “OpenCore Plus Time-Out Behavior” on page 34
for more details.
write_add[]
Block
Convolutional
External
Write address bus output.
write_enable
Block
External
Write enable. The write_enable signal is active high, and
should be connected to the write enable of the external RAM.
38
Altera Corporation
Specifications
References
Symbol Interleaver/Deinterleaver MegaCore Function User Guide
Andrews, Kenneth, Chris Heegard, and Dexter Kozen. A Theory of
Interleavers. Ithaca, New York. N.p., n.d.
European Telecommunications Standards Institute. DE/JTC-DVB-6,
Digital broadcasting systems for television, sound and data services.
3
Specifications
Altera Corporation
39