IIR Compiler
MegaCore Function
February 2001
User Guide
Version 1.0.1
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
A-UG-IIRCOMPILER-1.0.1
IIR CompilerMegaCore Function User Guide
Altera, APEX, APEX 20K, ByteBlasterMV, MegaCore, OpenCore, and Quartus are trademarks and/or service marks of Altera
Corporation in the United States and other countries. Altera Corporation acknowledges the trademarks of other organizations for
their respective products or services mentioned in this document, including the following: Verilog is a registered trademark of
Cadence Design Systems, Incorporated. Altera products are protected under numerous U.S. and foreign patents and pending
applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to
current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to
any products and services at any time without notice. Altera assumes no responsibility or liability arising out of
the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications
before relying on any published information and before placing orders for products or services.
Copyright  2001 Altera Corporation. All rights reserved.
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ii
About this User Guide
User Guide
This user guide provides comprehensive information about the Altera®
infinite impulse response (IIR) compiler MegaCore® function.
Table 1 shows the user guide revision history.
Table 1. Revision History
Revision
How to Find
Information
Description
1.00
January 5, 2001
First released version of the document.
1.0.1
February 12, 2001
Updated the document for version 1.0.1 of the
core, including updating the testing conditions
information and adding waveforms to show the
latency parameter.
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Altera Corporation
Date
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About this User Guide
IIR Compiler MegaCore Function User Guide
How to Contact
Altera
For the most up-to-date information about Altera products, go to the
Altera world-wide web site at http://www.altera.com.
For additional information about Altera products, consult the sources
shown in Table 2.
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Access
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Electronic mail
lit_req@altera.com (1)
lit_req@altera.com (1)
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You can also contact your local Altera sales office or sales representative.
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IIR Compiler MegaCore Function User Guide
Typographic
Conventions
About this User Guide
The IIR Compiler MegaCore Function User Guide uses the typographic
conventions shown in Table 3.
Table 3. Conventions
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold type.
Examples: fMAX , \maxplus2 directory, d: drive, chiptrip.gdf file.
Bold italic type
Book titles are shown in bold italic type with initial capital letters. Example:
1999 Device Data Book.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75
(High-Speed Board Design).
Italic type
Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of Quartus and MAX+PLUS II Help
topics are shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX 8000
Device with the ByteBlasterMV™ Download Cable.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,
input. Active-low signals are denoted by suffix _n, e.g., reset_n.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\max2work\tutorial\chiptrip.gdf. Also, sections of an actual
file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
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Bullets are used in a list of items when the sequence of the items is not important.
The checkmark indicates a procedure that consists of one step only.
1
r
The hand points to information that requires special attention.
f
The feet direct you to more information on a particular topic.
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The angled arrow indicates you should press the Enter key.
v
About this User Guide
Abbreviations &
Acronyms
IIR Compiler MegaCore Function User Guide
The following abbreviations and acronyms are used in this
document.
AGC
AHDL
CIC
EDA
EDIF
ESB
FIR
IIR
LE
PC
VHDL
vi
Automatic gain control circuitry
Altera Hardware Description Language
Cascaded integrated comb filter
Electronic design automation
Electronic Design Interchange Format
Embedded system block
Finite impulse response filter
Infinite impulse response filter
Logic element
Personal computer
VHSIC High-Level Hardware Description Language
Altera Corporation
Contents
User Guide
Specifications
Features .............................................................................................................................................9
General Description .........................................................................................................................9
Functional Description ..................................................................................................................10
Direct Form Structure ............................................................................................................10
Cascaded Structure ................................................................................................................11
Parallel Structure ....................................................................................................................12
Signals ..............................................................................................................................................13
MegaWizard Plug-In .....................................................................................................................13
Performance ....................................................................................................................................15
Getting Started
Download & Install the Function ................................................................................................18
Download the Function ........................................................................................................18
Installing the MegaCore Files ...............................................................................................18
Files Installed ..........................................................................................................................19
Generate an IIR Filter ....................................................................................................................19
Wizard Options ..............................................................................................................................21
Coefficient Wizard Page .......................................................................................................21
Enter Coefficient Values ...............................................................................................21
Enter Zero-Pole Values .................................................................................................24
MATLAB Script Example .............................................................................................25
Coefficient Scaling Wizard Page ..........................................................................................26
Data Path Width Wizard Page .............................................................................................29
Simulation Setting ..........................................................................................................30
Plotting ............................................................................................................................31
Frequency Response ......................................................................................................32
Structure Setting .............................................................................................................33
Feedback Bit Width Control ...................................................................................33
Feed-Forward Bit Width Control ..........................................................................34
Guidelines .......................................................................................................................35
Simulate in MATLAB ....................................................................................................................35
Compiling, Simulating & Device Configuration .......................................................................36
Implement the System ...........................................................................................................36
Simulate Using VHDL & Verilog HDL Models ................................................................37
Compiling & Simulating in the Quartus Software ............................................................37
Compiling & Simulating in the MAX+PLUS II Software ................................................37
Altera Corporation
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Contents
IIR Compiler MegaCore Function User Guide
Performing Synthesis, Compilation & Post-Routing Simulation ....................................38
For the Quartus Software ..............................................................................................38
For the MAX+PLUS II Software ..................................................................................39
Configuring a Device .............................................................................................................40
References .......................................................................................................................................40
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Specifications
1
Features
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General
Description
System-level programmable logic solution for infinite impulse
response (IIR) filters that dramatically shortens design cycles
Automatic conversion to cascaded IIR structure
Automatic conversion to parallel IIR structure
Supports IIR orders from 1 to 15
Supports data/coefficient bit widths from 1 to 32
Built-in zero/pole analyzer
Built-in frequency/time response simulator
Optimized for APEX™, FLEX®, and ACEX™ devices
Includes test vectors: provides a MATLAB/Simulink interface,
including bit-accurate models and testbench
OpenCoreTM feature allows designers to instantiate and simulate
designs in the QuartusTM or MAX+PLUS II software prior to licensing
Digital filters provide an important function in digital signal processing
(DSP) design, and are used in a wide variety of applications such as signal
separation, restoration, or shaping. The two classes of digital filters are IIR
and finite impulse response (FIR). IIR filters are primarily used for high
data throughput applications that require a sharp cut-off characteristic.
IIR filters require less hardware than FIR filters and have a faster response.
The IIR structure is well suited to automatic gain control circuits (AGC),
Goertzel algorithm implementation, digital direct synthesis, or cascaded
integrated comb (CIC) filters. Due to poles in their transfer function, IIR
filters are known as feedback systems. The recursive nature of the IIR filter
introduces additional design steps such as phase distortion analysis and
finite word-length effects analysis. The IIR compiler MegaCore® function
speeds up IIR design cycles by combining built-in system level analysis
tools with a parameterizable IIR MegaCore function.
Altera has extensively tested the IIR compiler function. The testing
methodology consists of comparing the timing and functional simulation
results of the design created by the IIR compiler with the IIR compiler
MATLAB model and with the built-in C++ model. The parameters tested
are the number of taps, structure, input bit width, coefficient bit width,
rounding, and saturation.
Altera Corporation
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Specifications
User Guide
Specifications
Functional
Description
IIR Compiler MegaCore Function User Guide
IIR filters of order n are characterized by Equation 1.
Equation 1
n
Yn =
n
∑ ai X ( n – i ) – ∑ bi Y ( n – 1 )
i=0
i=1
Where:
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Xi is the discrete input data
Yn the resulted filtered output data
The vector ai contains the coefficient value of the feed-forward path
The vector bi contain the coefficient value of the feedback path
The n coefficient ai, bi, values set the characteristic of the filter. The values
that are typically determined at the system level are the numerator and
denominator, respectively, of the floating point value of the system
transfer function in the Z-plane representation defined in Equation 2.
Equation 2
n
∑ ai Z
H(z) =
–1
i=0
----------------------n
1+
∑b Z
–i
i
i=1
The roots of the polynomial equation of the numerator and the roots of the
polynomial equation of the denominator are called the zeros and the poles
of the IIR filter, respectively. In the Z plane, the filter is stable when the
poles are entirely inside the unit circle or are coincident with zeros on the
unit circle.
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Altera Corporation
IIR Compiler MegaCore Function User Guide
Specifications
Direct Form Structure
1
Altera Corporation
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Specifications
The hardware realization of Equation 2 consists of adding weighted past
input values to weighted past output values as shown in Figure 1.
Specifications
IIR Compiler MegaCore Function User Guide
Figure 1. Addition of Weighted Past Input & Output Values
X(n)
Σ
Σ
Z
Σ
-b1
Σ
-b2
Σ
-bn
Z
Z
Y(n)
-1
a1
Σ
a2
Σ
an
Σ
-1
-1
This structure is called direct form II because it is directly drawn from
Equation 1. For high orders, the direct form structure may be sensitive to
finite word-length effects. That is, a small change in a filter coefficient
introduced by quantisation affects the pole-zero location and therefore
affects the filter stability and characteristics. One option to address this
issue is to increase the internal precision of the delay line or the coefficient
width. The IIR compiler supports up to 32 bits of internal precision for the
tap delay line as well as the coefficients.
Another option is to rearrange the coefficients for different hardware
structures. H(z) is rearranged in sections as second order and first order
IIR filters that are connected serially (cascaded implementation) or in
parallel. Each second-order filter is called a biquad.
Rearranging the coefficients of the direct form into cascaded or parallel
forms can be performed in third-party system tools such as MATLAB.
You can then import the coefficients tailored for cascaded or parallel
forms into the compiler wizard. You can also let the IIR compiler wizard
perform this task by specifying the form on the first page of the wizard.
Cascaded Structure
In a cascaded implementation, the system transfer function of the order n
IIR is rearranged by factorizing the second and first order filter. An
example is shown in Equation 3.
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Altera Corporation
IIR Compiler MegaCore Function User Guide
Specifications
Equation 3
( N + 1) ⁄ 2
∏
k=1
–2
a 0k + a 1k z + a 2k z
---------------------------------------------------- = C
–1
–2
1 + b 1k z + b 2k z
1
( N + 1) ⁄ 2
∏
Hk ( z )
k=1
Each product term of Equation 3 is a second or first order IIR filter. If n is
an odd number, the last product term is a first-order IIR filter. Figure 2
shows the cascaded structure.
Figure 2. Cascaded Structure
Xin
C
H 1 (z)
H k (z)
H n (z)
Yout
Parallel Structure
In a parallel implementation, the system transfer function of the n IIR filter
is rearranged in a sum of n/2 second-order and first-order filter. The IIR
system is obtained by performing a partial-fraction expansion of H(z) as
shown in Equation 4 and rearranging the residue term into a biquad.
Equation 4
(n + 1) ⁄ 2
H (z ) = C +
∑
k–1
–1
a 0k + a 1k z
---------------------------------------------- = C+
–1
–2
1 + b 1k z + b 2k z
(n + 1 ) ⁄ 2
∑
Hk( z )
k–1
Each sum term of Equation 4 is a second order IIR filter. If N is an odd
number, the last product term is a first order IIR filter. Figure 3 shows the
parallel structure.
Altera Corporation
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Specifications
H (z ) = C
–1
Specifications
IIR Compiler MegaCore Function User Guide
Figure 3. Parallel Structure
Xin
H 1 (z)
H k (z)
Σ
C
H n (z)
Σ
Σ
Yout
Parallel structures are generally larger than cascaded structures; however,
they generally run at a faster data rate.
Signals
The IIR compiler function has the signals shown in Table 1.
Table 1. IIR Compiler Signals
Signal
MegaWizard
Plug-In
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Type
Direction
Description
xin
Bus
Input
Input data to be filtered. The input bit width is set
in the IIR compiler wizard.
clock
Bit
Input
Clock.
srst
Bit
Input
Synchronous reset (optional), active high.
clken
Bit
Input
Clock enable (optional), active high.
yout
Bus
Output
Filtered output data. The output bit width is set in
the IIR compiler wizard.
You can launch the MegaWizard™ Plug-In Manager from within the
Quartus or MAX+PLUS II software, or you can run it from the command
line. The IIR compiler wizard generates an instance of the megafunction
that you can instantiate in your design. Table 2 highlights the main
features of the wizard.
Altera Corporation
IIR Compiler MegaCore Function User Guide
Specifications
1
Table 2. IIR Compiler Wizard Options
Coefficients
and Zero-Pole
Values
Filter
Description
Direct Form II You can set the characteristics of the IIR filter by importing the coefficient values
Cascaded
or the zero-pole values.
Parallel
You can enter coeficients manually as floating-point numbers or integers, or you
can import them from a file. The wizard generates the zero-pole values from the
coefficients.
You can enter zero-pole values manually or import them from a file. The wizard
can generate the coefficients from the zero-pole values.
Coefficient
Scaling
Direct Form
Cascaded
Parallel
The IIR compiler determines the output bit width based on the actual coefficient
values and the input bit width. These two parameters define the maximum
positive and negative output values. The wizard extrapolates the number of bits
required to represent that range of values. For full precision, you must use this
number of bits in your system.
You can scale the coefficients automatically, manually, or choose not to scale
them. The wizard dynamically plots Hfixed(z) in the Z plane so you can see if any poles are located outside of the unit circle.
System Model
Simulation
Direct Form
Cascaded
Parallel
You can use the built-in simulator to analyze any non-linearity on the transfer
function. The wizard dynamically shows the frequency or time response as you
change the stimulus. number system, and output bit width.
When you finish going through the wizard, it generates the following
files:
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Altera Corporation
Text Design File (.tdf) used to instantiate an instance of the FIR filter
in your design
MAX+PLUS II Vector File (.vec) used for simulation within the
MAX+PLUS II environment
Symbol File (.sym) used to instantiate the filter into a schematic
design
MATLAB and Simulink files used for simulation in MATLAB
Simulink
VHDL and Verilog HDL models used for simulation in other EDA
tools
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Specifications
Option
Performance
Table 3 shows the IIR compiler function’s performance using the Quartus
version 2000.09 software.
Notes:
Table 3. IIR Compiler Performance
Device
Filter
LEs
Used
EABs
Used
Data Rate
(MSPS)
APEX 20KE
IIR order 2 (16 bits)
216
0
82
APEX 20KE
IIR order 4 (12 bits)
354
0
67
Getting Started
User Guide
This design walkthrough involves the following steps:
1.
Obtain and install the IIR compiler function.
2.
Generate the filter(s) for your system using the IIR compiler wizard.
3.
Simulate the filter using the wizard-generated MATLAB models.
4.
Implement the rest of your system using the Altera Hardware
Description Language (AHDL), VHDL, Verilog HDL, or schematic
entry.
5.
Use the IIR compiler wizard-generated VHDL or Verilog HDL
simulation models to confirm your system’s operation.
6.
Compile your design and perform place-and-route.
7.
Perform system verification.
8.
License the IIR compiler function to configure or program the
devices.
The instructions assume that:
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Altera Corporation
You are using a PC.
You are familiar with the Quartus™ or MAX+PLUS® II software.
17
2
Getting Started
The Altera IIR compiler MegaCore™ function provides solutions for
integrating DSP functions into your digital system. This section describes
how to obtain the IIR compiler function, explains how to install it on your
PC, and describes how to implement a filter using the wizard. You can
test-drive MegaCore functions using the Altera OpenCore™ feature to
simulate the functions within your custom logic. When you are ready to
generate programming or configuration files, you should license the
function through the Altera web site or through your local Altera sales
representative. The IIR compiler is optimized for Altera APEX™ 20K
devices, greatly enhancing your productivity by allowing you to focus
efforts on the custom logic in the system.
Getting Started
IIR Compiler MegaCore Function User Guide
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Download &
Install the
Function
The Quartus software version 2000.09 or higher or the MAX+PLUS II
software version 10.0 or higher is installed in the default location.
You are using the OpenCore feature to test-drive the IIR compiler or
you have licensed the function.
Before you can start using the IIR compiler MegaCore function, you must
obtain the MegaCore files and install them on your PC. The following
instructions describe this process.
Download the Function
If you have Internet access, you can download MegaCore functions from
the Altera web site at http://www.altera.com. Follow the instructions
below to obtain the MegaCore functions via the Internet. If you do not
have Internet access, you can obtain the MegaCore functions from your
local Altera representative.
1.
Point your web browser to http://www.altera.com/IPmegastore.
2.
Type IIR compiler in the Keywords box of the IP MegaSearch
area and click Submit.
3.
Click the link for the Altera IIR compiler function.
4.
Follow the on-line instructions to download the function and save it
to your hard disk.
Installing the MegaCore Files
To install the files on Windows 95/98 or Windows NT 4.0, follow the
instructions below:
18
1.
Click Run (Start menu).
2.
Type <path name>\<filename>.exe, where <path name> is the location
of the downloaded MegaCore function and <filename> is the
filename of the function.
3.
Click OK. The MegaCore Installer dialog box appears. Follow the
on-line instructions to finish installation.
4.
After you have finished installing the MegaCore files, you must
specify the directory in which you installed them as a user library in
the Quartus or MAX+PLUS II software. Search for “User Libraries”
in Quartus or MAX+PLUS II Help for instructions on how to add
these libraries.
Altera Corporation
IIR Compiler MegaCore Function User Guide
Getting Started
Files Installed
The IIR compiler includes source files, a testbench, and documentation.
Table 1 shows the directory structure.
Table 1. IIR compiler Directory Structure
Directory
\doc
Contains documentation for the IIR compiler.
\lib
Contains encrypted design files for the IIR compiler.
\simlib\*
Contains the IIR compiler testbench.
This section describes the design flow using the Altera IIR compiler
MegaCore function and the Quartus or MAX+PLUS II development
system. The MegaWizard® Plug-In Manager, which you can use within
the Quartus or MAX+PLUS II software or as a stand-alone application,
lets you create or modify design files that contain MegaCore variations.
You can then instantiate the MegaCore variation in your design file. The
IIR compiler is parameterized, and you can customize it with the
MegaWizard Plug-In to meet the needs of your application.
You can use the Altera OpenCore feature to compile and simulate the
MegaCore functions, allowing you to evaluate the functions before
deciding to license them. However, you must obtain a license from Altera
before you can generate programming files or EDIF, VHDL, or
Verilog HDL gate-level netlist files for simulation in third-party EDA
tools.
1
You should use the Quartus software version 2000.09 or higher
or the MAX+PLUS II software version 10.0 or higher when
designing with the IIR compiler function. The function relies on
library files that only exist in these versions of software.
The following steps give an overview of how to create an IIR function
using the wizard. Detailed instructions on how to use various wizard
features is described in “Wizard Options” on page 21.
1.
Altera Corporation
Start the MegaWizard Plug-in Manager by choosing the
MegaWizard Plug-In Manager command (File menu) in any
Quartus or MAX+PLUS II application, or by starting the stand-alone
version of the MegaWizard Plug-In Manager by typing the
command megawiz r at a command prompt. The MegaWizard
Plug-In Manager dialog box is displayed.
19
2
Getting Started
Generate an IIR
Filter
Description
Getting Started
IIR Compiler MegaCore Function User Guide
1
Refer to Quartus or MAX+PLUS II Help for detailed
instructions on how to use the MegaWizard Plug-In
Manager.
2.
Specify that you want to create a new custom megafunction
variation and click Next.
3.
Select the IIR compiler function from the DSP MegaCore drop-down
list in the Available Megafunctions box, and specify the directory and
name for the files the wizard creates.
1
4.
If you do not specify the directory in which you installed the
MegaCore files as a user library in the Quartus or
MAX+PLUS II software, the function will not appear in the
Available Megafunctions box. Search for “User Libraries” in
Quartus or MAX+PLUS II Help for information on how to
specify these libraries.
Specify the IIR order and structure (direct form II, parallel, or
cascaded). Parallel and cascaded architectures are available for IIR
orders greater than 2.
1
To switch architectures (direct form, cascaded, or parallel) after
entering coefficients or zero-pole values for a given filter, you
can return to the first of the wizard page and select another
architecture. The IIR compiler automatically computes the
coefficient values of the new architecture.
5.
Import the coefficient values or the zero-pole values of the IIR filter
you wish to create.
6.
Scale the coefficients.
7.
Set the structure bit width of the feed forward and feedback data
paths of the chosen IIR struture. Estimate the quantization effect of
your selection with the interactive bit-accurate simulators.
8.
Specify the simulation stimulus output file(s).
When you finish going through the wizard, it creates an optimized netlist
of the IIR filter as well as a bit-accurate MATLAB model.
Once you have created a MegaCore variation, you can integrate it into
your custom design. After you have finished your design, you are ready
to instantiate it in your system design and compile it.
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Altera Corporation
IIR Compiler MegaCore Function User Guide
1
Wizard Options
Getting Started
For the best results, you should use the Fast logic synthesis style
when compiling your design in the MAX+PLUS II software.
This section describes how to use the features of the IIR compiler wizard.
Coefficient Wizard Page
Enter Coefficient Values
You can enter the coefficient values of the feed-forward IIR path (ai) and
the coefficient values of the feedback path (bi). You can import the
coefficients from a file or enter them manually. The coefficient values can
be floating-point numbers or integers.
Select the Zeros-Poles tab to generate the zero-pole values of the
coefficients. The IIR compiler calculates the roots of the numerator and
denominator polynome and the transfer function.
The wizard displays those values in the Z plane, providing information on
the IIR stability for floating-point coefficients. See Figure 1.
Altera Corporation
21
2
Getting Started
When you create a new variation, the wizard loads default coefficient
values for a default filter type. To build a different type of filter you must
enter the coefficients and zero-pole values. The wizard provides two ways
to set the IIR filter characteristics: setting the coefficient values of the feedforward and feedback IIR path or setting the zero-pole values of the
transfer function.
Getting Started
IIR Compiler MegaCore Function User Guide
Figure 1. Enter the Coefficients
The frequency diagram is described below:
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The Y axis scale represents the dB attenuation of the filter based on
the coefficients. A slider bar lets you to zoom the Y axis in and out.
The X axis is an absolute frequency, and is the ratio of the filter
frequency characteristic over the sample frequency.
The diagram is updated when you change the coefficients.
To enter or modify the coefficients manually:
a. Select the coefficient.
b. Enter the new value in the text box.
c. Click the New button.
To enter a coefficient set from a file, click on the Coefficient button
and load the ASCII coefficient file that you have created in a third
party system tool.
Altera Corporation
IIR Compiler MegaCore Function User Guide
Getting Started
For direct form II filters, the expected format of the coefficient file is:
A0
A1
A2
..
Ai
..
An
B0
B1
B2
..
Bi
..
Bn
2
Equation 1
n
∑ ai Z
H( z) =
–1
i=0
----------------------n
1+
∑b Z
–i
i
i=1
For cascaded and parallel architectures, the expected format of the
coefficient file is:
A00 A01 A02 B00 B01 B02
...
Ai0 Ai1 Ai2 Bi0 Bi1 Bi2
...
An0 An1 An2 Bn0 Bn1 Bn2
K
Where Aij are the floating-point coefficient values of the feed-forward
path of the biquad i, Bij are the floating-point coefficient values of the
feedback data path of the biquad i, and K is the gain factor of the cascaded
or parallel structure.
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Getting Started
Where Ai are the floating-point coefficient values of the polynome of the
numerator of the transfer function and Bi are the floating-point coefficient
values of the polynome of the denominator of the transfer function. See
Equation 1.
Getting Started
IIR Compiler MegaCore Function User Guide
1
The values displayed in the wizard are the coefficient values of
the hardware implementation (see Equation 2). The coefficients
of the feedback path are equal to the inverse of the coefficients of
the polynome of the coefficient of the transfer function.
Equation 2
n
Yn =
∑
n
a i X( n – i ) –
i=0
∑ bi Y( n – i )
i=1
Enter Zero-Pole Values
Enter the zero-pole values of the transfer function. The zero-pole values
can be imported from an ASCII file or can be entered manually as shown
in Figure 2.
Figure 2. Enter the Zero-Poles
The diagram is described below:
■
■
24
The X axis represents the real part of the zero and the pole; the Y axis
represents the imaginary part of the zero and the pole.
The blue circle are the zeros; the red crosses are the poles.
Altera Corporation
IIR Compiler MegaCore Function User Guide
■
■
■
Getting Started
The Z plane representation is scaled automatically based on the zeropole values.
To enter or modify the zeros-pole values manually:
a. Select the zero-pole value in the list.
b. Enter the new value in the text box.
c. Click New.
To enter a zero-pole set from a file, click the Zero-Poles button and
load the ASCI file that you have created from a third party system
tool.
2
The expected format of the file is:
Getting Started
Real(Z0)
Real(Zi)
....
Real(Zn)
Real(P0)
Real(Pi)
...
Real(Pn)
Imag(Z0)
Imag(Zi)
Imag(Zn)
Imag(P0)
Imag(Pi)
Imag(Pn)
Where Real(c) is the real part of the complex number c and Imag(c) is the
imaginary part of the complex number c.
MATLAB Script Example
Altera provides an example MATLAB M File (.m) with the IIR compiler.
You can run the M File, dformband.m, at the MATLAB prompt (see
Figure 3). This script generates a low-pass filter and yields three ASCII
files:
■
■
■
Coef.txt—Coefficients for the direct form II implementation
CoefSos.txt—Coefficients for the cascaded representation
ZerosPoles.txt—Zero-pole values
The IIR compiler outputs the coefficient values in two ASCII text files,
<design name>_FloatCoef.txt (the floating point values) and <design
name>_FixedCoef.txt (fixed point values).
Figure 3. dformband.m MATLAB Script
FilterOrder = 4;
[FeedForward,FeedBack] = ellip(2,3,50,[250/500,300/500],’bandpass’);
figure(1);
freqz(FeedForward,FeedBack);
figure(2);
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Getting Started
IIR Compiler MegaCore Function User Guide
zplane(FeedForward,FeedBack);
fid = fopen(‘coef.txt’,’w’);
for i=1:FilterOrder+1
fprintf(fid,’%e\n’,FeedForward(i));
end
for i=1:FilterOrder+1
fprintf(fid,’%e\n’,FeedBack(i));
end
fclose(fid);
[z,p,k] = tf2zp(FeedForward,FeedBack);
fid = fopen(‘ZeroPole.txt’,’w’);
for i=1:FilterOrder
fprintf(fid,’%e %e\n’,real(z(i)),imag(z(i)));
end
for i=1:FilterOrder
fprintf(fid,’%e %e\n’,real(p(i)),imag(p(i)));
end
fclose(fid);
Coefficient Scaling Wizard Page
Coefficient values are often represented as floating-point numbers. To
convert these numbers to a fixed-point system, the coefficients must be
multiplied by a scaling factor and rounded. The IIR compiler provides the
following scaling options:
26
■
Scale to a specified number of precision bits—Because the coefficients are
represented by a certain number of bits, it is possible to apply
whatever gain factor is required such that the maximum coefficient
value equals the maximum possible value for a given number of bits.
This approach produces coefficient values with a maximum signalto-noise ratio.
■
Limit scaling factors to powers of 2—With this approach, the IIR
compiler chooses the largest power of two scaling factor that can
represent the largest number within a particular number of bits of
resolution. Multiplying all of the coefficients by a particular gain
factor is the same as adding a gain factor before the IIR filter. In this
case, applying a power of two scaling factor makes it relatively easy
to remove the gain factor by shifting a binary decimal point.
■
Scale manually—The IIR compiler lets you manually scale the
coefficient values by a specified gain factor.
Altera Corporation
IIR Compiler MegaCore Function User Guide
■
Getting Started
No scaling—The IIR compiler can read in pre-scaled integer values for
the coefficients and not apply scaling factors.
The new set of scaled fixed point coefficient defines a new transfer
function Hfixed(z) as shown in Equation 3.
Equation 3
n
∑ aifixed Z
–1
i=0
H fixed ( z ) = -----------------------------------------n
1+
2
–i
i=1
The MegaWizard Plug In Manager plots Hfixed(z) in the Z plane. If a pole
is outside the unit circle, the filter will be unstable. The wizard graphically
plots the poles and you can adjust the scaling if any poles appear outside
the unit circle.
The IIR latency is the number of clock cycles that the IIR filter requires to
compute yout. See Figure 4.
Altera Corporation
■
If you choose zero latency, yout is combined and is calculated at the
same time that xin appears. This mode is useful for building
feedback control systems such as automatic gain control circuitry
(AGC) or digital clock and data recovery.
■
If you choose the medium latency option, yout is registered and is
calculated one clock cycle after xin appears.
■
If you choose the maximum latency option, the feed-forward path is
fully pipelined; the delay is based on the number of taps. The timing
critical path is the feedback path only.
27
Getting Started
∑ b ifi xed Z
Getting Started
IIR Compiler MegaCore Function User Guide
Figure 4. Scale the Coefficients
Figure 5 shows the simulation waveform for full latency.
Figure 5. Full Latency
Figure 6 shows the simulation waveform for medium latency.
28
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IIR Compiler MegaCore Function User Guide
Getting Started
Figure 6. Medium Latency
2
Getting Started
Figure 7 shows the simulation waveform for no latency.
Figure 7. No Latency
Data Path Width Wizard Page
On this page you can simulate the hardware architecture using a bitaccurate system model. After setting the value of the scaled coefficients,
the wizard lets you adjust the internal hardware architecture nodes for
both the feedback and feed-forward paths. Use the slider bar to adjust the
settings for both paths (you can also use the Satur and Round checkboxes
to perform those functions). See Figure 4.
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Getting Started
IIR Compiler MegaCore Function User Guide
Figure 8. Simulate the Hardware Architecture
The finite word length of the feedback and feed-forward paths may
introduce non-linearity in the Hfixed(z) transfer function. Therefore, the
wizard lets you perform additional analysis and dynamically displays
plots according to the settings you specify. You can view the plots in
frequency or time, depending on which tab you select.
Simulation Setting
If you choose the Fixed Point model response option the wizard plots (in
blue) the bit-accurate simulation result of the IIR filter that will be
implemented in the device. If you choose the Floating Point option the
wizard plots (in red) the simulation result of the floating-point IIR filter
that was specified on the coefficients wizard page. See Figure 9.
30
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IIR Compiler MegaCore Function User Guide
Getting Started
Figure 9. Simulation Settings
2
Getting Started
You can toggle the view between frequency and time using tabs. Four
input stimuli can be applied:
■
■
■
■
Impulse
Step
White Noise—A new input white noise stimuli is generated every
time you click on the white noise radio button.
From a File—You can import xin values from an ASCII text file; the
floating-point values can be generated from the MATLAB software or
any other third-party tool. The result of the simulation is
–
In the time domain (up to 512 samples)
–
In the frequency domain
–
In the ASCII file MYout.txt (up to the number of samples present
in the initial xin file).
The xin values are scaled and used for the MATLAB testbench or for the
Quartus or MAX+PLUS II Vector File simulus.
The xin and yout options switch the plot from input data of the IIR filter
or output data of the IIR filter, respectively.
Plotting
The Time Response tab displays the time response of the filter. The X axis
represents the sample number in time and the horizontal slider bar
controls the simulation time length. The maximum simulation time length
is 512 samples. For extended simulation time, Altera recommends you use
either the bit-accurate MATLAB model generated by the wizard or the
Quartus or MAX+PLUS II VHDL or Verilog HDL output file.
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Getting Started
IIR Compiler MegaCore Function User Guide
Frequency Response
The Y axis represents the amplitude of the filter response. The vertical
slider bar zooms the response view in and out. The Y axis scale represents
the dB attenuation of the filter based on the coefficients. A slider bar
allows you to zoom the Y axis in and out. The X axis is an absolute
frequency, which is the ratio of the filter frequency characteristic over the
sample frequency. See Figures 10 and 11.
1
To use the Up, Down, Left, and Right arrows on your keyboard
to move the slider bars, click on the slider bar to select it.
Figure 10. Time Response
Figure 11. Frequency Response
32
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IIR Compiler MegaCore Function User Guide
Getting Started
Structure Setting
This section controls of the bit width of the feed-forward and feedback
data of the IIR filter. See Figure 12.
Figure 12. Structure Settings
2
Getting Started
The Delay Line Width box sets the width of the delay element of the IIR
filter. This global parameter applies to the cascaded and parallel
structures; the tap delay line of each biquad has the same delay line width.
Feedback Bit Width Control
The output feedback data path (fb) is defined by Equation 4 and shown in
Figure 13.
Equation 4
n
fb n =
∑ – bifixed yout ( n – i )
i=1
Figure 13. Feedback Settings
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Getting Started
IIR Compiler MegaCore Function User Guide
bifixed are the scaled coefficients of the feedback data path, fb is added to
the incoming input data (xin). This adder width is equal to the delay line
width. Therefore, the number of bits fb uses for this addition is smaller
than the number of bits required to compute Equation 4 (full precision). A
slider bar lets you select the slice of the fb bus that is added to xin. When
the least significant bits (LSBs) are dropped you can choose to round or
truncate using the Satur or Round options, respectively. When the most
significant bits (MSBs) are dropped and possible overflows may occur,
you can choose to saturate or truncate by turning the Satur option on and
off, respectively. Saturation or rounding can reduce the bit width needed
for the tap delay line at the cost of increasing the feedback data path delay.
The effect of modifying any of these parameters is displayed in the
simulation area.
Feed-Forward Bit Width Control
The output feedforward data path (ff) is defined by Equation 5 and shown
in Figure 14.
Equation 5
n
ff n =
∑ aifixe d xin( n – i)
i=1
Figure 14. Feedforward Settings
aifixed are the scaled coefficients of the feed-forward data path. If the Full
Precision option is turned on the wizard computes the number of bits
required for Equation 5, which is the full output resolution bit width.
When the option is turned off you can choose an output bit width greater
or smaller than the full precision.
34
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IIR Compiler MegaCore Function User Guide
Getting Started
For a smaller number of bits, the output slider bar allows you to select the
slice of ff to keep. When LSBs are dropped you can choose to round or
truncate using the Satur or Round options, respectively. When MSBs are
dropped and possible overflows may occur, you can choose to saturate or
truncate by turning the Satur option on and off, respectively. Saturation
or rounding may reduce the bit width needed for the tap delay line at the
cost of increasing the feedback data path delay. The effect of modifying
any of these parameters is instantly displayed in the simulation area.
Guidelines
2
■
First, use full precision for the output feed-forward data path.
Choose the Impulse stimulus and the time domain plot.
■
Compare the fixed-point and floating-point views, adjusting the
width parameter of the feedback path.
a.
Choose the Step stimulus in the time domain plot. Tune the
parameters.
b.
Choose the white noise stimulus in the frequency domain,
adjusting the feedback parameters as needed.
c.
Reduce the output precision of the feed-forward path to find the
match.
If, after following the steps above, you cannot find any matching fixedpoint filters, you can increase the coefficient bit width and the delay line
bit width or change architectures (cascade or parallel).
Simulate in
MATLAB
You can use the wizard-generated files to simulate the filter in the
MATLAB software. The generated MATLAB model requires a library file,
iirtrim.dll, which is saved into the \iircompiler\simlib\matlab
directory when you install the IIR compiler. This file must be located in
the MATLAB path or copied into your MATLAB working directory.
Execute <your filter name> at the MATLAB prompt. This action runs the
MATLAB simulation of the bit-accurate model, plots the frequency and
phase response, and shows the three-plane representation of the scaled
coefficients. Figure 15 shows an example of analyzing the IIR phase of the
fixed-point MATLAB filter generated by the wizard.
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Getting Started
Setting the most optimum bitwidth parameters consists of finding the
values of the slide bars/combo box/check box width so that the
simulation response of the fixed-point model is as identical as possible to
the initial floating-point model. Use the following guidelines when you
set the bitwidth parameters of the fixed-point IIR filter.
Getting Started
IIR Compiler MegaCore Function User Guide
Figure 15. MATLAB Analysis
Compiling,
Simulating &
Device
Configuration
Once you have generated the IIR filter variation, you can implement the
whole system, simulate the design, compile in the Quartus or
MAX+PLUS II software, and configure a device.
Implement the System
When you are finished simulating your system, you are ready to
implement it. You can use the design files generated by the IIR compiler
wizard in your design. The wizard outputs an AHDL Text Design File
(.tdf) and a Symbol File (.sym). You can use the MAX+PLUS II software,
Quartus software, or other EDA tools to create your design.
36
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IIR Compiler MegaCore Function User Guide
Getting Started
Simulate Using VHDL & Verilog HDL Models
The IIR compiler wizard generates VHDL and Verilog HDL simulation
models. You can use these models to perform simulations of your system
using third-party EDA tools.
Compiling & Simulating in the Quartus Software
The following steps explain how to compile and simulate your design in
the Quartus software, and use the test vector configuration file.
Click Start Compilation (Processing Menu) to compile your design.
2.
Click Simulation Mode (Processing menu). Choose Simulator
Settings (Processing menu) and select the Time/Vectors tab.
Uncheck Automatically add Pin to Simulation Output Waveforms.
In the Source of Vector Stimuli box, select <output name>.vec, where
<output name> is the name you specified in the MegaWizard Plug-In.
Click OK.
3.
Click Run Simulation (Processing menu) to begin simulation.
Compiling & Simulating in the MAX+PLUS II Software
The following steps explain how to compile and simulate your design in
the MAX+PLUS II software.
1.
In the MAX+PLUS II Compiler, turn on Functional SNF Extractor
(Processing menu).
2.
Click Start to compile your design.
3.
Run the MAX+PLUS II Simulator. The vector file created by the
MegaWizard Plug-In Manager for your custom IIR compiler
function is loaded automatically. Click Start to begin simulation.
4.
Once simulation has completed, click the Open SCF button to view
the waveform for the design.
After you have verified that your design is functionally correct, you are
ready to perform system verification.
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2
Getting Started
1.
Getting Started
IIR Compiler MegaCore Function User Guide
Performing Synthesis, Compilation & Post-Routing Simulation
The Quartus and MAX+PLUS II software work seamlessly with tools
from all EDA vendors, including Cadence, Exemplar Logic, Mentor
Graphics, Synopsys, Synplicity, and Viewlogic. After you have licensed
the MegaCore function, you can generate EDIF, VHDL, Verilog HDL, and
Standard Delay Output Files from the Quartus or MAX+PLUS II software
and use them with your existing EDA tools to perform functional
modeling and post-route simulation of your design.
The following sections describe the design flow to compile and simulate
your custom MegaCore design with a third-party EDA tool. To synthesize
your design in a third-party EDA tool and perform post-route simulation,
perform the following steps:
1.
Create your custom design instantiating a IIR compiler MegaCore
function.
2.
Synthesize the design using your third-party EDA tool. Your EDA
tool should treat the MegaCore instantiation as a black box by either
setting attributes or ignoring the instantiation.
1
For more information on setting compiler options in your
third-party EDA tool, refer to the MAX+PLUS II ACCESS
Interfaces Guidelines.
3.
After compilation, generate a hierarchical netlist file in your thirdparty EDA tool.
4.
Open your netlist file in the Quartus or MAX+PLUS II software.
For the Quartus Software
38
1.
Select Compile mode (Processing Menu).
2.
Specify the Compiler settings in the Compiler Settings dialog box
(Processing menu) or use the Compiler Settings wizard.
3.
Specify the user libraries for the project and the order in which the
compiler searches the libraries.
4.
Specify the input settings for the project. Choose EDA Tool Settings
(Project menu). Select Custom EDIF in the Design entry/synthesis
tool list. Click Settings. In the EDA Tool Input Settings dialog box,
make sure that the relevant tool name or option is selected in the
Design Entry/Synthesis Tool list.
Altera Corporation
IIR Compiler MegaCore Function User Guide
Getting Started
5.
Depending on the type of output file you want, specify Verilog HDL
output settings or VHDL output settings in the General Settings
dialog box (Project Menu). Use the 1993 VHDL language option.
6.
Compile your design. The Quartus Compiler synthesizes and
performs place-and-route on your design, and generates output and
programming files.
7.
Import your Quartus-generated output files (.edo, .vho, .vo, or .sdo)
into your third-party EDA tool for post-route, device-level, and
system-level simulation.
Getting Started
For the MAX+PLUS II Software
f
Altera Corporation
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1.
Set your EDIF file as the current project.
2.
Choose EDIF Netlist Reader Settings (Interfaces menu).
3.
In the EDIF Netlist Reader Settings dialog box, select the vendor for
your EDIF netlist file in the Vendor drop-down list box and click
OK.
4.
Make logic option and/or place-and-route assignments for your
custom logic using the commands in the Assign menu.
5.
In the MAX+PLUS II Compiler, make sure Functional SNF Extractor
(Processing menu) is turned off.
6.
Turn on the Verilog Netlist Writer or VHDL Netlist Writer
command (Interfaces menu), depending on the type of output file
you want to use in your third-party simulator. Use the 1993 VHDL
language option.
7.
Compile your design. The MAX+PLUS II Compiler synthesizes and
performs place-and-route on your design, and generates output and
programming files.
8.
Import your MAX+PLUS II-generated output files (.edo, .vho, .vo, or
.sdo) into your third-party EDA tool for post-route, device-level, and
system-level simulation.
For more information on setting compiler options in your third-party
EDA tool, refer to the MAX+PLUS II ACCESS Key Guidelines.
39
Configuring a Device
Notes:
References
After you have compiled and analyzed your design, you are ready to
configure your targeted Altera FLEX device. If you are evaluating the
MegaCore function with the OpenCore feature, you must license the
function before you can generate configuration files.
Arthur Bernard Williams, Fred J. Taylor. Electronic Filter Design
Handbook, 2nd ed. McGraw-Hill Companies, November 1988.
Madisetti, Vijay. VLSI Digital Signal Processors: An Introduction to
Rapid Prototyping and Design Synthesis. Butterworth-Heinemann,
November 1994.
Vaidyanathan, P. P. Multirate Systems and Filter Banks. Simon &
Schuster Trade, October 1992.
Bingham, John A. C. The Theory and Practice of Modem Design. Wiley,
John & Sons, Incorporated, November 1990.
William H. Press , Saul A. Teukolsky , William T. Vetterling, Brian P.
Flannery. Numerical Recipes in C : The Art of Scientific Computing. The
Press Syndicate of the University of Cambridge, October 1992.
Luc Semeria Abhijit Ghosh. Methodology for Hardware/Software Coverification in C/C++.
The MathWorks, Inc. Signal Processing Toolbox User’s Guide. Natick,
MA. September 2000.