®
Design Software &
Development Kit
Selector Guide
January 2003
Introduction
SOPC Builder
As FPGAs evolve to include system-level building blocks within the device—such as high-speed I/O circuitry, multi-gigabit
transceivers, embedded processors, digital signal processing
(DSP) blocks, and embedded memory blocks—the design tools
for these devices must extend their capabilities with new
methodologies that support system-level and block-based
design. Altera offers industry-leading design software and
development kits that provide a complete design environment
for developing system-on-a-programmable-chip (SOPC) solutions. This selector guide will help you choose the Altera®
design environment that best meets your needs. It describes:
SOPC Builder is an automated system-generation tool
integrated with the Quartus II design environment. SOPC
Builder rapidly generates a custom embedded microprocessor
system and supports system-level architecture changes to
analyze performance tradeoffs. Using the wizard-based
SOPC Builder (depicted in Figure 1), you can easily select
and customize system-level building blocks, including
Excalibur™ devices and Nios® embedded processors,
intellectual property (IP) cores, software libraries, and userdefined building blocks. SOPC Builder automatically
connects the hardware components using high-performance
on-chip bus architectures, and then customizes software
components to match the hardware.
• Altera’s design software products (page 2)
• Altera Design Software Subscription Program (page 3)
• Design software products (page 5)
Figure 1. SOPC Builder
• Recommended system configurations (page 8)
SOPC
Builder
• Altera programming hardware (page 9)
• Altera development kits (page 9)
• Third-party products that complement Altera software
and hardware products (page 11)
Quartus II Design Software
The Altera Quartus® II design software
is the most comprehensive environment
available for SOPC design. The Quartus II
software environment supports systemlevel design, embedded processor software development,
FPGA and CPLD design, synthesis, place-and-route, verification, and device programming. The Quartus II software
now includes exclusive timing closure and LogicLock™
block-based design flows as standard features. These features
increase designer productivity, and shorten design and
verification cycles. The Quartus II software also supports
Altera’s SOPC Builder system development and integration
software (included in subscriptions) and the DSP Builder
interface (available separately) between the Quartus II
software and the The MathWorks MATLAB and Simulink
products. These tools provide powerful system-level design
and analysis capabilities. The Quartus II software now
supports all Altera FPGAs as well as CPLDs recommended
for new designs (see Table 2 on page 5).
2
UART
Timer
CPU
RAM
Interface Architecture
User Logic
IP
User DSP
IP
Synthesis & Simulation Included with
Subscriptions
Altera-specific versions of the
Mentor Graphics® LeonardoSpectrum™
and the Model Technology™ ModelSim®
synthesis and simulation tools are included with all Altera
design software subscriptions. You can select support for
either the VHDL or Verilog hardware description language
(HDL). You can also use the synthesis and simulation tools
included in the Quartus II design software. For a list of the
third-party EDA software compatible with Altera design
software, see the “Third-Party Solutions" section of this
selector guide on page 11.
Altera Corporation
Support for Embedded Processor Designs
Altera’s embedded processor solutions
integrate hard and soft core embedded
processors, on-chip or off-chip memory,
peripherals, and programmable logic on a
single device. Altera is the first company to
offer embedded processor development and
debugging tools as well as programmable logic development
in a single integrated environment. All Altera design
software subscriptions now include the GNUPro C/C++
tools to develop and debug software that runs on Excalibur
devices or Nios embedded processors. These development
and debugging tools are integrated with the Quartus II
design software and can be run directly through the
Quartus II software user interface.
Altera Design Software
Subscription Program
Altera design software is available as part of a comprehensive
software suite under the Altera Design Software Subscription
Program. Subscribing to the Altera Design Software Subscription
Program provides you with the software necessary to perform
the following activities for all Altera PLDs:
•
System-level design
•
Embedded software development
•
FPGA & CPLD programmable logic design
•
Synthesis
•
Place-and-route
The Quartus II software also includes a suite of simulation
models for Altera's embedded processor solutions. These
simulation models can be used with ModelSim-Altera software and other third-party simulation products to simulate
a complete system, including embedded processor software,
memory, and custom programmable logic. Simulation
models included with Altera design software subscriptions
range from bus functional models for peripheral development,
very fast functional simulation and instruction set simulation
models for quick hardware/software co-simulation, and
cycle-accurate models to verify the processor and PLD
system’s exact operation.
•
Verification
•
Device programming
•
Model Technology ModelSim-Altera simulation software
DSP Builder
•
Excalibur embedded processor design software
Digital signal processing (DSP) system design in Altera
FPGAs requires both high-level algorithms and HDL development tools. The Altera DSP Builder integrates these tools
by combining the algorithm development, simulation, and
verification capabilities of The MathWorks MATLAB and
Simulink system-level design tools with synthesis, simulation, and Altera design software. DSP Builder shortens
DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly
development environment. You can combine existing
MATLAB functions and Simulink blocks with Altera DSP
Builder blocks and Altera IP MegaCore® functions to link
system-level design and implementation with DSP algorithm
development. DSP Builder allows system, algorithm, and
hardware designers to share a common development
platform. DSP Builder, shown in Figure 2 on page 4, is
available from Altera.
•
MAX+PLUS® II design software
Altera Corporation
Your subscription provides complete access to Altera design
software and updates for one year, and includes the following
software products:
•
Altera Quartus II design software
•
SOPC Builder system definition and construction software
•
Mentor Graphics LeonardoSpectrum-Altera synthesis software
Descriptions for each software product included in Altera
software subscriptions appear throughout this selector guide.
If your subscription expires, your current Altera software will
continue to work, but you will not receive the updates and
new features offered in subsequent software releases. You can
further enhance the value of your software subscription by
purchasing an Altera development kit (page 9), adding the
Altera DSP Builder system-level design software, or purchasing
Altera Megafunction Partners Program (AMPPSM) partner or
Altera IP. For more information on Altera IP, visit the Altera
web site at www.altera.com.
Figure 2. DSP Builder
Selecting a Design Software
Product
Altera subscription products are based on the operating
system (OS), network environment, and number of enabled
users. Select the subscription product that best suits your
needs from Table 1.
Altera Device Support
Together, the Quartus II and MAX+PLUS II design software
support all the Altera FPGA and CPLD families, as shown in
Table 2. The 12-month Altera Design Software Subscription
Program comes with both design tools.
MAX+PLUS II Design Software
The MAX+PLUS II design software offers a variety of
options for design entry, compilation, verification, and
programming for legacy designs. This easy-to-use tool
supports the Altera ACEX®, FLEX®, MAX®, and mature
PLD families, and integrates with industry-standard design
entry, synthesis, and verification tools. For details about the
MAX+PLUS II software features, see Table 4 on page 6.
Free Design Software
The Quartus II Web Edition and MAX+PLUS II BASELINE
software support the low- to mid-density devices listed in
Table 2. Table 3 shows the free Altera design software
options.
Altera Design Software Feature
Comparisons
Table 4 on page 6 describes each design software feature and
compares the Quartus II, MAX+PLUS II, Quartus II Web
Edition, and MAX+PLUS II BASELINE software.
You can download and license the Quartus II Web Edition
and MAX+PLUS II BASELINE software free of charge from
the Altera web site. The Quartus II Web Edition software
is a subset of the Quartus II software that provides entrylevel support for the Cyclone™, Stratix™, Excalibur,
APEX™ II, APEX 20KE, FLEX 10KE, ACEX, FLEX 6000,
MAX 7000B, MAX 7000AE, and MAX 3000A devices.
The MAX+PLUS II BASELINE software is a subset of the
MAX+PLUS II software targeted at the industry’s most
popular product-term architectures—the MAX 7000 and
MAX 3000 devices—as well as mature Altera devices.
4
Altera Corporation
Table 1. Selecting a Design Software Product
PLATFORM SUPPORT
TYPE OF LICENSE
ORDERING CODE
PC
Stand-alone, single-user
FIXEDPC
PC
Multiple-user network license (one concurrent user)
FLOATPC
PC, Solaris, HP-UX
Multiple-user network license (one concurrent user)
FLOATNET
PC, Red Hat Linux 7.1
Multiple-user network license (one concurrent user)
FLOATLNX
PC
Add additional concurrent PC users
ADD-FLOATPC
PC, Solaris, HP-UX
Add additional concurrent PC, Solaris, or HP-UX users
ADD-FLOATNET
PC, Red Hat Linux 7.1
Add additional PC or Red Hat Linux 7.1 concurrent users
ADD-FLOATLNX
Same as original subscription
One-year extension for FIXEDPC, FLOATPC, FLOATNET, FLOATLNX,
ADD-FLOATPC, ADD-FLOATNET licenses
RENEWAL
Note: Purchase one FLOATPC, FLOATNET, FLOATLNX, or ADD-FLOATLNX product and purchase ADD-FLOATPC, ADD-FLOATNET, or ADD-FLOATLNX products to add
support for additional concurrent users on the same network.
Table 2. Altera Design Software Device Support
DEVICE
QUARTUS II
Stratix (All)
✔
Stratix EP1S10
✔
Stratix GX (All)1
✔
Cyclone (All)
✔
APEX II (All)
✔
APEX II EP2A15
✔
APEX 20K (All)
✔
APEX EP20K30E, EP20K60E, EP20K160E
✔
Mercury™ (All)
✔
MAX+PLUS II
QUARTUS II
WEB EDITION
MAX+PLUS II
BASELINE
✔
✔
✔
✔
✔
FLEX 10K (All)
✔
FLEX EPF10K30E, EPF10K50S, EPF10K100E
FLEX EPF10K130E, EPF10K200S
✔
✔
✔
EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A
✔
Excalibur (All)
✔
Excalibur EPXA1
✔
ACEX (All)
✔
✔
✔
FLEX 6000 (All)
✔
✔
✔
✔
MAX 9000 (All)
✔
MAX 7000 (All)
✔
✔
✔
MAX 7000B, MAX 7000AE
✔
✔
✔
✔
MAX 3000 (All)
✔
✔
✔
✔
Note: 1 Contact your local Altera sales office to enable Stratix GX support.
Table 3. Free Altera Design Software
DESIGN SOFTWARE
LICENSE TYPE
TOOLS INCLUDED
PLATFORM
SUPPORT
LICENSE
DURATION
Quartus II Web Edition
Stand-alone, single-user
Quartus II Web Edition,
LeonardoSpectrum-Altera
PC
150 Days
Software will not run until
a new license is requested
MAX+PLUS II BASELINE
Stand-alone, single-user
MAX+PLUS II BASELINE,
LeonardoSpectrum-Altera
PC
180 Days
Software will not run until
a new license is requested
Altera Corporation
EXPIRATION
5
Synthesis
FPGA Design
Embedded
Software
System-Level
Design
6
X+
PLU
SI
QU
I
A
W E RTU
S
B E II
DI
TIO
MA
N
X+
B A PLU
SE
L I N S II
E
DESCRIPTION
MA
FEATURE
QU
AR
TU
SI
I
Table 4. Software Feature Comparisons (Part 1 of 2)
SOPC Builder Support
Automates system definition and development. SOPC Builder is now
included with subscriptions.
✔
✔
DSP Builder Support
Provides interface between the Altera design software and The Mathworks
MATLAB and Simulink tools for DSP designers. DSP Builder is available
from Altera.
✔
✔
Embedded Software
Integration
Integrates embedded software C/C++ development tools and debuggers for
Excalibur embedded processor solutions.
✔
✔
LogicLock Block-Based
Design Methodology
Increases designer productivity and shortens design and verification cycles.
Altera offers the only PLD design software to include block-based design
methodologies as a standard feature.
✔
NativeLink® Integration
Offers seamless interface for passing information and design processing
between the Quartus II software and third-party EDA software.
✔
Text-Based Design Entry
Provides colored syntax-sensitive editors for VHDL, Verilog HDL, and Altera
Hardware Description Language (AHDL) development.
✔
✔
✔
✔
Schematic Design Entry
Allows you to use basic graphical building blocks for creating a design.
✔
✔
✔
✔
Block Design Entry
Allows you to edit design information in graphical format and
automatically convert to a VHDL or Verilog file for synthesis and
simulation using industry-standard tools.
✔
Library of Parameterized
Modules (LPM)
Offers parameterized functions that can be used as building blocks to
simplify design entry and increase performance.
✔
Tool Command Language (Tcl)
Scripting and Synopsys Design
Constraints (SDC) Support
Allows design flow automation and the ability to make device assignments
using industry-standard Tcl scripts and SDC.
✔
MegaWizard Plug-In
Manager
Provides graphical-driven tools that can be used stand-alone or within the
design software to parameterize and instantiate LPM, MegaCore, and Altera
Megafunction Partners Program (AMPP) megafunctions.
✔
✔
✔
✔
MegaCore Functions
Offers pre-verified HDL design files for complex, system-level functions
optimized for Altera device architectures.
✔
✔
✔
✔
VHDL and Verilog Synthesis
Integrates VHDL and Verilog HDL synthesis.
✔
Third-Party Synthesis
Support
Includes LeonardoSpectrum-Altera synthesis software and support for thirdparty synthesis software from Mentor Graphics, Synopsys, and Synplicity
with all subscriptions.
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Altera Corporation
Device Programming
Standard Support
Verification
Place & Route
X+
PLU
SI
QU
I
A
WE RTU
S
BE
DIT II
ION
MA
X+
BA PLU
SEL S
INE II
DESCRIPTION
MA
FEATURE
QU
AR
TU
SI
I
Table 4. Software Feature Comparisons (Part 2 of 2)
PowerFit™ Place-and-Route
Uses your timing constraints to optimally place-and-route a design to
satisfy all timing requirements.
✔
Fast Fit
Reduces compile times up to 50%.
✔
Timing Closure Flow
Simplifies the process of analyzing and removing system bottlenecks to
maximize performance.
✔
Timing Closure Floorplan
Editor
Displays physical timing estimates between nodes, LogicLock region
connectivity in real time, displays routing congestion, and includes a
graphical method for assigning logic cells and pins.
✔
Netlist Optimizations
Applies re-synthesis optimizations, gate-level register retiming, and register
duplication to improve push-button performance results.
✔
OpenCore® Evaluation
Enables you to compile and simulate MegaCore and AMPP parameterized
functions before licensing the function.
✔
✔
✔
✔
Static Timing Analysis
Allows you to determine the speed-critical and performance-limiting paths
in a design and optimize critical timing paths.
✔
✔
✔
✔
Functional Simulation
Allows you to simulate the logical function of a design with zero
propagation delays.
✔
✔
✔
✔
Timing Simulation
Allows you to simulate the logical function and worst-case timing of a fully
synthesized and optimized design.
✔
✔
✔
✔
ModelSim-Altera
Simulates HDL code using a VHDL or Verilog HDL testbench stimuli.
✔
✔
Testbench Generation
Converts waveform simulation file to testbench file. Automatically creates
a testbench template after compilation to jump-start testbench development.
✔
SignalTap® II Logic
Analysis
Captures and analyzes state of internal nodes or I/O signals of devices
running in-system and at system speeds; now supports incremental routing
of additional nodes.
✔
SignalProbe™ In-System
Debugging
Incrementally routes an internal node to an unused or reserved pin for
analysis with an external scope or logic analyzer.
✔
IBIS Model Generation
Outputs design-specific input/output buffer information specification (IBIS)
models to third-party software for signal integrity and EMC analysis.
✔
Hardware/Software
Co-Simulation Support
Outputs simulation models to simulate complete systems including
programmable logic, embedded processor, embedded processor software,
and memory.
✔
Formal Verification
Supports third-party formal verification software that can identify
functional differences between source RTL netlists and post-place-and-route
netlists without the creation of test vectors.
✔
PowerGauge™ Power
Analysis
Links power consumption estimates with user-specific design files and
operating parameters.
✔
IEEE 1532
Supports IEEE 1532 standard for programming devices in-system via the
IEEE 1149 standard JTAG interface.
✔
Jam™ STAPL
Supports JEDEC-approved Jam STAPL standard for programming devices
in-system via the IEEE 1149 standard JTAG interface.
✔
Altera Corporation
✔
✔
✔
✔
✔
✔
✔
7
Recommended System
Configurations
You will need the following components to operate Altera
design software on Windows-based or Linux-based PCs,
Sun workstations, or HP workstations, as listed below under
each system type. Table 5 lists the memory requirements for
Altera devices.
Windows-Based or Linux-Based PC
●
Pentium II 400 with 512-Mbyte system memory (faster
systems provide better software performance)
■
Operating System Software
■
Microsoft Windows XP
■
Microsoft Windows 2000
■
Microsoft Windows NT version 4.0 or later
■
Microsoft Windows 98
■
Red Hat Linux Version 7.1 (Quartus II software only)
●
SVGA monitor
●
CD-ROM drive
●
Serial port (or USB port if using Windows 98, Windows XP,
Windows 2000) for the MasterBlaster™ download cable
●
Parallel port for use with the ByteBlaster™ II or
ByteBlasterMV™ download cables
●
Internet Explorer 5.0 or later
Sun Workstation
●
Sun Ultra workstation with color monitor running
Solaris version 2.6, 7, or 8
●
ISO 9990-compatible CD-ROM drive
●
A valid X-Windows display
●
Netscape Navigator 5.0 or later or Internet Explorer 5.0
or later
HP Workstation
●
HP 9000 700/800 Workstation with color monitor
running HP-UX version 11.0 with the Additional Core
Enhancements (ACE) dated November 1999 or later
●
ISO 9990-compatible CD-ROM drive
●
A valid X-Windows display
●
Netscape Navigator 5.0 or later or Internet Explorer 5.0
or later
Beginning June 1, 2003, the Quartus II and MAX+PLUS II
software packages will not support Microsoft Windows 98
and Sun Solaris 2.6; however, customer support for these
operating systems will continue until December 31, 2003.
Table 5. Memory Requirements
FAMILY
Stratix
DEVICE
EP1S10, EP1S20, EP1S25
EP1S30, EP1S40, EP1S60
Stratix GX
APEX 20K
APEX 20KE
APEX 20KC
Excalibur
512 Mbytes
512 Mbytes
1 Gbyte
1 Gbyte
1.5 Gbytes
1.5 Gbytes
EP1SGX10C, EP1SGX10D, EP1SGX25C, EP1SGX25D, EP1SGX25F
512 Mbytes
512 Mbytes
1 Gbyte
1 Gbyte
EP1C3, EP1C6
256 Mbytes
256 Mbytes
EP1C12, EP1C20
512 Mbytes
512 Mbytes
EP20K100, EP20K100E, EP20K160E, EP20K200, EP20K200C,
EP20K200E, EP20K30E, EP20K60E
256 Mbytes
256 Mbytes
EP20K300E, EP20K400, EP20K400C, EP20K400E,
EP20K600C, EP20K600E
512 Mbytes
512 Mbytes
1 Gbyte
1 Gbyte
EP2A15, EP2A25, EP2A40
512 Mbytes
512 Mbytes
EP2A70
1.5 Gbytes
1.5 Gbytes
EPXA1
256 Mbytes
256 Mbytes
EPXA4
512 Mbytes
512 Mbytes
EP20K1000C, EP20K1000E, EP20K1500C, EP20K1500E
APEX II
MINIMUM
SWAP SPACE1
EP1S80
EP1SGX40D, EP1SGX40F
Cyclone
MINIMUM
PHYSICAL RAM
1 Gbyte
1 Gbyte
FLEX 10KE, FLEX 6000
MAX 7000, MAX 3000
ACEX
EPXA10
All
256 Mbytes
256 Mbytes
Mercury
EP1M120
256 Mbytes
256 Mbytes
EP1M350
512 Mbytes
512 Mbytes
Note: 1 Minimum additional swap space on hard disk drive.
8
Altera Corporation
Altera Programming
Hardware
Altera Development Kits
Altera’s MasterBlaster, ByteBlasterMV, and ByteBlaster II
configuration cables, described in Table 6, are available for
in-circuit reconfiguration of Cyclone, Stratix, Stratix GX,
APEX II, APEX 20K, Excalibur, FLEX 10K, ACEX, FLEX 6000,
and Mercury products, and in-system programming of
MAX 7000, MAX 3000, and MAX 9000 devices. The configuration cables download device data directly from the
Altera design software user interface or directly from a
system prompt. When used with the Quartus II software,
the MasterBlaster, ByteBlasterMV, and ByteBlaster II configuration cables also provide communication for the
SignalTap® II embedded logic analyzer included in the
Quartus II software. For a description of the SignalTap II
embedded logic analyzer, see Table 4 on page 6 or visit
the Design Software section of the Altera web site.
The Altera Programming Unit (APU), used with the appropriate programming adapters, provides the hardware and
software needed for programming all Altera devices. Use
Table 6 to select the appropriate programming hardware
for your system. A complete list of adapters for the APU is
available on the Development Kits/Cables section of the
Altera web site.
Altera development kits provide a platform to quickly
transition concepts into working designs. Altera development kits also speed system design by allowing application software development to begin earlier in the design
flow. In addition to a high-quality development board
designed around Altera’s state-of-the-art FPGAs, many
Altera development kits include:
●
On-board memory
●
Industry-standard I/O ports
●
Power supply
●
A version of the Quartus II design software
●
SOPC Builder system development tool
●
Embedded processor C/C++ development tools
●
ByteBlasterMV or ByteBlaster II download cable
●
Technical documentation
●
Reference designs
Altera and its partners offer a wide range of development
kits, each addressing particular discipline challenges. For
example, the DSP Development Kit (Professional Version)
is a prototyping platform that provides wireless system
designers with a solution for signal processing design,
whereas the Nios and Excalibur Development Kits cover a
broad range of embedded applications.
Table 7 on page 10 shows a sample of the Altera development kits that are available to help speed your product to
market. Visit the Altera web site for a list of the latest
development kits available from Altera and its partners.
Table 6. Altera Programming Hardware
ORDERING CODE
HARDWARE
HARDWARE
INTERFACE
ADDITIONAL FEATURES
PL-BYTEBLASTERMV
ByteBlasterMV parallel
download cable
PC parallel port
Supports the SignalTap II embedded logic analyzer as well as
3.3- and 5.0-V operation.
PL-BYTEBLASTER2
ByteBlaster II parallel download
cable
PC parallel port
Supports the SignalTap II embedded logic analyzer as well as
1.8-, 2.5-, 3.3- and 5.0-V operation. Also supports Altera's
latest low-cost serial configuration devices used with Cyclone
FPGAs .
PL-MASTERBLASTER
MasterBlaster download
cable
USB/RS-232
Supports the SignalTap II embedded logic analyzer as well as
1.8-, 2.5-, 3.3-, and 5.0-V operation.
PL-APU
Altera Programming Unit (APU)
USB
Supports traditional out-of-system programming.
Altera Corporation
9
Table 7. Development Kits
DEVELOPMENT KIT
ALTERA DEVICE
FEATURED ON BOARD
Nios Development Kit,
Cyclone Edition
Cyclone EP1C20
Provides everything needed for system
development using a Nios embedded processor.
NIOS-DEVKIT-1C20
Q1 2003
Nios Development Kit,
Stratix Edition
Stratix EP1S10
Provides everything needed for system
development using a Nios embedded processor.
NIOS-DEVKIT-1S10
Q1 2003
Nios Development Kit,
Stratix Professional
Edition
Stratix EP1S40
Provides everything needed for system
development using a Nios embedded processor.
NIOS-PROKIT-1S40
Q2 2003
Nios Development Kit,
APEX Edition
APEX EP20K200E
Provides everything needed for system
development using a Nios embedded processor.
EXCALIBUR-NIOS
Now
Nios Ethernet
Development Kit
Used with
Nios Development Kit
Provides instant network connectivity for the Nios
development board with plug-in daughter card.
NIOS-EDKX
Now
Linux Development Kit
by Microtronix
Used with
Nios Development Kit
Provides complete hardware and software
platform for embedded Linux development with
the Nios embedded processor.
NIOS-LINUX-KIT
Now
Excalibur EPXA1
Starter Development
Kit
Excalibur EPXA1
Provides everything needed for hardware and
software development using Excalibur EPXA1
devices.
EPXA-DEVKIT-XA1
Now
Excalibur EPXA10 SDR
Development Kit
Excalibur EPXA10
Provides everything needed for hardware and
software development using Excalibur EPXA10
devices. Includes a single data rate (SDR)
SDRAM dual inline memory module (DIMM)
socket.
EPXA10-DEV-BOARD
Now
Excalibur EPXA10 DDR
Development Kit
Excalibur EPXA10
Provides everything needed for hardware and
software development using Excalibur EPXA10
devices. Includes and onboard double data rate
(DDR) SDRAM for high-external data rate
applications.
EPXA-DEVKIT-XA10D
Now
DSP Development Kit,
Stratix Edition
Stratix EP1S25
Provides everything needed to develop complete
SOPC solutions including the DSP Builder
software.
DSB-BOARD/S25
Now
DSP Development Kit,
Stratix Professional
Edition
Stratix EP1S80
Provides everything needed to develop complete
SOPC solutions including the DSP Builder
software.
DSB-BOARD/S80
Q1 2003
DSP Development Kit
(Starter Version)
APEX EP20K200E
Provides everything needed to develop complete
SOPC solutions. Also includes DSP Builder
software including the DSP Builder software.
DSP-BOARD/A2E
Now
DSP Development Kit
(Professional Version)
APEX EP20K1500E
Provides everything as the Starter Version of the
same name, but adds higher performance analog
devices and a larger PLD. Also includes DSP
Builder software including the DSP Builder
software.
DSP-BOARD/A15E
Now
APEX PCI
Development Kit
APEX EP20K400E
Can be used to prototype a wide variety of
custom designs coupled with any of Altera's PCI
MegaCore functions or AMPP partner cores.
PCI-BOARD/A4E
Now
APEX PCI
Development Kit
APEX EP20K1000E
Provides same as above with a larger PLD.
PCI-BOARD/A10E
Now
FLEX PCI
Development Kit
FLEX EPF10K200S
Provides same as the APEX PCI Development
Kits but with a lower-cost FLEX device.
PCI-BOARD2/S
Now
10
APPLICATIONS
ORDERING
CODE
AVAILABILITY
Altera Corporation
Third-Party Solutions
Third-Party Programming Hardware
Several third-party solutions complement Altera’s design
software and development tools. Third-party vendor support
includes synthesis and verification tools, programming
hardware, and development tools for Excalibur device
design.
A number of third-party companies supply hardware to
program and configure Altera PLDs. Third-party programming hardware suppliers include:
ACCESS Program & Partners
Altera’s Commitment to Cooperative
Engineering Solutions (ACCESS)
ACCESS PROGRAM
Program® partners include EDA vendors who have developed design entry, HDL synthesis and
simulation, design rule checker, formal verification, static timing analysis, signal-integrity-analysis, and other complementary products that support Altera FPGAs and CPLDs.
Altera design software users can take advantage of the latest EDA tools and methodologies available through the
ACCESS Program partners. Table 8 summarizes some of
the vendors and tools that support seamless NativeLink
integration with the Quartus II design software.
●
Data I/O
●
BP Microsystems
●
System General Company
For more information on the device support provided by
these companies, refer to the Development Kits/Cables
section of the Altera web site.
SM
Third-Party Support for Embedded
Processor Design
Altera software subscriptions include development
tools to support the ARM® processor in Excalibur
devices and the Nios embedded processor. In
addition, Excalibur Partner Program members offer hardware
and software co-verification tools, C/C++ compilers, debuggers, and operating systems (see Table 9 on page 12).
For the latest information on third-party tools that support
Excalibur and Nios SOPC design, refer to the Design
Software section of the Altera web site.
For a complete listing of Altera’s ACCESS Partner tools,
contact Altera or visit the Altera web site.
Table 8. Vendors & Tools that Support NativeLink Integration
DESIGN FLOW
Synthesis
Verification
Altera Corporation
VENDOR
TOOL NAME
Mentor Graphics
Precision, LeonardoSpectrum, LeonardoSpectrum-Altera
Synopsys
Design Compiler, FPGA Compiler II
Synplicity®
Synplify®, Synplify Pro®, Amplify®
Cadence
Verilog-XL, NC Verilog, NC VHDL
Innoveda
BLAST, XTK
Mentor Graphics
Tau
Model Technology
ModelSim, ModelSim-Altera
Synopsys
LEDA, PrimeTime, Scirocco, VSS, VCS
Verplex
Conformal LEC
11
Table 9. Vendors & Tools that Support Embedded Processor Design
DESIGN FLOW
Development and
Debug Tools
VENDOR
TOOL NAME
Red Hat
GNUPro development tools for Excalibur devices and the Nios processor
ARM Ltd.
ARM Development Suite (ADS) for Excalibur devices
Mentor Graphics
XRAY debugger for Excalibur devices
code|lab EDE and code|lab debug for the Nios processor
Sophia Systems
WatchPoint debugger tool for the Nios processor
Viosoft Corp.
Arriba! IDE for the Nios processor
Hardware and Software
Co-Verification
Mentor Graphics
Seamless for Excalibur devices
System Integration Tools
Beach Solutions
EASI-Integrator for Excalibur devices
Operating Systems Support
WindRiver Systems
VxWorks AE 1.1 operating system for Excalibur devices
Tornado 3.1 development tools for Excalibur devices
Accelerated Technology
Nucleus PLUS RTOS for the Nios processor and Excalibur devices
Shugyo Design Technologies
KROS operating system for the Nios processor
Micrium
µC-OS-II RTOS for the Nios processor
MiSPO Co. Ltd.
NORTi Compact Edition for the Nios processor
Microtronix Datacom Ltd.
µClinux operating system for the Nios processor
MontaVista Software Inc.
Embedded Linux operating system for Excalibur devices
OSE Systems
OSE RTOS for Excalibur devices
Lauterbach
Trace Tools for Excalibur devices
Embedded Performance Inc.
Magic Plus Trace Tools for Excalibur devices
Microtronix Datacom Ltd.
Nios OCD Solutions Kit
Agilent
Agilent Trace Tools for Excalibur devices
Real-Time Trace Tools
Altera Offices
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
USA
Telephone: (408) 544-7000
www.altera.com
Altera European Headquarters
Holmers Farm Way
High Wycombe
Buckinghamshire
HP12 4XF
United Kingdom
Telephone: (44) 1 494 602 000
Altera Japan Ltd.
Shinjuku i-Land Tower 32F
6-5-1, Nishi-Shinjuku
Shinjuku-ku, Tokyo 163-1332
Japan
Telephone: (81) 3 3340 9480
www.altera.com/japan
Altera International Ltd.
2102 Tower 6
The Gateway, Harbour City
9 Canton Road
Tsimshatsui Kowloon
Hong Kong
Telephone: (852) 2945 7000
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that
are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. ARM and the ARM Powered
logo are registered trademarks of ARM Limited. Mentor Graphics and ModelSim are registered trademarks, and LeonardoSpectrum and Model Technology are trademarks of Mentor Graphics
Corporation. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask
work rights, and copyrights.
SG-TOOLS-19