EPC16 I/O Pins
ver. 2.0
Table 1 shows the I/O pins for the EPC16 100-pin plastic quad flat pack (PQFP) package.
Table 1. EPC16 Configuration Device Pins
Pin Name
Pin Type
Input
EXCLK
Output
DCLK
Description
External clock source.
Configuration devices drive this signal to the programmable logic device
(PLD) as a configuration clock.
PLD configuration output data bus.
PLD configuration output data bus.
PLD configuration output data bus.
PLD configuration output data bus.
PLD configuration output data bus.
PLD configuration output data bus.
PLD configuration output data bus.
PLD configuration output data bus.
Configuration devices sense that OE goes high, before starting PLD
configuration.
Initiate configuration.
Connected to CONF_DONE in the PLD. The PLD will drive it low, when
OE asserted.
Joint Test Action Group (JTAG) data input.
JTAG data output.
JTAG mode selection.
JTAG clock
Select one of eight pages that contains configuration data.
Select one of eight pages that contains configuration data.
Select one of eight pages that contains configuration data.
Select 2 ms or 100 ms power-on reset (POR).
Select test mode for configuration device.
Select test mode for configuration device.
Ground pins.
No Connect pins.
100-Pin PQFP
61
11
n INIT _ CONF
nCS
Output
Output
Output
Output
Output
Output
Output
Output
Open-Drain
Input/Output
Output
Input
TDI
TDO
TMS
TCK
PGM1
PGM0
PGM2
PORSEL
TM0
TM1
GND
NC
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
Supply
No Connect
Floating (1)
BYTE# (2)
VCC
VCCW
C -WE#
Unconnected
Input
Supply
Supply
Output
F -WE#
CE#
OE#
RY/BY# (3)
Input
Input
Input
Output
F - RP#
Input
C - RP#
Output
WP#
F-A0
Input
Input
C-A0
Output
Address input to flash memory. Should be connected to F-A0 on the
board.
65
F-A1
Input
Address input to flash memory. Should be connected to C-A1 on the
board.
56
C-A1
Output
Address input to flash memory. Should be connected to F-A1 on the
board.
62
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
55
54
53
52
51
50
34
32
31
29
28
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
OE
Altera Corporation
Unconnected pins.
Flash byte enable. Connected to VCC.
Power supply pins.
Flash program/erase power supply.
Controller write enable pin. Should be connected to
F-WE# on the
board.
Flash write enable pin. Should be connected to C-WE# on the board.
Flash pin that activates the flash memory.
Flash pin that enables the drivers of flash output pins.
Flash ready busy pin. Will be asserted when write or erase operation is
completed.
Flash pin which resets the flash memory. Should be connected to CRP# on the board.
Flash pin that resets the flash memory. Should be connected to F-RP#
on the board.
Flash pin that should be tied to VCC or GND on the board.
Address input to flash memory. Should be connected to C-A0 on the
board.
73
84
88
91
96
10
9
8
23
16
60
42
44
48
35
13
14
15
66
71
40
2, 41, 58, 70, 69, 79
3, 4, 18, 19, 20, 30, 63,
64, 76, 77
7, 24, 57, 74
5
12, 22, 59, 67, 68, 92
43
33
38
78
80
37
39
72
45
75
1
EPC16 I/O Pins
ver. 2.0
Table 1. EPC16 Configuration Device Pins
Pin Name
Pin Type
Input
A13
Input
A14
Input
F-A15
C-A15
Output
F-A16
Input
C-A16
Output
A17
A18
A19
A20 (3)
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Input
Input
Input
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Description
Address input to flash memory.
Address input to flash memory.
Address input to flash memory. Should be connected to C-A15 on the
board.
Address input to flash memory. Should be connected to F-A15 on the
board.
Address input to flash memory. Should be connected to C-A16 on the
board.
Address input to flash memory. Should be connected to F-A16 on the
board.
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
Address input to flash memory.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
Data bus that interface with flash memory and controller.
100-Pin PQFP
27
26
25
21
6
17
49
47
46
36
81
83
86
89
93
95
98
100
82
85
87
90
94
97
99
1
Notes:
(1) These pins are internally connected within the package. That is why they should be left unconnected.
(2) BYTE# should be connected to VCC.
(3) A20 (pin 36) and RY/BY# (pin 37) should be floating in EPC16.
Altera Corporation
2