Bank VREF Bank Pin Name/Function Optional Function(s) Configuration F324
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Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF Bank VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function IO LVDS31p INIT_DONE IO LVDS31n IO LVDS30p CLKUSR IO LVDS30n IO VREF0B1 IO IO LVDS29p IO LVDS29n VCCIO1 GND IO DPCLK1 IO LVDS28p IO LVDS28n IO LVDS27p IO LVDS27n IO LVDS26p IO LVDS26n IO LVDS25p IO LVDS25n IO LVDS24p IO LVDS24n IO LVDS23p IO LVDS23n IO LVDS22p IO LVDS22n IO VCCIO1 GND IO LVDS21p IO LVDS21n IO LVDS20p IO LVDS20n IO LVDS19p IO LVDS19n IO LVDS18p IO LVDS18n Pin List F324 F400 C3 C2 D3 D2 D4 D1 E3 E2 C3 C2 D3 D2 D4 D1 E4 E5 F1 E4 E5 F2 F3 F4 F5 G1 G2 F6 F7 G3 G4 G5 G6 H1 F3 E3 E2 F4 F5 F2 F1 F6 G5 G1 G2 G6 G7 G3 G4 H7 H2 H3 H4 H5 H1 H2 H3 H4 J1 J2 H5 H6 DQS for x8 in DQS for x8 in the F324 the F400 DQ0L0 DQ0L1 DQ0L0 DQ0L1 DQS0L DQ0L2 DQ0L3 DQS0L DQ0L2 DQ0L3 DQ0L4 DQ0L5 DQ0L6 DQ0L7 DQ0L4 DQ0L5 DQ0L6 DQ0L7 DM0L DM0L Page 1 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF Bank VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function IO LVDS17p IO LVDS17n IO LVDS16p IO LVDS16n IO IO VREF1B1 VCCIO1 IO nCSO DATA0 DATA0 nCONFIG nCONFIG VCCA_PLL1 CLK0 LVDSCLK1p CLK1 LVDSCLK1n GNDA_PLL1 GNDG_PLL1 nCEO nCEO nCE nCE MSEL0 MSEL0 MSEL1 MSEL1 DCLK DCLK IO ASDO GND IO PLL1_OUTp IO PLL1_OUTn IO LVDS15p IO LVDS15n IO LVDS14p IO LVDS14n IO LVDS13p IO LVDS13n IO LVDS12p IO LVDS12n IO LVDS11p IO LVDS11n IO LVDS10p IO LVDS10n Pin List F324 F400 H6 J3 J4 J5 J6 J7 J8 J1 H7 J2 J5 J3 J4 K1 J6 K2 J7 K3 K7 L1 K6 K2 K3 K1 K4 K5 K6 K7 L7 L2 L5 L1 L6 L3 L4 K4 K5 L8 M8 M2 M1 M5 M6 M4 M3 M7 N6 N1 N2 N4 N3 L7 L6 L2 L3 L5 L4 DQS for x8 in DQS for x8 in the F324 the F400 DM1L DM1L Page 2 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B4 B4 B4 B4 B4 B4 B4 B4 VREF Bank VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function VCCIO1 GND IO IO LVDS9p IO LVDS9n IO LVDS8p IO LVDS8n IO LVDS7p IO LVDS7n IO LVDS6p IO LVDS6n IO LVDS5p IO LVDS5n IO LVDS4p IO LVDS4n IO LVDS3p IO LVDS3n IO DPCLK0 VCCIO1 GND IO LVDS2p IO LVDS2n IO VREF2B1 IO IO LVDS1p IO LVDS1n IO LVDS0p IO LVDS0n IO LVDS128p IO LVDS128n IO LVDS127p IO LVDS127n IO LVDS126p IO LVDS126n IO LVDS125p IO LVDS125n Pin List F324 F400 DQS for x8 in DQS for x8 in the F324 the F400 M1 N5 N7 P7 P2 P1 P6 P5 P3 P4 R1 R2 R6 R5 R3 R4 T4 DQ1L0 DQ1L0 DQ1L1 DQ1L2 DQ1L3 DQ1L1 DQ1L2 DQ1L3 DQ1L4 DQ1L5 DQS1L DQ1L4 DQ1L5 DQS1L DQ1L6 DQ1L7 DQ1L6 DQ1L7 DQ1B7 DQ1B6 DQ1B7 DQ1B6 M3 M2 M5 M4 N1 N2 M6 N7 N5 N6 N3 N4 P5 P2 P3 R1 P4 R2 R3 T2 T3 U3 V4 T4 U4 T5 U5 T2 T3 U1 U4 U2 U3 V2 V3 W3 Y4 V4 W4 T5 U5 V5 W5 Page 3 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF Bank VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function GND VCCIO4 IO DPCLK7 IO VREF2B4 IO LVDS124p IO LVDS124n IO LVDS123p IO LVDS123n IO LVDS122p IO LVDS122n IO LVDS121p IO LVDS121n IO LVDS120p IO LVDS120n IO LVDS119p IO LVDS119n IO LVDS118p IO LVDS118n GND VCCIO4 IO LVDS117p IO LVDS117n IO LVDS116p IO LVDS116n IO LVDS115p IO LVDS115n IO LVDS114p IO LVDS114n IO VREF1B4 IO LVDS113p IO LVDS113n GND VCCIO4 IO LVDS112p IO LVDS112n IO LVDS111p Pin List F324 F400 DQS for x8 in DQS for x8 in the F324 the F400 R4 R5 V6 U6 P6 P7 T6 R6 U7 V7 T7 R7 U8 V8 T8 R8 T6 T7 W6 Y6 U6 V6 W7 Y7 R7 T8 V7 U7 V8 U8 W8 Y8 DQS1B DQS1B DQ1B5 DQ1B4 DQ1B5 DQ1B4 DQ1B3 DQ1B2 DQ1B1 DQ1B0 DQ1B3 DQ1B2 DQ1B1 DQ1B0 U9 V9 R9 T9 U9 V9 T9 R9 Y9 W9 T10 U10 V10 W10 Y10 DM1B DM1B P9 U10 V10 T10 V11 U11 W11 Page 4 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF Bank VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function IO LVDS111n IO IO LVDS110p IO LVDS110n IO LVDS109p IO LVDS109n IO LVDS108p IO LVDS108n GND VCCIO4 IO LVDS107p IO LVDS107n IO LVDS106p IO LVDS106n IO LVDS105p IO LVDS105n IO LVDS104p IO LVDS104n IO LVDS103p IO LVDS103n IO LVDS102p IO LVDS102n IO LVDS101p IO LVDS101n IO VREF0B4 IO DPCLK6 GND VCCIO4 IO LVDS100p IO LVDS100n IO LVDS99p IO LVDS99n IO LVDS98p IO LVDS98n IO LVDS97p IO LVDS97n Pin List F324 F400 R10 Y11 R11 Y12 W12 T11 T12 U12 V12 P10 R11 T11 U11 V11 V12 U12 T12 R12 V13 U13 T13 R13 P12 P13 U14 T13 R13 Y13 W13 U13 V13 R14 T14 W14 Y14 U14 V14 V15 U15 Y15 W15 T14 R14 V15 U15 U16 T15 T15 T16 W16 V16 V17 U16 Y17 W17 DQS for x8 in DQS for x8 in the F324 the F400 DM0B DM0B DQ0B7 DQ0B6 DQ0B5 DQ0B4 DQ0B7 DQ0B6 DQ0B5 DQ0B4 DQS0B DQS0B DQ0B3 DQ0B2 DQ0B1 DQ0B0 DQ0B3 DQ0B2 DQ0B1 DQ0B0 Page 5 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF Bank VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function IO LVDS96n IO LVDS96p IO LVDS95n IO LVDS95p IO LVDS94n IO LVDS94p IO VREF2B3 IO GND VCCIO3 IO DPCLK5 IO LVDS93n IO LVDS93p IO LVDS92n IO LVDS92p IO LVDS91n IO LVDS91p IO LVDS90n IO LVDS90p IO LVDS89n IO LVDS89p IO LVDS88n IO LVDS88p IO LVDS87n IO LVDS87p IO GND VCCIO3 IO LVDS86n IO LVDS86p IO LVDS85n IO LVDS85p IO LVDS84n IO LVDS84p IO LVDS83n IO LVDS83p Pin List F324 F400 T16 T17 R17 R18 R15 R16 P16 P17 W18 V18 V19 U20 U18 U19 U17 T18 P15 P14 N14 N18 N17 N13 N12 N16 N15 M18 M17 M14 M15 T19 T17 R16 R19 R20 R17 R18 R15 P14 P18 P17 P16 P15 P19 P20 N14 M16 L18 L17 M13 L13 L16 L15 N18 N17 N19 N20 N16 N15 M18 M17 DQS for x8 in DQS for x8 in the F324 the F400 DQ1R7 DQ1R7 DQ1R6 DQ1R6 DQS1R DQ1R5 DQ1R4 DQS1R DQ1R5 DQ1R4 DQ1R3 DQ1R2 DQ1R1 DQ1R3 DQ1R2 DQ1R1 DQ1R0 DQ1R0 DM1R DM1R Page 6 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF Bank VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF0B3 Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function IO LVDS82n IO LVDS82p IO LVDS81n IO LVDS81p IO IO PLL2_OUTn IO PLL2_OUTp CONF_DONE CONF_DONE nSTATUS nSTATUS TCK TCK TMS TMS TDO TDO GNDG_PLL2 GNDA_PLL2 CLK3 LVDSCLK2n CLK2 LVDSCLK2p VCCA_PLL2 TDI TDI VCCIO3 IO VREF1B3 IO IO LVDS80n IO LVDS80p IO LVDS79n IO LVDS79p IO LVDS78n IO LVDS78p IO LVDS77n IO LVDS77p IO LVDS76n IO LVDS76p IO LVDS75n IO LVDS75p IO LVDS74n IO LVDS74p GND Pin List F324 F400 L14 K16 K15 K17 L12 K18 K14 K13 J18 K12 J16 J15 J12 J17 M15 M16 M20 M19 M14 M13 L13 L18 L17 L19 L16 L20 L15 K20 K14 L14 K17 K18 J14 J13 H13 H14 H15 H16 H17 K19 J13 K16 K15 J18 J17 J14 H14 J20 J19 J15 J16 H20 H19 H17 H18 DQS for x8 in DQS for x8 in the F324 the F400 DM0R DM0R Page 7 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function VCCIO3 IO IO LVDS73n IO LVDS73p IO LVDS72n IO LVDS72p IO LVDS71n IO LVDS71p IO LVDS70n IO LVDS70p IO LVDS69n IO LVDS69p IO LVDS68n IO LVDS68p IO LVDS67n IO LVDS67p IO DPCLK4 GND VCCIO3 IO LVDS66n IO LVDS66p IO IO VREF0B3 IO LVDS65n IO LVDS65p IO LVDS64n IO LVDS64p IO LVDS63n IO LVDS63p IO LVDS62n IO LVDS62p IO LVDS61n IO LVDS61p IO LVDS60n IO LVDS60p VCCIO2 Pin List F324 F400 DQS for x8 in DQS for x8 in the F324 the F400 H18 G18 G17 G13 G14 G15 G16 G12 F12 F18 F17 F13 F14 F16 F15 E17 H16 G17 G18 H15 G14 G19 G20 G15 G16 F20 F19 F15 F16 E19 E18 F18 DQ0R7 DQ0R6 DQ0R5 DQ0R4 DQ0R7 DQ0R6 DQ0R5 DQ0R4 DQ0R3 DQS0R DQ0R3 DQS0R E16 E15 D18 E14 D16 D15 C17 D17 C16 B16 B15 A15 C15 D14 F17 E17 D20 D17 D19 D18 C19 C18 C17 B18 B17 A17 C16 B16 D16 E16 DQ0R2 DQ0R1 DQ0R0 DQ0R2 DQ0R1 DQ0R0 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T0 DQ0T1 DQ0T2 DQ0T3 Page 8 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function GND IO DPCLK3 IO VREF0B2 IO LVDS59n IO LVDS59p IO LVDS58n IO LVDS58p IO LVDS57n IO LVDS57p IO LVDS56n IO LVDS56p IO LVDS55n IO LVDS55p IO LVDS54n IO LVDS54p IO LVDS53n IO LVDS53p VCCIO2 GND IO LVDS52n IO LVDS52p IO LVDS51n IO LVDS51p IO LVDS50n IO LVDS50p IO IO LVDS49n IO LVDS49p IO LVDS48n IO LVDS48p VCCIO2 GND IO LVDS47n IO LVDS47p IO VREF1B2 IO LVDS46n Pin List F324 F400 DQS for x8 in DQS for x8 in the F324 the F400 B14 C14 E13 C15 D15 B15 A15 E15 F14 A14 B14 E14 E13 C14 D14 A13 B13 C13 D13 DQS0T DQS0T DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQ0T4 DQ0T5 DQ0T6 DQ0T7 DM0T DM0T B13 A13 D13 C13 D12 C12 B12 A12 C11 D11 B11 A11 E11 C10 D10 B10 A10 E10 E12 F12 A12 B12 D12 C12 E11 A11 B11 D11 C11 D10 C10 F10 A10 Page 9 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function IO LVDS46p IO LVDS45n IO LVDS45p IO LVDS44n IO LVDS44p IO LVDS43n IO LVDS43p VCCIO2 GND IO LVDS42n IO LVDS42p IO LVDS41n IO LVDS41p IO LVDS40n IO LVDS40p IO LVDS39n IO LVDS39p IO LVDS38n IO LVDS38p IO LVDS37n IO LVDS37p IO LVDS36n IO LVDS36p IO VREF2B2 IO DPCLK2 VCCIO2 GND IO LVDS35n IO LVDS35p IO LVDS34n IO LVDS34p IO LVDS33n IO LVDS33p IO LVDS32n DEV_OE IO LVDS32p DEV_CLRn VCCINT Pin List F324 F400 D9 C9 A9 B9 B10 E10 E9 C9 D9 A9 B9 D8 C8 A8 B8 E8 E7 A7 B7 D7 C7 E6 D6 B6 C6 A6 B5 C8 D8 A8 B8 E8 F8 C7 D7 A7 B7 E7 F7 A6 B6 E6 C6 C5 D5 A4 B4 B3 C4 A17 B5 C5 D6 D5 A4 B4 B3 C4 A19 DQS for x8 in DQS for x8 in the F324 the F400 DM1T DM1T DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQS1T DQS1T DQ1T4 DQ1T5 DQ1T6 DQ1T7 DQ1T4 DQ1T5 DQ1T6 DQ1T7 Page 10 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number VREF Bank Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 Pin List F324 F400 A2 B1 B18 F10 F8 G11 G9 H10 J9 K10 L9 M10 M8 N11 N9 U1 U18 V17 V2 A2 B1 B20 H10 H12 J11 J9 K10 K12 L11 L9 M10 M12 N11 N9 W1 W20 Y19 Y2 E1 H8 K8 N8 T1 R10 R12 R8 Y16 Y5 E20 H13 K13 N13 T20 A16 A5 E1 G7 M7 P1 P11 P8 V14 V5 E18 H12 M12 P18 A14 DQS for x8 in DQS for x8 in the F324 the F400 Page 11 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number VREF Bank Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function VCCIO2 VCCIO2 VCCIO2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin List F324 F400 A5 E12 E9 A1 A16 A18 A3 B17 B2 C1 C18 F11 F9 G10 G8 H11 H8 H9 J10 J11 J8 K11 K8 K9 L10 L11 L8 M11 M9 N10 N8 T1 T18 U17 U2 V1 F11 F13 F9 A1 A18 A20 A3 B19 B2 C1 C20 G10 G11 G12 G13 G8 G9 H11 H9 J10 J12 K11 K9 L10 L12 M11 M9 N10 N12 P10 P11 P12 P13 P8 P9 V1 DQS for x8 in DQS for x8 in the F324 the F400 Page 12 of 17 Pin Information for the Cyclone™ EP1C20 Device Final version 1.1 Bank Number VREF Bank Copyright © 2003 Altera Corp. Pin Name/Function Optional Function(s) Configuration Function GND GND GND GND GND GND GND Pin List F324 F400 V16 V18 V3 V20 W19 W2 Y1 Y18 Y20 Y3 DQS for x8 in DQS for x8 in the F324 the F400 Page 13 of 17 Pin Information for the Cyclone™ EP1C20 Device version 1.1 Pin Name Pin Type (1st, 2nd, & 3rd Function) VCCIO[1..4] Power VCCINT Power VREF[0..2]B[1..4] I/O, Input VCCA_PLL[1..2] GNDA_PLL[1..2] GNDG_PLL[1..2] Power Ground Ground nSTATUS Bidirectional (opendrain) Bidirectional (opendrain) nCONFIG Input CONF_DONE DCLK DATA0 nCE nCEO ASDO nCSO INIT_DONE Pin Description Supply and Reference Pins These are I/O supply voltage pins for banks 1 through 4. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, and 3.3-V PCI I/O standards. These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, SSTL2, and SSTL3 I/O standards. Input reference voltage for banks 1-4. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. Analog power for PLLs[1..2]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Analog ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Guard ring ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Configuration and JTAG Pins This is a dedicated configuration status pin; it is not available as a user I/O pin. This is a dedicated configuration status pin; it is not available as a user I/O pin. Dedicated configuration control input. A low transition resets the target device; a low-to-high transition begins configuration. All I/O pins tri-state when nCONFIG is driven low. In passive serial configuration mode, DCLK is a clock input used to clock configuration data from an external Input (PS mode), Output source into the Cyclone device. In active serial configuration mode, DCLK is a clock output from the Cyclone (AS mode) device (the Cyclone device acts as master in this mode). This is a dedicated pin used for configuration. Dedicated configuration data input pin. Input Active-low chip enable. Dedicated chip enable input used to detect which device is active in a chain of devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Input Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device’s nCE pin. Output Active serial data output from the Cyclone device. This output pin is utilized during active serial configuration mode. The Cyclone device controls configuration and drives address and control information out on ASDO. In passive serial configuration, this pin is available as a user I/O pin. I/O, Output Chip select output that enables/disables a serial configuration device. This output is utilized during active serial configuration mode. The Cyclone device controls configuration and enables the serial configuration device by driving nCSO low. In passive serial configuration, this pin is available as a user I/O pin. I/O, Output This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, the pin indicates when the device has entered user mode. This pin can be used as a user I/O pin after I/O, Output (open-drain) configuration. Copyright © 2003 Altera Corp. Pin Definitions Page 14 of 17 Pin Information for the Cyclone™ EP1C20 Device version 1.1 Pin Name Pin Type (1st, 2nd, & 3rd Function) CLKUSR I/O, Input DEV_CLRn I/O, Input DEV_OE MSEL[1..0] TMS TDI TCK TDO I/O, Input Input Input Input Input Output CLK0 Input, LVDS Input CLK1 Input, LVDS Input CLK2 Input, LVDS Input CLK3 Input, LVDS Input DPCLK[7..0] I/O PLL1_OUTp I/O, Output PLL1_OUTn I/O, Output PLL2_OUTp I/O, Output PLL2_OUTn I/O, Output LVDS[0..128]p I/O, LVDS RX or TX LVDS[0..128]n I/O, LVDS RX or TX Copyright © 2003 Altera Corp. Pin Description Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration. Dual-purpose pin that can override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as defined in the design. Dual-purpose pin that can override all tri-states on the device. When this pin is driven low, all I/O pins are tristated; when this pin is driven high, all I/O pins behave as defined in the design. Dedicated mode select control pins that set the configuration mode for the device. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG output pin. Clock and PLL Pins Dedicated global clock input. The dual-function of CLK0 is LVDSCLK1p, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK1 is LVDSCLK1n, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK2 is LVDSCLK2p, which is used for differential input to PLL2. Dedicated global clock input. The dual-function of CLK3 is LVDSCLK2n, which is used for differential input to PLL2. Dual-purpose clock pins that can connect to the global clock network. These pins can be used for high fan-out control signals, such as clocks, clears, IRDY, TRDY, or DQS signals. These pins are also available as user I/O pins. External clock output from PLL 1. This pin can be used with differential or single ended I/O standards. If clock output from PLL1 is not used, this pin is available as a user I/O pin. Negative terminal for external clock output from PLL1. If the clock output is single ended, this pin is available as a user I/O pin. External clock output from PLL 2. This pin can be used with differential or single ended I/O standards. If clock output from PLL2 is not used, this pin is available as a user I/O pin. Negative terminal for external clock output from PLL2. If the clock output is single ended, this pin is available as a user I/O pin. Dual-Purpose LVDS & External Memory Interface Pins Dual-purpose LVDS I/O channels 0 to 128. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Dual-purpose LVDS I/O channels 0 to 128. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Pin Definitions Page 15 of 17 Pin Information for the Cyclone™ EP1C20 Device version 1.1 Pin Name Pin Type (1st, 2nd, & 3rd Function) LVDSCLK1p Input, LVDS Input LVDSCLK1n Input, LVDS Input LVDSCLK2p Input, LVDS Input LVDSCLK2n Input, LVDS Input DQS[0..1][L,R,T,B] DQ[0..7][L,R,T,B] DM[0..1][L,R,T,B] I/O I/O I/O Copyright © 2003 Altera Corp. Pin Description Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK0 input pin. Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK1 input pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK2 input pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK3 input pin. Optional data strobe signal for use in external memory interfacing. These pins also function as DPCLK pins; therefore, the DQS signals can connect to the global clock network. A programmable delay chain is used to shift the DQS signals by 90 or 72 degrees. Optional data signal for use in external memory interfacing. Optional data mask output signal for use in external memory interfacing. Pin Definitions Page 16 of 17 Pin Information For The Cyclone™ EP1C20 Device, ver 1.1 VREF2B2 VREF1B2 VREF0B2 VREF0B3 VREF1B3 VREB2B3 PLL2 B3 B1 PLL1 VREB2B1 VREF1B1 VREF0B1 B2 B4 VREF2B4 VREF1B4 VREF0B4 Notes: 1.This is a top view of the silicon die. 2.This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and the Quartus II for exact locations. Copyright © 2003 Altera Corp. PLL & Bank Diagram Page 17 of 17
