Bank VREF Bank Pin Name/Function Optional Function(s) Configuration Q240
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Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF Bank VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 Pin Name/Function Optional Function(s) Configuration Function IO LVDS23p INIT_DONE IO LVDS23n IO LVDS22p CLKUSR IO LVDS22n IO VREF0B1 IO IO LVDS21p IO LVDS21n VCCIO1 GND IO DPCLK1 IO LVDS20p IO LVDS20n IO LVDS19p IO LVDS19n IO LVDS18p IO LVDS18n IO LVDS17p IO LVDS17n IO LVDS16p IO LVDS16n IO LVDS15p IO LVDS15n IO LVDS14p IO LVDS14n IO VCCIO1 GND IO LVDS13p IO LVDS13n IO LVDS12p IO LVDS12n IO VREF1B1 IO nCSO DATA0 DATA0 nCONFIG nCONFIG Copyright © 2003 Altera Corp. Q240 F256 F324 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 D4 C3 C2 B1 G5 F4 D3 E4 C3 C2 D3 D2 D4 D1 E3 E2 F5 E3 D2 E2 D1 F3 G3 F2 E1 G2 F1 F1 E4 E5 F2 F3 F4 F5 G1 G2 F6 F7 G3 G4 G5 G6 H1 DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 DQ0L0 DQ0L1 DQ0L0 DQ0L1 DQ0L0 DQ0L1 DQS0L DQ0L2 DQ0L3 DQS0L DQ0L2 DQ0L3 DQS0L DQ0L2 DQ0L3 DM0L DM0L DQ0L4 DQ0L5 DQ0L6 DQ0L7 22 23 24 25 26 Pin List H5 G4 H2 H3 H2 H3 H4 H5 H6 J1 H7 J2 DM0L Page 1 of 15 Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF Bank VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 Pin Name/Function Optional Function(s) Configuration Function VCCA_PLL1 CLK0 LVDSCLK1p CLK1 LVDSCLK1n GNDA_PLL1 GNDG_PLL1 nCEO nCEO nCE nCE MSEL0 MSEL0 MSEL1 MSEL1 DCLK DCLK IO ASDO IO PLL1_OUTp IO PLL1_OUTn IO LVDS11p IO LVDS11n IO LVDS10p IO LVDS10n IO LVDS9p IO LVDS9n VCCIO1 GND IO IO LVDS8p IO LVDS8n IO LVDS7p IO LVDS7n IO LVDS6p IO LVDS6n IO LVDS5p IO LVDS5n IO LVDS4p IO LVDS4n IO LVDS3p IO LVDS3n IO DPCLK0 VCCIO1 Copyright © 2003 Altera Corp. Q240 F256 F324 27 28 29 30 31 32 33 34 35 36 37 38 39 H6 G1 H1 J6 J5 H4 J4 J3 J2 K4 K3 J1 K2 J5 J3 J4 K1 J6 K2 J7 K3 K7 L1 K6 K4 K5 L7 L6 L2 L3 L5 L4 DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 DM1L 40 41 42 43 44 45 46 47 48 49 50 51 Pin List L3 K1 L1 L2 M1 N1 M2 N2 M3 L5 M1 M3 M2 M5 M4 N1 N2 M6 N7 N5 N6 N3 N4 P5 DQ1L0 DQ1L1 DQ1L2 DQ1L3 DQ0L4 DQ0L5 DQ0L4 DQ0L5 DQ1L4 DQ1L5 DQS1L Page 2 of 15 Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF Bank VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF1B4 Pin Name/Function Optional Function(s) Configuration Function GND IO LVDS2p IO LVDS2n IO VREF2B1 IO IO LVDS1p IO LVDS1n IO LVDS0p IO LVDS0n IO LVDS102p IO LVDS102n IO LVDS101p IO LVDS101n IO LVDS100p IO LVDS100n IO LVDS99p IO LVDS99n GND VCCIO4 GND VCCINT IO DPCLK7 IO VREF2B4 IO LVDS98p IO LVDS98n IO LVDS97p IO LVDS97n IO LVDS96p IO LVDS96n GND VCCINT IO LVDS95p IO LVDS95n IO LVDS94p IO LVDS94n IO LVDS93p Copyright © 2003 Altera Corp. Q240 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Pin List F256 F324 DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 M4 N3 K5 L4 R1 P2 P3 N4 R2 T2 R3 P4 R4 T4 R5 P5 P2 P3 R1 P4 R2 R3 T2 T3 U3 V4 M8 N8 T4 U4 T5 U5 DQ0L6 DQ0L7 DQ0L6 DQ0L7 DQ1L6 DQ1L7 DQ1B7 DQ1B6 DQ1B7 DQ1B6 DQ1B7 DQ1B6 M5 M6 N5 N6 P6 R6 M7 R4 R5 V6 U6 P6 P7 T6 R6 DQS1B DQS1B DQS1B DQ1B5 DQ1B4 DQ1B5 DQ1B4 DQ1B5 DQ1B4 T6 R7 P7 N7 R8 U7 V7 T7 R7 U8 DQ1B3 DQ1B2 DQ1B1 DQ1B0 Page 3 of 15 Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF Bank VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 Pin Name/Function Optional Function(s) Configuration Function IO LVDS93n IO LVDS92p IO LVDS92n GND VCCINT GND VCCIO4 IO LVDS91p IO LVDS91n IO LVDS90p IO LVDS90n IO LVDS89p IO LVDS89n IO VREF1B4 IO LVDS88p IO LVDS88n IO LVDS87p IO LVDS87n GND VCCINT IO IO LVDS86p IO LVDS86n IO LVDS85p IO LVDS85n GND VCCIO4 IO LVDS84p IO LVDS84n GND VCCINT IO LVDS83p IO LVDS83n IO LVDS82p IO LVDS82n IO LVDS81p Copyright © 2003 Altera Corp. Q240 F256 F324 87 88 T8 M8 V8 T8 R8 DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 89 90 91 92 93 M10 94 95 96 97 R9 T9 U9 V9 R9 T9 M9 N9 P9 U10 V10 T10 R10 98 99 100 101 P9 N9 R10 T11 P10 R11 T11 U11 V11 N10 P10 V12 U12 R11 P11 T12 R12 V13 U13 T13 N8 P8 DM1B DM1B DM1B DM0B 102 103 Pin List DQ0B7 DQ0B6 DQ0B5 DQ0B4 Page 4 of 15 Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF Bank VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 Pin Name/Function Optional Function(s) Configuration Function IO LVDS81n IO LVDS80p IO LVDS80n IO IO VREF0B4 IO DPCLK6 GND VCCINT GND VCCIO4 IO LVDS79p IO LVDS79n IO LVDS78p IO LVDS78n IO LVDS77p IO LVDS77n IO LVDS76p IO LVDS76n IO LVDS75n IO LVDS75p IO LVDS74n IO LVDS74p IO LVDS73n IO LVDS73p IO VREF2B3 IO GND VCCIO3 IO DPCLK5 IO LVDS72n IO LVDS72p IO LVDS71n IO LVDS71p IO LVDS70n IO LVDS70p IO LVDS69n Copyright © 2003 Altera Corp. Q240 F256 F324 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 N11 N12 M9 M11 M12 R13 N10 M10 P12 P13 U14 P12 R12 T13 R13 R14 P13 T15 R15 N13 P14 P15 R16 N15 N16 K12 K14 T14 R14 V15 U15 N11 M11 U16 T15 T16 T17 R17 R18 R15 R16 P16 P17 DQ1B3 DQ1B2 DQ1B1 DQ1B0 DQ1B3 DQ1B2 DQ1B1 DQ1B0 DQ0B3 DQ0B2 DQ0B1 DQ0B0 DQ1R7 DQ1R7 DQ1R7 DQ1R6 DQ1R6 DQ1R6 L12 N14 M13 M14 L13 M15 M16 L14 P15 P14 N14 N18 N17 N13 N12 N16 DQS1R DQ1R5 DQ1R4 DQS1R DQ1R5 DQ1R4 DQS1R DQ1R5 DQ1R4 Pin List DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 DQS0B Page 5 of 15 Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF Bank VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF0B3 Pin Name/Function Optional Function(s) Configuration Function IO LVDS69p IO LVDS68n IO LVDS68p IO LVDS67n IO LVDS67p IO GND VCCIO3 IO LVDS66n IO LVDS66p IO LVDS65n IO LVDS65p IO LVDS64n IO LVDS64p IO IO PLL2_OUTn IO PLL2_OUTp CONF_DONE CONF_DONE nSTATUS nSTATUS TCK TCK TMS TMS TDO TDO GNDG_PLL2 GNDA_PLL2 CLK3 LVDSCLK2n CLK2 LVDSCLK2p VCCA_PLL2 TDI TDI IO VREF1B3 IO LVDS63n IO LVDS63p IO LVDS62n IO LVDS62p IO LVDS61n IO LVDS61p GND Copyright © 2003 Altera Corp. Q240 F256 F324 139 140 141 L15 L16 K16 N15 M18 M17 M14 M15 M16 DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 DQ1R3 DQ1R2 DQ1R1 DQ1R0 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Pin List K15 J16 K13 J13 J14 J15 H15 J12 J11 H16 G16 H11 H14 H12 L18 L17 M13 L13 L16 L15 L14 K16 K15 K17 L12 K18 K14 K13 J18 K12 J16 J15 J12 J17 J14 J13 H13 H14 H15 H16 H17 DM1R DM0R Page 6 of 15 Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 Pin Name/Function Optional Function(s) Configuration Function VCCIO3 IO IO LVDS60n IO LVDS60p IO LVDS59n IO LVDS59p IO LVDS58n IO LVDS58p IO LVDS57n IO LVDS57p IO LVDS56n IO LVDS56p IO LVDS55n IO LVDS55p IO LVDS54n IO LVDS54p IO DPCLK4 GND VCCIO3 IO LVDS53n IO LVDS53p IO IO VREF0B3 IO LVDS52n IO LVDS52p IO LVDS51n IO LVDS51p IO LVDS50n IO LVDS50p IO LVDS49n IO LVDS49p IO LVDS48n IO LVDS48p IO LVDS47n IO LVDS47p VCCIO2 Copyright © 2003 Altera Corp. Q240 F256 F324 G14 G13 G15 F16 F14 F13 F15 E16 E15 D16 D15 E14 F12 H18 G18 G17 G13 G14 G15 G16 G12 F12 F18 F17 F13 F14 F16 F15 E17 E13 D14 H13 G12 B16 C15 C14 D13 B15 A15 B14 C13 B13 A13 B12 C12 E16 E15 D18 E14 D16 D15 C17 D17 C16 B16 G11 F11 B15 A15 C15 D14 DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 Pin List DQ0R7 DQ0R6 DQ0R5 DQ0R4 DM1R DM1R DQ1R3 DQ1R3 DQ0R3 DQS0R DQ1R2 DQ1R1 DQ1R0 DQ1R2 DQ1R1 DQ1R0 DQ0R2 DQ0R1 DQ0R0 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T0 DQ0T1 DQ0T2 DQ0T3 Page 7 of 15 Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 Pin Name/Function Optional Function(s) Configuration Function GND VCCINT GND IO DPCLK3 IO VREF0B2 IO IO LVDS46n IO LVDS46p IO LVDS45n IO LVDS45p IO LVDS44n IO LVDS44p IO LVDS43n IO LVDS43p VCCINT GND IO LVDS42n IO LVDS42p VCCIO2 GND IO LVDS41n IO LVDS41p IO LVDS40n IO LVDS40p IO VCCINT GND IO LVDS39n IO LVDS39p IO LVDS38n IO LVDS38p IO VREF1B2 IO LVDS37n IO LVDS37p IO LVDS36n IO LVDS36p Copyright © 2003 Altera Corp. Q240 F256 F324 DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 190 191 192 193 194 195 196 197 E12 E11 E9 D12 D11 DQS0T C11 B11 B14 C14 E13 G10 F10 B13 A13 D13 C13 D12 C12 A11 B10 B12 A12 200 201 202 203 C10 D10 A9 B9 C11 D11 B11 A11 E11 204 205 206 207 D9 C9 208 E10 C10 D10 B10 A10 E10 G9 F9 D9 C9 DQS0T DQS0T DQ0T4 DQ0T5 DQ0T6 DQ0T7 198 199 Pin List C8 D8 DM0T DM0T DM0T DM1T Page 8 of 15 Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 Pin Name/Function Optional Function(s) Configuration Function IO LVDS35n IO LVDS35p VCCIO2 GND VCCINT GND IO LVDS34n IO LVDS34p IO LVDS33n IO LVDS33p IO LVDS32n IO LVDS32p IO LVDS31n IO LVDS31p VCCINT GND IO LVDS30n IO LVDS30p IO LVDS29n IO LVDS29p IO LVDS28n IO LVDS28p IO VREF2B2 IO DPCLK2 VCCINT GND VCCIO2 GND IO LVDS27n IO LVDS27p IO LVDS26n IO LVDS26p IO LVDS25n IO LVDS25p IO LVDS24n DEV_OE IO LVDS24p DEV_CLRn Copyright © 2003 Altera Corp. Q240 F256 F324 DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 A9 B9 209 210 211 212 213 214 215 216 217 218 219 220 221 E8 A8 B8 D7 C7 B7 A6 D8 C8 A8 B8 E8 E7 A7 B7 DQ1T0 DQ1T1 DQ1T2 DQ1T3 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 E7 B6 C6 D6 D5 E6 E5 D7 C7 E6 D6 B6 C6 A6 B5 DQS1T C5 B5 A4 B4 C4 B3 A2 B2 C5 D5 A4 B4 F8 G8 B3 C4 Pin List DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQ1T4 DQ1T5 DQ1T6 DQ1T7 Page 9 of 15 Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number VREF Bank Pin Name/Function Optional Function(s) Configuration Function VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 GND GND GND GND Copyright © 2003 Altera Corp. Q240 Pin List F256 F324 A7 A10 G8 G10 H7 H9 J8 J10 K7 K9 T7 T10 C1 G6 P1 A17 A2 B1 B18 H10 J9 K10 L9 U1 U18 V17 V2 T3 L7 L10 T14 P16 K11 C16 A14 F10 F7 A3 A1 A16 A5 A12 DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 E1 G7 M7 P1 P11 P8 V14 V5 E18 H12 M12 P18 A14 A5 E12 E9 A1 A16 A18 A3 Page 10 of 15 Pin Information for the Cyclone™ EP1C12 Device Final version 1.2 Bank Number VREF Bank Pin Name/Function Optional Function(s) Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Copyright © 2003 Altera Corp. Q240 Pin List F256 F324 F6 F8 F9 F11 G7 G9 G11 H8 H10 J7 J9 K6 K8 K10 L6 L8 L9 L11 T1 T5 T12 T16 B17 B2 C1 C18 H11 H8 H9 J10 J11 J8 K11 K8 K9 L10 L11 L8 T1 T18 U17 U2 V1 V16 V18 V3 DQS for x8 in DQS for x8 in DQS for x8 in the Q240 the F256 the F324 Page 11 of 15 Pin Information for the Cyclone™ EP1C12 Device version 1.2 Pin Name Pin Type (1st, 2nd, & 3rd Function) VCCIO[1..4] Power VCCINT Power VREF[0..2]B[1..4] I/O, Input VCCA_PLL[1..2] GNDA_PLL[1..2] GNDG_PLL[1..2] Power Ground Ground nSTATUS Bidirectional (opendrain) Bidirectional (opendrain) nCONFIG Input CONF_DONE DCLK DATA0 nCE nCEO ASDO nCSO INIT_DONE Pin Description Supply and Reference Pins These are I/O supply voltage pins for banks 1 through 4. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, and 3.3-V PCI I/O standards. These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, SSTL2, and SSTL3 I/O standards. Input reference voltage for banks 1-4. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. Analog power for PLLs[1..2]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Analog ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Guard ring ground for PLLs[1..2]. The designer can connect this pin to the GND plane on the board. Configuration and JTAG Pins This is a dedicated configuration status pin; it is not available as a user I/O pin. This is a dedicated configuration status pin; it is not available as a user I/O pin. Dedicated configuration control input. A low transition resets the target device; a low-to-high transition begins configuration. All I/O pins tri-state when nCONFIG is driven low. In passive serial configuration mode, DCLK is a clock input used to clock configuration data from an external Input (PS mode), Output source into the Cyclone device. In active serial configuration mode, DCLK is a clock output from the Cyclone (AS mode) device (the Cyclone device acts as master in this mode). This is a dedicated pin used for configuration. Dedicated configuration data input pin. Input Active-low chip enable. Dedicated chip enable input used to detect which device is active in a chain of devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Input Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device’s nCE pin. Output Active serial data output from the Cyclone device. This output pin is utilized during active serial configuration mode. The Cyclone device controls configuration and drives address and control information out on ASDO. In passive serial configuration, this pin is available as a user I/O pin. I/O, Output Chip select output that enables/disables a serial configuration device. This output is utilized during active serial configuration mode. The Cyclone device controls configuration and enables the serial configuration device by driving nCSO low. In passive serial configuration, this pin is available as a user I/O pin. I/O, Output This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, the pin indicates when the device has entered user mode. This pin can be used as a user I/O pin after I/O, Output (open-drain) configuration. Copyright © 2003 Altera Corp. Pin Definitions Page 12 of 15 Pin Information for the Cyclone™ EP1C12 Device version 1.2 Pin Name Pin Type (1st, 2nd, & 3rd Function) CLKUSR I/O, Input DEV_CLRn I/O, Input DEV_OE MSEL[1..0] TMS TDI TCK TDO I/O, Input Input Input Input Input Output CLK0 Input, LVDS Input CLK1 Input, LVDS Input CLK2 Input, LVDS Input CLK3 Input, LVDS Input DPCLK[7..0] I/O PLL1_OUTp I/O, Output PLL1_OUTn I/O, Output PLL2_OUTp I/O, Output PLL2_OUTn I/O, Output LVDS[0..102]p I/O, LVDS RX or TX LVDS[0..102]n I/O, LVDS RX or TX Copyright © 2003 Altera Corp. Pin Description Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration. Dual-purpose pin that can override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as defined in the design. Dual-purpose pin that can override all tri-states on the device. When this pin is driven low, all I/O pins are tristated; when this pin is driven high, all I/O pins behave as defined in the design. Dedicated mode select control pins that set the configuration mode for the device. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG output pin. Clock and PLL Pins Dedicated global clock input. The dual-function of CLK0 is LVDSCLK1p, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK1 is LVDSCLK1n, which is used for differential input to PLL1. Dedicated global clock input. The dual-function of CLK2 is LVDSCLK2p, which is used for differential input to PLL2. Dedicated global clock input. The dual-function of CLK3 is LVDSCLK2n, which is used for differential input to PLL2. Dual-purpose clock pins that can connect to the global clock network. These pins can be used for high fan-out control signals, such as clocks, clears, IRDY, TRDY, or DQS signals. These pins are also available as user I/O pins. External clock output from PLL 1. This pin can be used with differential or single ended I/O standards. If clock output from PLL1 is not used, this pin is available as a user I/O pin. Negative terminal for external clock output from PLL1. If the clock output is single ended, this pin is available as a user I/O pin. External clock output from PLL 2. This pin can be used with differential or single ended I/O standards. If clock output from PLL2 is not used, this pin is available as a user I/O pin. Negative terminal for external clock output from PLL2. If the clock output is single ended, this pin is available as a user I/O pin. Dual-Purpose LVDS & External Memory Interface Pins Dual-purpose LVDS I/O channels 0 to 102. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Dual-purpose LVDS I/O channels 0 to 102. These channels can be used for receiving or transmitting LVDS compatible signals. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for LVDS interfacing, these pins are available as user I/O pins. Pin Definitions Page 13 of 15 Pin Information for the Cyclone™ EP1C12 Device version 1.2 Pin Name Pin Type (1st, 2nd, & 3rd Function) LVDSCLK1p Input, LVDS Input LVDSCLK1n Input, LVDS Input LVDSCLK2p Input, LVDS Input LVDSCLK2n Input, LVDS Input DQS[0..1][L,R,T,B] DQ[0..7][L,R,T,B] DM[0..1][L,R,T,B] I/O I/O I/O Copyright © 2003 Altera Corp. Pin Description Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK0 input pin. Dual-purpose LVDS clock input to PLL1. If differential input to PLL1 is not required, this pin is available as the CLK1 input pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK2 input pin. Dual-purpose LVDS clock input to PLL2. If differential input to PLL2 is not required, this pin is available as the CLK3 input pin. Optional data strobe signal for use in external memory interfacing. These pins also function as DPCLK pins; therefore, the DQS signals can connect to the global clock network. A programmable delay chain is used to shift the DQS signals by 90 or 72 degrees. Optional data signal for use in external memory interfacing. Optional data mask output signal for use in external memory interfacing. Pin Definitions Page 14 of 15 Pin Information For The Cyclone™ EP1C12 Device, ver 1.2 VREF2B2 VREF1B2 VREF0B2 VREF0B3 VREF1B3 VREB2B3 PLL2 B3 B1 PLL1 VREB2B1 VREF1B1 VREF0B1 B2 B4 VREF2B4 VREF1B4 VREF0B4 Notes: 1.This is a top view of the silicon die. 2.This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and the Quartus II for exact locations. Copyright © 2003 Altera Corp. PLL & Bank Diagram Page 15 of 15
