Data Sheet March 2001, ver. 1.1
The Nios TM timer peripheral is a simple 32-bit interval timer. The Nios
CPU controls the timer by writing to several peripheral registers and can request and then read coherent snapshots of the internal counter value.
The Nios timer peripheral generates a single interrupt-request output that can be masked by an internal control bit.
Figure 1. Nios Embedded Timer
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Each timer is generated by a MegaWizard ® Plug-In in the Quartus ™ II software. A complete system may contain any number of timer modules—limited only by the capacity of the target device.
The Nios CPU controls the timer by:
■
■
■
■
Setting the internal countdown pre-load value (timer period) by writing values to the PeriodL and PeriodH registers.
Starting and stopping the internal counter by writing 1s to the start and stop bits in the control register.
Enabling or disabling interrupts on time-out by writing to the interrupt-enable time-out (iTO) bit in the Control register.
Setting the operating mode (continuous or count only once) by writing to the continuous-run (Cont)-bit in the Control register.
Because the Nios timer must work with 16-bit systems, all embedded processor-accessible registers are 16 bits wide. Thus, a 32-bit Nios CPU would need to perform two separate write-operations to two 16-bit registers (PeriodL and PeriodH) to set a 32-bit down-count value.
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Nios Embedded Processor Timer Peripheral
The Nios CPU can request a coherent snapshot of the current internal counter value by writing to either the SnapL or SnapH registers. A write to either of these registers causes both registers to be simultaneously loaded with the current value of the internal counter.
The Nios timer runs off a single master clock input (clk). This clock is used to run both the Nios CPU interface registers and the internal counter. The system should be set up so that the same clock drives both the timer and the Nios CPU.
Table 1. Timer Register Map
A2 to A0 Register
Name
2
3
0
1
4
5
Status
1,2
Control
Period(L)
Period(H)
Snap(L)
,5
Snap(H)
15
Description of Register Bit
… … … 4 3 2 1 0
Run
3
TO
Stop Start Cont iTO
Time-out Period – 1 (bits 15:0)
4
Time-out Period – 1 (bits 31:16)
Time-out Counter Snapshot (bits 15:0)
Time-out Counter Snapshot (bits 31:16)
Notes
(1) A write-operation to the Status register clears the time-out (TO) bit.
(2) Write-event register. A write-operation to this address causes an event in the device.
(3) Read-only value.
(4) Host-written control value. Can be read-back at any time.
(5) A write operation to either the Snap(L) or Snap(H) registers updates both registers with a coherent snapshot of the current internal-counter value.
The Status register contains individual bits that indicate different internal conditions. The bits in the status register are:
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TO (bit 0)—The TO bit is set to a 1 whenever the internal counter reaches zero. The TO bit is cleared (set to 0) whenever the Nios CPU performs a write operation to the Status register.
Run (bit 1)—The Run bit is set to a 1 whenever the internal counter is running; otherwise Run bit is 0. The Nios CPU starts and stops the internal counter by writing to the Stop and Start bits in the Control register.
The Run bit is not changed by a write operation to the status register.
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Nios Embedded Processor Timer Peripheral
The Control register contains individual bits, set by the Nios CPU, which control the timer operation. The bits in the Control register are:
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■ iTO (bit 0)—If the iTO bit is a 1, the Nios timer generates an interrupt request (drives its IRQ output true (1)) whenever the TO bit in the status register is a 1. If the iTO bit is a 0, the interrupt request IRQ output is always 0.
Cont (bit 1)—The Cont bit determines how the internal counter behaves when it reaches zero. When the internal counter reaches zero, it reloads with the 32-bit value stored in the PeriodL and
PeriodH registers, regardless of the Cont bit. If the Cont bit is a 1, the internal counter runs until it is stopped by the Stop bit. If Cont is a 0, the internal counter stops after it reaches zero and reloads with the period value.
Start (bit 2)—The Nios CPU starts the internal counter running
(counting-down) by writing a 1 to the Start bit in the Control register.
The Start bit is an event bit-the counter is started when the write operation is performed. The value stored in the Start bit of the Control register has no subsequent effect on the internal counter. Writing a 0 to the Start bit has no effect on the operation of the Timer.
Any 1 written to the Start bit starts the counter, regardless of the stored value. If the timer has been stopped, writing a 1 to the Start bit causes the timer to restart counting from the number currently held in its counter.The Nios CPU may read-back the value of the Start bit.
■ Stop (bit 3)-The Nios CPU stops the internal counter by writing a 1 to the Stop bit in the Control register. The Stop bit is an event bit causing the counter to stop when the write operation is performed. The value stored in the Stop bit of the Control register has no subsequent effect on the internal counter. Writing a 0 to the Stop bit has no effect on the operation of the Timer.The Nios CPU may read back the value of the
Stop bit.
The PeriodL register holds the 16 least significant bits of the 32-bit downcount pre-load value (the 16 most significant bits are held in the PeriodH register). The actual period (i.e., interrupt rate) of the Nios timer is one greater than the value stored in the PeriodH and PeriodL registers
(because the internal counter assumes the value zero (0x00000000) for one clock cycle).
The internal counter is loaded with the 32-bit value stored in PeriodH and
PeriodL when either:
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Nios Embedded Processor Timer Peripheral
1.
The Nios CPU performs a write operation to either the PeriodH or
PeriodL registers.
2.
The internal counter reaches 0.
The internal counter is automatically stopped whenever the Nios CPU writes to either the PeriodH or PeriodL registers.
The PeriodH register holds the 16 most significant bits of the 32-bit downcount preload value (the 16 least significant bits are held in the PeriodL register). The actual period (i.e., interrupt rate) of the Nios timer is one greater than the value stored in the PeriodH and PeriodL registers. This is because the internal counter assumes the value zero (0x00000000) for one clock cycle.
The SnapL register holds the 16 least significant bits of the most recently sampled 32-bit counter snapshot. (The 16 most significant bits are held in the SnapH register). The Nios CPU may request a coherent snapshot of the current 32-bit internal counter by performing a write-operation (writedata ignored) to either the SnapL or SnapH registers. The Nios CPU may request a snapshot whether or not the internal counter is running.
Requesting a snapshot does not change the operation of the internal counter.
The SnapH register holds the 16 most-significant bits of the most recently sampled 32-bit counter snapshot. The 16 least-significant bits are held in the SnapL register.
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Nios Embedded Processor Timer Peripheral
If there is one or more timer peripheral present in the Nios system, the timer peripheral software routines are available in the Nios library
(.lib folder in the custom software development kit).
f For more information regarding software routine calls and custom software development kits, please refer to the Nios Software Development
Reference Manual.
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2001 Altera Corporation. All rights reserved.
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Nios Embedded Processor Timer Peripheral
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