Using High-Speed
Transceiver Blocks in
Stratix GX Devices
November 2002 , ver. 1.0
Introduction
Application Note 237
Applications involving backplane and chip-to-chip architectures have
become increasingly complex and, therefore, operate at higher data rates.
Because these complex applications utilize protocols that require
increasing bandwidth, there is a need for devices to offer more flexibility
while also satisfying multi-gigabit data rate requirements. Altera’s
StratixTM GX family of devices meets both needs with its embedded
transceivers. Stratix GX transceivers can receive and transmit at data rates
up to 3.125 gigabits per second (Gbps), and also have embedded circuitry
to implement high-speed serial bus protocols. Stratix GX devices include
4 to 20 full-duplex transceiver channels, each incorporating clock data
recovery (CDR) technology and embedded serializer/deserializer
(SERDES) capability. The transceiver channels are grouped in integrated,
four channel blocks and are designed for low power consumption and
small die size.
This application note discusses the following:
■
■
■
■
Stratix GX transceiver I/O banks
Transceiver clock distribution
Transceiver internal test modes
Applications & protocols supported with Stratix GX devices
Related Links
■
■
Stratix GX
Transceiver
I/O Banks
Altera Corporation
AN-237-1.0
Stratix GX FPGA Family Data Sheet
AN 202: Using High-Speed Differential I/O Interfaces in Stratix Devices
Stratix GX devices contain seven I/O banks. Figure 1 shows the
Stratix GX transceiver blocks located in I/O bank five. Each transceiver
block contains four, full-duplex transceiver channels. Stratix GX devices
can have up to twenty full-duplex transceiver channels in five transceiver
blocks. Table 1 lists the number of transceiver blocks per Stratix GX
device.
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 1. Location of Stratix GX Transceiver Blocks
I/O Bank 3
I/O Banks 1 and 2 Support:
■ Differential I/O Standards
with DPA:
- True LVDS
- LVPECL
- 3.3-V PCML
- HyperTransport Technology
■ Single-Ended I/O Standards:
- 3.3-, 2.5-, 1.8-V LVTTL
- GTL+
- CTT
- SSTL-2 Class I and II
- SSTL-3 Class I and II
I/O Bank 4
Regular I/O Blocks Support
■ 3.3-, 2.5-, 1.8-V LVTTL
■ 3.3-V PCI, PCI-X
■ GTL
■ GTL+
■ AGP
■ CTT
■ SSTL-18 Class I and II
■ SSTL-2 Class I and II
■ SSTL-3 Class I and II
■ HSTL Class I and II
I/O Bank 2
I/O Bank 5
Contains
Transceiver
Blocks
I/O Bank 5
I/O Bank 1
Individual
Power Bus
I/O Bank 7
I/O Bank 6
Table 1 lists the number of transceiver blocks per Stratix GX device as well
as the number of full-duplex transceiver channels.
Table 1. Number of Transceiver Blocks per Stratix GX Device
Device
Number of
Transceiver Blocks
Full-Duplex
Transceiver Channels
EP1SGX10C
1
4
EP1SGX10D
2
8
EP1SGX25C
1
4
EP1SGX25D
2
8
EP1SGX25F
4
16
EP1SGX40D
2
8
EP1SGX40G
5
20
Each transceiver block contains four channels, a transmit PLL, four
receive PLLs, and other associated control circuitry. Figure 2 shows the
high-level structure of the Stratix GX transceiver block.
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 2. Stratix GX Transceiver Block
Receiver Channel 0
PLD
Logic
Array
Receiver Pins
Channel 0
Transmitter Channel 0
Transmitter Pins
Receiver Channel 1
PLD
Logic
Array
Receiver Pins
Channel 1
Transmitter Channel 1
Transmitter Pins
PLD Logic
Array and/or
Global Clock
PLD
Logic
Array
XAUI
Receiver
State
Machine
XAUI
Transmitter
State
Machine
Channel
Aligner
State
Machine
Receiver Channel 2
PLD
Logic
Array
Receiver Channel 3
Receiver Pins
Transmitter Pins
Receiver Pins
Channel 3
Transmitter Channel 3
Altera Corporation
Reference
Clock Pins
Channel 2
Transmitter Channel 2
PLD
Logic
Array
Transmitter
PLL
Transmitter Pins
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Each Stratix GX transceiver channel consists of a transmitter and receiver.
The transmitter contains:
■
■
■
■
■
Transmitter logic array interface
8B/10B encoder
Transmitter PLL
Serializer
Output buffer
The receiver contains:
■
■
■
■
■
■
■
Input buffer
Clock recovery unit (CRU)
Deserializer
Pattern detector and word aligner
Rate matcher and channel aligner
8B/10B decoder
Receiver logic array interface
You can set all the Stratix GX transceiver functions through the Quartus II
software. You can set programmable pre-emphasis, programmable
equalizer, and programmable current driver dynamically as well. Each
Stratix GX transceiver is also capable of Built-In Self Test (BIST)
generation and verification as well as various loopback modes. Figure 3
shows the block diagram for the Stratix GX transceiver.
Stratix GX transceivers provide physical coding sublayer (PCS) and
physical media attachment (PMA) implementation for protocols such as
10 gigabit attachment unit interface (XAUI). The PCS portion of the
transceiver consists of the logic array interface, 8B/10B encoder/decoder,
pattern detector, word aligner, rate matcher, channel aligner, and the BIST
and PRBS pattern generator/verifier. The PMA portion of the transceiver
consists of the serializer/deserializer, the CRU, and the I/O buffers.
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Altera Corporation
Receiver
Transmitter
BIST
Pattern
Verifier
Demultiplexer
(1-to-2) and
Receiver FIFO
Reverse Parallel
Loopback
BIST
Pattern
Generator
8B/10B
Decoder
Rate
Matcher
and
Channel
Aligner
Multiplexer
(2-to-1) and
Transmitter FIFO
PRBS
Pattern
Verifier
Pattern
Detector
and Word
Aligner
Parallel
Loopback
8B/10B
Encoder
PRBS
Pattern
Generator
Receiver
PLL
Clock
Recovery
Unit
Serial-toParallel
Parallelto-Serial
Transmitter
PLL
Reference
Clock
Reverse Serial
Loopback
Serial
Loopback
Enable
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 3. Stratix GX Transceiver Block Diagram
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Transmitter Path
The following describes the data path through the Stratix GX transceiver
transmitter (see Figure 3). Data travels through the Stratix GX transceiver
transmitter via the following modules:
■
■
■
■
■
Transmitter logic array interface
8B/10B encoder
Transmitter PLL
Serializer (parallel to serial converter)
Output buffer
Transmitter Logic Array Interface
The data path starts at the logic array via the transmitter logic array
interface. The transmitter logic array interface includes the multiplexer
and transmitter synchronization FIFO. The transmitter synchronization
FIFO transfers the data from the logic array clock domain to the clock
domain of the transmitter channel. The multiplexer takes a 16- or 20-bit
data bus and converts it into a double-speed 10- or 8-bit data buses,
respectively. If the data from the logic array is not 16-bit or 20-bit (double
width mode), the multiplexer is bypassed. Figure 4 shows the operation
of the multiplexer and transmitter synchronization FIFO.
Figure 4. Transmitter Multiplexer & Synchronization FIFO Operation
Transmitter
Synchronization
FIFO
8-, 10-, 16-,
or 20-bit data
Logic Array
Clock
8- or 10-bit data
8- or
10-bit data
8-, 10-, 16-,
or 20-bit data
8- or 10-bit data
Transmit
PLL Clock
2-to-1 Multiplexer
The transmitter synchronization FIFO is four words deep with a
maximum clock rate of 160 MHz. The write clock of the transmitter
synchronization FIFO is the clock from the logic array, whereas the read
clock is the reference clock from the transmitter PLL. The logic array clock
must be a multiple of the fast clock generated by the transmitter PLL.
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
8B/10B Encoder
The 8B/10B encoder translates an 8-bit parallel data stream into a 10-bit
code for future serial transmission. Figure 5 shows the 8B/10B encoder
and its associated signals.
Figure 5. 8B/10B Encoder & Associated Signals
Data [7..0]
Force disparity
Data [9..0]
8B/10B
Encoder
Control
Besides the 8-bit data bus, the inputs to the 8B/10B encoder also include
the force disparity signal (for the InfiniBand protocol) and the control
signal. The force disparity signal generates the disparity of the 10-bit code
by either starting the 8B/10B encoder with a positive disparity pattern
(i.e., force disparity = high), or negative disparity pattern (i.e., force
disparity = low). Positive disparity is defined as more 1’s than 0’s in the
10-bit generated code. This disparity signal forces the disparity of all
channels to be the same during the first training sequence.
One feature of the 8B/10B encoder is that it forces at least one transition
for every five bits of data sent. This feature enables the receiving device to
acquire and maintain lock. When high, the control signal input tells the
encoder that the input word is a control character Kx.y and not data Dx.y
(see Table 2).
Table 2. 8B/10B Encoder Control Character Codes
Control Characters
K28.0, K28.1, K28.2, K28.3, K28.4, K28.5, K28.6, K28.7, K23.7, K27.7, K29.7,
and K30.7
The 8B/10B encoder operates in two modes: XAUI mode and standard
mode. When the 8B/10B encoder is in XAUI mode, the XAUI transmit
state machine controls the data to the encoder. In XAUI mode, the XAUI
state machine controls the 8B/10B encoder and all four transmitter
channels operate together. In standard mode, each transmitter channel
operates independently. The 8B/10B encoder can also be bypassed.
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Transmitter PLL
Each transceiver block has one transmitter PLL, which receives the
reference clock and generates the following signals:
■
■
■
High-speed serial clock used by the serializer
Slow-speed reference clock used by the receiver
Slow-speed clock used by the logic array (divisible by 2)
Figure 6 shows the transmitter PLL’s inputs and outputs and Table 3
shows the transmitter PLL specifications.
Figure 6. Transmitter PLL Input Sources
CLK input buffer to local
interconnect to other transceiver
blocks, bypassing the
transmitter PLL
Local transceiver
block reference
input pins
Global clock
2
Inter-transceiver
block 1 (IQ1) clock
High-speed serializer clock
(0˚ and 180˚ phase)
Low-speed parallel clock
to receiver PLL, transmitter,
and logic array
Inter-transceiver
block 2 (IQ2) clock
Transmitter PLL
Table 3 shows the transmitter PLL specifications.
Table 3. Transmitter PLL Specifications
Parameter
Specification
Input reference frequency range
62.5 MHz to 650 MHz
Input reference duty cycle
60%/40%
Input reference jitter
100 ps (peak-to-peak)
Data rate support
0.622 to 3.125 Gbps
Multiplication factor (W) (1), (2)
2, 4, 5, 8, 10, 16, or 20
Note to Table 3:
(1)
(2)
8
You can only use multipliers 2 and 5 when the transmitter PLL reference clock
source is the local transceiver block reference input pins.
All transmitter channels in a transceiver block use the same multiplication factor.
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
The transmitter PLL supports an operation range from 622 Mbps to
3.125 Gbps data rate with programmable PLL multiplication factor (W).
Table 4 shows the reference clock and multiplier settings for common
Stratix GX device protocols.
Table 4. Reference Clock & Multiplier Settings for Applicable Standards
CDR Applications
Data Rate (Gbps)
Frequency Multiplication
(W)
Reference Clock Frequency
(MHz)
Min
Max
Min
Max
1G Ethernet
1.25
4
10
125.00
312.50
InfiniBand
2.5
4
20
125.00
625.00
10 Gigabit Ethernet
XAUI
3.125
8
20
156.25
625.00
RapidIO
1.25, 2.5, 3.125
4
20
125.00
625.00
Fibre Channel
1.0625 to 2.125
4
10
150.00
300.00
SFI-5, SPI-5
2.488 to 3.125
4
4
622.00
781.00
PCI Express
2.5
4
20
125.00
625.00
SMPTE 292M
1.485
4
10
148.50
371.25
Custom applications
0.622 to 3.125
62.50
625.00
4, 5, 8, 10, 16, 20
Serializer (Parallel to Serial Converter)
The serializer converts parallel data from the 8B/10B encoder, or PLD
logic array, to serial data. The serializer can support 8-, 10-, 16-, or 20-bit
words when used with the transmitter multiplexer. The serializer drives
the serial data to the output buffer (see Figure 7). The serializer can drive
the serial bit-stream at a data rate range of 622 Mbps to 3.125 Gbps. The
serializer outputs the least significant bit (LSB) of the word first.
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 7. Serializer Block Diagram
Serializer
Parallel data in
(from 8B/10B
encoder)
8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Serial data
out (to output
buffer)
Low-speed
parallel clock
High-speed
serial clock
Figure 8 shows the serial bit order of the serializer output.
Figure 8. Serializer Bit Order
Parallel clock
Serial clock
Parallel data in (hex)
Serial data out
00
56
0 11 0 1 0 1 0
Output Buffer
The Stratix GX transceiver buffers support 1.5-V pseudo current mode
logic (PCML) up to 3.125 Gbps. The buffer’s signaling levels are
compatible with low voltage positive emitter coupled logic (LVPECL),
low voltage differential signaling (LVDS), and 3.3-V PCML signaling
when AC coupled. The Stratix GX transceiver is capable of driving
40 inches of FR4 trace across two connectors. The internal termination, in
the input and output buffers, supports AC and DC coupling with
programmable differential termination settings of 100-, 120-, or 150-Ω.
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
The output buffer consists of:
■
■
■
Programmable current driver
Programmable pre-emphasis circuit
Internal transmitter termination
Figure 9 shows the block diagram of the output buffer.
Figure 9. Transmitter Output Buffer Block Diagram
Output Buffer
Programmable
Termination
Serializer
Programmable
Current
Driver
Programmable
Pre-Emphasis
Circuit
Output
Pins
Programmable Current Driver
The programmable current driver controls the output differential voltage
(VOD) to handle different length, backplane, and receiver requirements.
You can program the output buffer VOD to drive either short or long
distances through connectors and cable. The programmable current
driver brings the signal to the appropriate levels at the receiver by
boosting the output signal levels to compensate for transmission line
losses. Figure 10 shows how VOD can be programmed to any value
between 400 and 1,600 mV by setting the current level.
You can change the VOD setting with the Quartus II software or
dynamically via a signal accessible within the FPGA logic array without
reconfiguring the device.
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Figure 10. VOD Signal Levels
Single-Ended Waveform
VA
±VOD
VB
Differential Waveform
+800
+VOD
0-V Differential
VOD (Differential)
VOD (Differential)
= VA − VB
− VOD
− 800
Table 5 shows the setting per current and impedance levels.
Table 5. Programmable VOD (Differential)
Current Level (mA)
VOD (mV)
100 Ω
120 Ω
150 Ω
4
400
480
600
8
800
960
1,200
10
1,000
1,200
1,500
12
1,200
1,440
14
1,400
16
1,600
Programmable Pre-Emphasis Module
The programmable pre-emphasis module in each transmit buffer boosts
the high-frequency components in the transmit data signal, which may be
lost in the transmission media, while attenuating the lower-frequency
components. This process maximizes the data eye opening at the far-end
receiver. Pre-emphasis is particularly useful when driving data over a
backplane, with low-quality coaxial cables, or over long distances.
Figures 11 and 12 show conceptual eye diagrams of a 3.125 Gbps signal—
at the transmitter and receiver —with and without pre-emphasis.
You can set pre-emphasis with the Quartus II software or dynamically via
a signal accessible within the FPGA logic array without reconfiguring the
device.
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 11. Eye Diagram of Transmitted Signal Without Pre-Emphasis After
40 Inches of FR4 Board Trace
Transmitter without Pre-Emphasis
Receiver without Pre-Emphasis
Figure 12. Eye Diagram of Transmitted Signal With Pre-Emphasis After
40 Inches of FR4 Board Trace
Transmitter with Pre-Emphasis
Receiver with Pre-Emphasis
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Table 6 shows possible settings for the pre-emphasis level.
Table 6. Programmable Pre-Emphasis
VOD (Differential)
Pre-Emphasis Level
5%
10%
15%
20%
25%
400
420
440
460
480
500
480
504
528
552
576
600
600
630
660
690
720
750
800
840
880
920
960
1000
960
1008
1056
1104
1152
1200
1000
1050
1100
1150
1200
1250
1200
1260
1320
1380
1440
1500
1400
1470
1540
-
-
-
1440
1512
1584
-
-
-
1500
1575
-
-
-
-
1600
-
-
-
-
-
Table 6 shows that the pre-emphasis levels can be set at 5%, 10%, 15%,
20%, and 25% of the programmed VOD setting. The maximum voltage
level at the transmitter differential pins is 1,600 mV (differential). VOD
(differential) is the voltage difference between VA and VB (see Figure 10).
The current drive, the pre-emphasis setting, and the selected termination
should be such that the resulting VOD is 1,600 mV or less. For example, a
16-mA current drive selection is only permitted with 100-Ω termination
and disabled pre-emphasis. The maximum current setting for the 150-Ω
termination resistor is 10 mA with only a 5% pre-emphasis level
permitted. The following equation explains how these three factors are
related.
VOD (differential) ≤ 1600 mV = (pre-emphasis) × (current drive) ×
(termination)
Example 1: 16 mA, 100 Ω, no pre-emphasis
VOD (differential) = (1.00) × (16) × (100.0)
= 1,600 mV ≤ 1,600 mV
Example 2: 10 mA, 150 Ω, 5% pre-emphasis
VOD (differential) = (1.05) × (10) × (150.0)
= 1,575 mV ≤ 1,600 mV
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Internal Transmitter Termination
The output buffer also includes programmable on-chip termination
circuitry of 100-, 120-, or 150-Ω differential termination for different
protocols (i.e., 10 Gigabit Ethernet XAUI and InfiniBand using 100-Ω
termination; Fibre Channel using 150-Ω termination). With on-chip
termination, you do not need to add external components, which use
board space. Plus, the termination resistors are located as close as possible
on the pins, which reduces signal distortion and allows a cleaner signal by
eliminating stubs from the device. A central calibration block controls the
resistance and can calibrate the differential termination either only once
after power-on or reset, or continuously. This option is set during
configuration with the Altera Quartus II software.
The on-chip termination only supports AC-coupled connections for
10 Gigabit Ethernet XAUI, Gigabit Ethernet, Fibre Channel, and RapidIO
protocols (with the exception of InfiniBand, which requires both DC and
AC coupling). If you use AC coupling, you need to provide an external
capacitor. The resistance is accurate to within ±5% of temperature,
voltage, and process changes. You can choose termination for different
channels independently. The default setting for on-chip termination in the
transmitter output buffer is 100 Ω differential. Figure 13 shows the
internal transmitter termination inside the 1.5-V PCML output buffer.
Figure 13. Internal Transmitter Termination
50, 60, or 75 Ω
VCM
50, 60, or 75 Ω
Receiver Path
The following describes the data path through the Stratix GX transceiver
receiver (see Figure 2). Data travels through the Stratix GX transceiver
receiver via the following modules:
■
■
■
■
■
■
■
■
Altera Corporation
Input buffer
Receiver loopback buffer
CRU
Receiver PLL
Pattern detector, word aligner, & data realigner
Channel aligner & rate matcher
8B/10B decoder
Receiver logic array interface
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Input Buffer
The input buffer receives the differential serial data, terminates the data,
adjusts the data for inter-symbol interference (ISI) reduction, and—after
detection—the data is sent to the receiver’s clock recovery unit (CRU).
Figure 14 shows the structure of the input buffer.
The input buffer contains:
■
■
■
Internal receiver termination
Equalizer module
Signal detector
Figure 14. Receiver Input Buffer
Input Buffer
Programmable
Termination
Input
pins
Programmable
Equalizer
Signal
Detector
To CRU
Internal loopback
from transmitter
Loopback Buffer
Internal Receiver Termination
The input buffer includes programmable on-chip termination of 100-,
120-, or 150-Ω differential termination (see Figure 15). The internal
receiver termination scheme behaves identically to the internal
transmitter termination scheme. (See “Internal Transmitter Termination”
on page 15 for more information on Stratix GX internal termination).
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Figure 15. Internal Receiver Termination
50, 60, or 75 Ω
VCM
50, 60, or 75 Ω
Equalizer Module
To negate the effect of high-frequency signal loss in the cable, the
receiver’s equalizer module boosts the signal gain at higher frequencies.
Also, to extend the permissible length of a transmission medium, the
receiver must compensate for protocol inter-symbol interference (ISI) that
distorts the signal. Each receiver input buffer includes a programmable
equalizer, which automatically compensates for ISI dielectric and skin
effect losses.
The equalizer allows the Stratix GX transceivers to operate at 3.125 Gbps
across various lengths of transmission media, and can boost signals by up
to nine decibels (dB). The programmable equalizer settings are based on
the total trace length of FR4 of 0 inches (i.e., no equalization), 20 inches,
and 40 inches. For example, if you know that the trace length to the
Stratix GX transceiver receiver is 20 inches, you can set the equalizer to
compensate for the signal losses so that the signal detector receives the
data correctly. The equalizer is disabled when the transceiver is in a
loopback mode.
You can set the equalizer with the Quartus II software or dynamically via
a signal accessible within the FPGA logic array without reconfiguring the
device.
Signal Detector
Input data goes through the equalizer to the signal detector. The signal
detector is a peak-detector based, differential-signal-level, hysteresis
detector. The peak detector finds the signal based on the voltage level
setting programmed by the designer.
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Each channel has a programmable, signal-loss-threshold-differential
voltage level. Table 7 shows the four center selection levels and their
required differential voltages for a “high” and “low.” The VMIN_ON is the
minimum differential voltage that should arrive at the receiver for the
signal detector output to go “high.” The VMAX-OFF is the maximum
differential voltage below which the signal detector output will go “low.”
Table 7 lists the minimum required times that the incoming signal should
remain either above VMIN_ON or below VMAX_OFF for the signal detector
to change its state in either direction. Table 7 also shows the
detection/loss of signal (LOS) TMIN_OFF time for a typical differential
input voltage of 1,200 mV. When the signal detector does not detect the
signal, the receiver PLL is reset to the reference clock phase instead of the
input data.
For example, on one of the four settings the signal detector output is
“high” when the differential levels are above 640 mV and “low” when the
differential levels are below 590 mV. The example is from the 10 Gigabit
Ethernet XAUI protocol setting with center voltage at 615 mV. You can
specify the threshold settings through the Altera Quartus II software.
Table 7. Receiver Signal Detector Specification
Threshold
Setting
Vmin-on
(mV)
Vmax-off
(mV)
Tmin-on
(ms)
Tmin-off
(ms)
1
640
590
8
116
2
510
450
7
145
3
380
290
6
165
4
190
80
5
198
Receiver Loopback Buffer
The loopback buffer allows you to loop the transmitter’s differential serial
output back to the receiver (i.e., serial loopback mode, see “Channel
Loopback Modes” on page 34). In serial loopback mode, the buffer’s
inputs are at maximum levels, so equalization is not required. The
receiver’s input pins are also pulled low in serial loopback mode.
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Clock Recovery Unit
The CRU uses the reference clock and the serial data input at the receiver
to generate a high-speed clock based on the transitions inside the data.
The CRU feeds the high-speed clock to the serial side of the
serializer/deserializer (SERDES). Next, the receiver uses the recovered
clock throughout the remaining blocks of the receiver, and can feed it to
the logic array for use in other logic. Figure 16 shows the CRU and the
associated control block. The clock control block contains the run-length
violation (RLV) detection circuit.
Figure 16. CRU & Associated Control Block Diagram
Input Buffer
Loss of signal
Input
pins
Clock
Recovery
Unit
Reference clock
from receiver PLL
Loopback
data
Retimed data to deserializer
Recovered clock
Data lock
freq_lock
Control
Block
Run length violation
Reset
Loopback control
The reference clock and data rate must be within 100 parts per million
(ppm) in terms of its frequency content as per the overall system
specification. When no data is incoming, the data/clock recovery circuit
runs off of a reference clock source to keep the synchronizer voltage
controlled oscillator (VCO) close to the optimum recovered clock rate
while waiting for the real data. The CRU supports an operation range
from 622 Mbps to 3.125 Gbps data rate. Table 8 shows the CRU
specifications.
Table 8. CRU Specifications
Parameter
Minimum
Maximum
Serial input data rate
622 Mbps
3.125 Gbps
Run length tolerance
80 UI
-
Frequency offset tolerance
Altera Corporation
–100 ppm
+100 ppm
Bit error rate
-
10-12
Lock time (frequency)
-
1 ms
Lock time (data)
-
0.05 ms
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Run Length Violation Detection Circuit
The programmable run length violation (RLV) detection circuit monitors
the transitions in the data used to generate the clock. The RLV detection
circuit in the CDR block detects and reports when the data in the bit
stream exceeds a preset maximum number of consecutive 1’s or 0’s. You
can set the maximum level—based on your protocol—during
configuration, and the RLV detection circuit will return an error signal if
the data exceeds the maximum. The value of the RLV threshold ranges
from 4 to 160 unchanging data bits, depending on the resolution (i.e.,
whether the input symbol width is set for 8-bit or 10-bit wide data). The
default setting is 128 or 160, depending on the input symbol width setting.
Receiver PLL
Each receiver channel contains a receiver PLL, which takes an input
reference and multiplies it up to the receiver input’s data rate. All four
receiver PLLs within a transceiver must use the same multiplier. The CRU
uses the high-speed serial clock to generate a clock based on the input data
stream’s transitions. The input to the receiver PLL comes from one of the
following sources: the transmitter PLL, the inter-transceiver block clock,
global clocks, I/O bus or generic routing, or the local transceiver block
reference input pins. Figure 17 shows the possible input sources and
outputs for the receiver PLL.
Figure 17. Receiver PLL Input Sources
Local transceiver
block reference
input pins
Receiver
PLL
High-speed
serializer clock
to CRU
Global clocks, I/O bus,
or generic routing
Transmitter PLL
output clock
Inter-transceiver
block 2 (IQ2) clock
When the CRU asserts its frequency lock signal (i.e., FREQ_LOCK), the
CRU is locked to data. The FREQ_LOCK is asserted when the following
conditions occur: the signal detector of the receiver input buffer states a
signal is detected (i.e., SIGDET=1), the receiver PLL VCO frequency and
its reference clock (i.e, RXPLL_INPUT_REF) frequency are within
100 ppm (i.e., FREQ_LOCK=1), and the PLL is very close to absolute phase
lock to the reference clock (i.e., PHASELOCK=1).
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During initialization, the receiver PLL will normally lock to the external
reference until SIGDET=1, FREQ_LOCK=1, and PHASELOCK=1, at which
point the receiver PLL will switch to the incoming data (data mode).
In data mode, the receiver PLL uses a phase detector to keep the recovered
clock aligned properly with the data. If the PLL does not stay locked to
data because of data problems (i.e., frequency drift or severe amplitude
reduction), the receiver PLL will lock back to the reference clock if
AUTOMATIC BACK TO REFERENCE is asserted and if either SIGDET=0
or FREQ_LOCK=0. Table 9 shows the specifications for the receiver PLL.
Table 9. Receiver PLL Specifications
Parameter
Specifications
Input reference frequency range
62.5 MHz to 650 MHz
Input reference duty cycle
60%/40%
Input reference jitter
100 ps (peak-to-peak)
Data rate support
622 Mbps to 3.125 Gbps
Multiplication factor (W)
2, 4, 5, 8, 10, 16, or 20
Note to Table 9:
(1)
You can only use the 2, 4, or 5 multipliers if the output of the transmitter PLL is the
receiver PLL reference clock source.
Frequency Detector
The frequency detector determines whether the incoming reference clock
and data are within a prescribed ppm difference (i.e., to assert
FREQ_LOCK). You can change the acceptable frequency difference
threshold from the default of 1,000 ppm to any value between 31.25 and
2,000 ppm, in 64 steps of 31.25 ppm each. This feature allows users to set
their own ppm level and lock to the reference clock either dynamically or
with the Quartus II software.
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Lock-to-Reference Mode and Lock-to-Data Mode
The receiver PLL acquires the proper frequency from a reference clock in
lock-to-reference mode, which compares the phase and frequency. This
may take up to 1 ms at the lowest data rate. Once the receiver PLL is phase
and frequency locked to the reference clock, it switches to lock-to-data
mode when SIGDET=1 (i.e., the input levels are valid). When the receiver
PLL is in lock-to-data mode, it generates a clock that is phase locked to the
data; thus, the receiver PLL sends out data that is optimally retimed with
the extracted clock. The receiver PLL switches back to lock-to-reference
mode if SIGDET=0 (i.e., the input levels are not valid), or if the frequency
difference between the receiver PLL output and the data exceeds the
allowed ppm difference. You can set the lock-to-data and lock-toreference mode either dynamically or with the Quartus II software. You
can manually switch between reference mode and data mode.
Deserializer (Serial to Parallel Converter)
The deserializer converts incoming high-speed serial data to either 8- or
10-bit-wide parallel data—synchronized to the CRU’s recovered clock.
The deserializer drives the parallel data to the pattern detector and word
aligner module, (see Figure 18). The data rate of the deserializer output
bus is the input data rate divided by the width of the output data bus. For
example, for a 10-bit bus and a serial input data rate of 2.5 Gbps, the
parallel data rate is 2,500/10, or 250 MHz. The first bit into the deserializer
is the least significant bit (LSB) of the data bus out of the deserializer.
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Figure 18. Deserializer Block Diagram
Deserializer
Serial data in
(from CRU)
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
8
Parallel data
out (to word
aligner)
High-speed
serial clock
Low-speed
parallel clock
Figure 19 shows the serial bit order of the deserializer input.
Figure 19. Deserializer Serial Bit Order
Serial clock
Parallel clock
Serial data in
Parallel data
out (hex)
0 11 0 1 0 1 0
00
56
Pattern Detector, Word Aligner & Data Realigner
Because the parallel data from the deserializer may need to be realigned,
the pattern detector, word aligner & data realigner modules line up the
parallel data to the correct boundary by searching for the protocol’s comma
pattern. Figure 20 shows the receiver’s pattern detector, word aligner, and
data realigner input and output circuitry.
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Figure 20. Receiver Pattern Detector, Word Aligner & Data Realigner
Align success
Word
Aligner
Data [9..0]
Align enable
Data [9..0]
Pattern detect
Pattern
Detector
A1A2 or
A1A1A2A2 detect
Data
Realigner
Realign enable
Pattern Detector
After the data leaves the deserializer, it may enter the pattern detector.
The pattern detector searches for a comma pattern across the entire
incoming data that is word-aligned. The pattern detector checks for the
pattern in every bit position. You can program the pattern detector to
recognize one 7-bit pattern, one 10-bit pattern, two consecutive 8-bit
characters (e.g., A1A2), or four consecutive 8-bit characters (e.g.,
A1A1A2A2). For 7-bit and 10-bit patterns, both the positive and negative
disparities (i.e., true and complement) will be checked by the pattern
detector. For the two consecutive 8-bit characters, only the positive
disparity is checked.
The pattern detect signal goes high every time the pattern is detected in
the deserialized bit stream. Otherwise, the pattern detect signal goes low.
The programmable pattern detector gives the receiver the flexibility to
support various standards requiring different comma patterns. Table 10
shows preprogrammed comma patterns supported by Stratix GX
transceivers. A custom pattern can be specified during device
configuration with the Quartus II software. The pattern detector can be
bypassed.
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Table 10. Comma Patterns Supported by the Pattern Detector
Patterns
Pattern Types
Bit Length
Example Bit Pattern
8B/10B commas
/K28.5/ or / K28.1/ or / K28.7 /
7 or 10
b’0011111XXX or
b’1100000XXX
A1, A2 detect
A1 followed by A2
8
b’11110110 followed
by b’00101000
A1A1, A2A2 detect
A1, followed by A1, followed by 8
A2, followed by A2
b’11110110 followed
by b’11110110
followed by
b’00101001 followed
by b’00101001
Custom
Any
Any
16
Word Aligner
The word aligner used with the pattern detector block aligns the incoming
data to a word boundary by detecting and aligning a programmable
synchronization pattern. Based on the location determined by the pattern
detector block, the word aligner will align the outgoing data to the
determined word boundary. This unique pattern of 1’s and 0’s either
cannot occur as part of valid data or is a pattern that repeats at defined
intervals.
Data Realigner
There are two data realigner modes, automatic and manual, and they
determine the word boundary. Table 11 shows the data realignment
modes.
Table 11. Data Realignment Modes
Data Realignment Mode
Altera Corporation
Effective Mode
Automatic data realignment
Gigabit Ethernet, or XAUI state machine
controlled, or user-controlled
Manual data realignment
Manual data realignment and manual
synchronization
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Automatic data realignment uses the 10 Gigabit Ethernet XAUI or Gigabit
Ethernet synchronizer state machine to do the following:
■
■
■
Locate the pattern in the incoming data
Determine the word boundary
Change the word boundary
The output of the data realigner is coordinated using a selection register
that is controlled by either the XAUI or Gigabit Ethernet state machine.
(State machine selection is done during configuration.) The selected state
machine uses the pattern detect signal from the pattern detector and a
known protocol to update the register that controls the data realignment.
For protocols other than the 10 Gigabit Ethernet XAUI or Gigabit Ethernet,
you can control whether or not to accept the state machine’s word
boundary, which is done with the ENCDT (i.e., pattern detect enable)
signal. When ENCDT is high, the word boundary will be allowed to
change. Conversely, when ENCDT is low, the word boundary does not
change.
In the user-controlled automatic mode, the SYNC_STATUS/RESYNC
signal acts as a RESYNC signal. Whenever the pattern is detected in the
incoming data stream and the internal state machine determines a word
boundary that is different than the existing word boundary, the RESYNC
signal will be asserted. The RESYNC signal is de-asserted when the word
boundary is allowed to change to the boundary selected by the internal
logic. In the state machine-controlled automatic mode the
SYNC_STATUS/RESYNC signal acts as a SYNC_STATUS signal, signifying
the conditions for word boundary selection have been satisfied.
When the data realigner operates in manual mode, the selection register
that coordinates the word aligner is updated using the logic array’s
realignment port. The realignment port causes the word boundary of the
incoming data stream to slip by one bit. The manual realignment mode is
supported for both the 8-bit and the 10-bit data path. Continual bit manual
realignment may be done. For an eight-bit data path, for every eight
cycles, data will be re-sent with the data slipped by a bit. Each time a bit
slips, the bit—which arrives at the receiver earlier—is skipped. Internal
logic will still search for the appropriate pattern in the incoming data
stream, but the internal word logic will not change the word boundary to
where it has found the pattern. However, you can change the boundary if
necessary.
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Channel Aligner and Rate Matcher
The next stage the data enters after the pattern detector and word aligner
is the channel aligner and rate matcher. Figure 21 shows the channel
aligner and rate matcher and associated state machine blocks. Both the
channel aligner and the rate matcher are bypassed for protocols other than
10 Gigabit Ethernet XAUI or Gigabit Ethernet.
Figure 21. Channel Aligner & Rate Matcher
Data [12..0]
Data [12..0]
Channel
Aligner
Rate
Matcher
Recovered clock
Logic array
clock
Master clock (1)
Deskew
State
Machine
Gigabit
Ethernet State
Machine
XAUI
State
Machine
To other channels (2)
To other channels (2)
Notes to Figure 21:
(1)
(2)
This is the recovered clock from channel 0 or output from the receiver PLL.
When using the XAUI interface, the channel 0 state machine controls this output.
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Channel Aligner
The channel aligner lines up all channels with a common clock, which is
one of the channel’s recovered clocks. The channel aligner consists of a
channel alignment symbol detector and a 16-byte deep channel aligner
FIFO buffer. The channel aligner is only active when the transceiver block
is operating in XAUI mode. Each receiver channel has its own CDR block,
and the data arrives at each receive pin at slightly different times. The
channel aligner with its deskew FIFO makes sure that the data proceeds
in each receiver out of the FIFO synchronized to the clock edge of the
recovered clock of channel 0. The XAUI deskew state machine controls the
channel aligner and operates in accordance with the Standards Document:
IEEE Draft P802.3 ae /D3.2, Clauses 46, 47, 48, and 51. The mechanism is
summarized as follows:
■
■
■
■
Each channel searches the incoming data for the /A/ character
In each channel, when /A/ is found, the deskew FIFO is enabled
When /A/ is found in all channels, the XAUI deskew state machine
enables the reading of data from the deskew FIFO
The XAUI deskew state machine now monitors the reception of /A/
columns that are not aligned and responds as specified by the
relevant 10 Gigabit Ethernet XAUI standard clause.
Rate Matcher
Stratix GX transceiver blocks use rate matchers to adjust for differences
between the recovered clock and the PLL reference clock. If the reference
clock is not frequency locked to the receiver’s logic array clock, the rate
matcher inserts, or removes, SKIP code groups (i.e., column of /R/) into,
or from, the IDLE stream to match the particular protocol’s rate.
After channel alignment, the receiver performs rate matching. The rate
matching circuit contains a 12-word deep FIFO buffer, which operates in
either rate matching mode (i.e., through the Gigabit and XAUI state
machine) or generic FIFO buffer mode. There is one state machine per
transceiver block for 10 Gigabit Ethernet XAUI, and one state machine per
transceiver channel for Gigabit Ethernet (GIGE).
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The rate matcher is a Gigabit Ethernet-, or 10 Gigabit Ethernet XAUI-,
specific block that controls reading and writing from the FIFO buffer,
while the generic FIFO controls reading and writing with write-enable or
read-enable signals specified from the logic array. The FIFO buffer modes
are: rate matching XAUI, rate matching GIGE, and generic FIFO.
■
■
■
In rate matching XAUI mode, the FIFO write clock (i.e., wrclk) is
connected to the recovered clock of channel 0. The write-enable and
read-enable signals (i.e., we and re) are controlled by the protocol,
which inserts or deletes //R// (i.e., idle) groups into the data
stream. Writing and reading is controlled by the number of //R//
groups seen. The rate matcher in XAUI mode keeps track of the
number of writes and reads to the FIFO with the FIFO counter
register. The rate matcher in XAUI mode deletes /R/ from all the
channels when the FIFO counter is above 9, and inserts /R/ to all the
channels when the FIFO counter is below 4, which prevents FIFO
overflow and underflow, respectively.
In rate matching GIGE mode, the clock connections are the same as
rate matching XAUI mode, but instead of inserting or deleting //R//
groups, /I2/ ordered sets are inserted or deleted to control writing
and reading of the FIFO. In the rate matching GIGE mode, FIFO
overflow and underflow are handled in the same way as rate
matching XAUI mode, except each channel performs its own rate
matching.
In generic FIFO mode, the designer controls the FIFO using re and
we signals.
8B/10B Decoder
After leaving the channel aligner and rate matcher, the receive data enters
the 8B/10B decoder. The 8B/10B decoder translates a 10-bit parallel data
stream into 8-bit data. Figure 22 shows the block diagram of the 8B/10B
decoder. Data leaving the decoder is 10-bits wide, and contains the control
bit and disparity error bit as well as the 8-bit decoded data.
Figure 22. 8B/10B Decoder Block Diagram
Data [7..0]
Data [9..0]
Disparity Error
8B/10B
Decoder
Error Detect
Data and control [9..0]
K Code
Invalid code [1..0]
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The error detect signal is set when the detector detects an invalid code.
The K code signal is set when the output data is a valid command byte
(Kx.y) and not a data byte (Dx.y). The disparity error signal, which is
synchronous to the data, is set when the decoder detects a running
disparity error. The invalid code control signals are input back into the
decoder—after the initial data transmission. The designer can control
which codes are invalid for a particular protocol. Table 12 shows the
options for the invalid codes, which are specified during device
configuration.
Table 12. INVALID_CODE Setting
Group Setting
Invalid Codes
1
K28.1, K28.3, K28.4, K28.7
2
K28.6
The 8B/10B decoder can operate in two modes: XAUI mode or standard
mode. In XAUI mode, all four channels operate together and the XAUI
state machine controls the decoding process where various idle codegroups are mapped to a 10-Gigabit Medium Independent Interface
(XGMII)-specific 8B/10B idle code, and error code-groups are specially
handled depending on their occurring location. In standard mode, each
receiver channel operates independently. The 8B/10B decoder can also be
bypassed.
Receiver Logic Array Interface
Before the data goes to the Stratix GX logic array, it may need to go
through the demultiplexer and receiver synchronization FIFO for phase
alignment. To bring the data rate to a speed supported by the logic array,
the phase alignment stage allows receiver data going to the logic array to
be either single- or double-width.
In single-width mode, the demultiplexer selects the 8-bit or 10-bit data bus
from the 8B/10B decoder at the same rate as the decoder. In double-width
mode, the byte deserializer expands the data to contain a 16- or 20-bit data
bus width at half the rate from the 8B/10B decoder.
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Because the synchronizer FIFO essentially sees only a bank of registers, it
provides a simpler clock scheme boundary from which to transfer data
(i.e., from the transceiver channels to the logic array). The FIFO’s write
clock comes from the logic array clock, a multiple of 1 or 2 of the recovered
clock(s), low-speed parallel clock from transmitter PLL, or the recovered
clock from channel 0 (i.e., in XAUI mode), whereas the FIFO’s read clock
comes from the logic array. Figure 23 shows the demultiplexer and
synchronization FIFO.
Figure 23. Receiver Demultiplexer & Synchronization FIFO
8 or 10
8, 10,
16, or 20
8- or 10-bit data
16 or 20
8-, 10-, 16-,
or 20-bit data
Receiver
Synchronization
FIFO
Logic array clock
Low-speed parallel clock
from transmitter PLL
Recovered clock
from channel
Recovered clock from
channel 0 (XAUI mode)
Transceiver
Clock
Distribution
Altera Corporation
Master Clock
All Stratix GX devices provide 16 dedicated global clock networks,
16 regional clock networks (i.e., four per device quadrant), and
8 dedicated fast regional clock networks. There are 12 dedicated clock
pins (i.e., CLK[11..0]) to drive either global or regional clock networks.
The recovered clocks (i.e., from the transceiver blocks) drive four
additional clock networks (i.e., CLK[15..12]). However, the recovered
clocks can either drive four regional clock networks or four global clock
networks (i.e., only one recovered clock per transceiver block can drive
the global or regional clock networks). Figure 24 shows the global and
regional clock connections for the side pins and transceiver blocks.
31
32
FPLL8CLK
CLK2
CLK3
CLK0
CLK1
FPLL7CLK
l0
PLL 8 l 1
g0
l0
l 02
PLL 2 l 1
g0
g0
PLL 1 l 1
l0
g0
PLL 7 l 1
Regional
Clocks
RCLK3
RCLK2
RCLK1
RCLK0
G0
G1
G2
G8
Global
Clocks
G3
G9
G11
G10
Regional
Clocks
RCLK9
RCLK8
RCLK11
RCLK10
(3)
4
(3)
4
(3)
4
(3)
4
Transceiver
Block
Transceiver
Block
Transceiver
Block
Transceiver
Block
Reference
Clock
Reference
Clock
Reference
Clock
Reference
Clock
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 24. Global & Regional Clock Connections from Side Pins & Transceiver Blocks (EP1SGX40
Device) Notes (1), (2)
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Notes to Figure 24:
(1)
(2)
(3)
PLLs 1,2 7, and 8 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs. PLLs 7 and 8 do not drive global clocks.
In EP1SGX40 devices that have five transceiver blocks, only four transceiver blocks can drive the global and local
clock networks.
The high-speed serial data stream in each transceiver block generates the recovered clocks. Each transceiver block
has four recovered clocks from the four transceiver channels. One of the four clocks drive the global and local clock
networks.
Figure 25 shows the clock routing throughout the Stratix GX transceiver
channel.
Figure 25. Stratix GX Transceiver Clock Routing
Low-Speed
Parallel Clock
Transmitter
Synchronization
FIFO
Transmitter logic
array clock
WR
RD
Multiplexer
8B/10B
Encoder
Serializer
WR
RD
WR
RD
High-Speed
Transmitter
Serial Clock
Receiver
PLL
and CRU
Transmitter
PLL
Recovered clock
High-Speed
Transmitter
Serial Clock
Divide by 1 or 2
Receiver logic
array clock
Recovered
Clock
WR
RD
WR
RD
Receiver
Synchronization
FIFO
Demultiplexer
f
Altera Corporation
8B/10B
Decoder
WR
RD
WR
RD
Rate
Matcher
Channel
Aligner
WR
RD
Word
Aligner
Deserializer
Recovered clock
from channel 0
See the Stratix GX FPGA Family Data Sheet for more information on
transceiver clocks.
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Transceiver
Internal Test
Modes
The Stratix GX transceiver has many internal test modes for verifying
functionality within the device. Each receiver/transmitter channel pair
has a BIST generator and verifier as well as a PRBS generator and verifier.
The BIST generator can produce regular PRBS data of 28 or 210 patterns, or
28-1 or 210-1 unique bit combinations. The PRBS generator can produce
regular PRBS data of 28 patterns, or 28-1 unique bit combinations. Along
with these internal generators and verifiers, the transceiver also has the
capability to test the Stratix GX device through various loopback modes.
By combining PRBS, BIST, and loopback operation, the transceiver can
perform these self-tests at full-speed and between two devices.
This section describes the following Stratix GX transceiver operation
modes:
■
■
■
Channel loopback
BIST generator & verifier
PRBS generator & verifier
Channel Loopback Modes
One method of testing the Stratix GX transceiver is using its channel
loopback modes. Loopback is defined where data from the transmitter
section is routed directly to the receiver section. Reverse loopback is
defined where data from the receiver section is routed directly to the
transmitter. The data can either be serial or parallel. There are three
different channel loopback modes:
■
■
■
■
Serial loopback
Reverse serial loopback
Parallel loopback
Reverse parallel loopback
Serial Loopback
In serial loopback mode, which is controlled via the logic array, the output
of the transmitter’s serializer loops back to the input of the receiver’s
deserializer. While in the serial loopback mode, the transmitter’s output
buffer still transmits data coming from the serializer with 80% of the
selected VOD setting. To deactivate the input buffer, internal pull-down
circuitry used only for serial loopback mode is activated on the input
buffer’s pin pair.
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Reverse Serial Loopback
In reverse serial loopback mode, the retimed data from the CRU loops
back to the transmitter’s output buffer.
Parallel Loopback
In parallel loopback mode, the data from the transmitter synchronizer
FIFO is looped back to the pattern detector and word aligner. The parallel
loopback mode can be either 10-bit parallel loopback, which comes from
the 8B/10B encoder, or 8-bit parallel loopback, which bypasses the
8B/10B encoder.
Reverse Parallel Loopback
In reverse parallel loopback mode, the data from the receiver
demultiplexer loops back to the transmitter synchronizer FIFO.
1
All loopback mode settings, with the exception of serial loopback
mode, are established at device configuration and can be selected
within the Quartus II software. Serial loopback mode is
controlled through the logic array and can be changed
dynamically. Loopback operations are only allowed when the
transmitter and receiver are placed on adjacent channels.
BIST Generator & Verifier
The BIST generator creates multiple data patterns, which can be verified
by the BIST verifier. If the incoming data does not match the locally
generated data in the verifier, the test fails. In BIST test mode 0, the BIST
generator can produce a PRBS pattern in the transmitter with a
corresponding PRBS pattern in the verifier at the receiver. Both generator
and verifier can work with 10- or 8-bit data patterns. (However, in the
latter case, the generator will fill the upper two bits with 1’s). If operating
in 10-bit mode, or 28-1 patterns in 8-bit mode, the pattern generator
produces 210 - 1 unique bit combinations in the PRBS bit stream. This
feature is very useful for testing both transmitter and receiver
performance. Table 13 summarizes the BIST and its corresponding
pattern test modes. If BIST is enabled (BISTEN=1), the modes in Table 13
will be the modes of the BIST generator.
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Table 13. BIST Generator Test Modes
BIST Test Mode
Pattern Generated
10
0
PRBS 2
1
00-FF incremental pattern includes K28.5 /S/ and /T/
– 1 repetitive patterns with 8B/10B bypass
2
High Frequency Pattern 1010101010 (D21.5)
3
Low Frequency Pattern 0011111000 (K28.7)
4
Mixed Frequency Pattern 0011111010 - 1100000101
The BIST operates in three channel loopback modes:
■
■
■
BIST 8B parallel loopback
BIST parallel loopback
BIST serial loopback
BIST 8B Parallel Loopback Mode
The BIST 8B parallel loopback path (see Figure 26) runs through the
transmitter synchronization FIFO, the multiplexer (optional), the
demultiplexer (optional), and the receiver synchronization FIFO.
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Altera Corporation
Receiver
Transmitter
BIST
Pattern
Verifier
Demultiplexer
(1-to-2) and
Receiver FIFO
Reverse Parallel
Loopback
BIST
Pattern
Generator
8B/10B
Decoder
Rate
Matcher
and
Channel
Aligner
Multiplexer
(2-to-1) and
Transmitter FIFO
PRBS
Pattern
Verifier
Pattern
Detector
and Word
Aligner
Parallel
Loopback
8B/10B
Encoder
PRBS
Pattern
Generator
Receiver
PLL
Clock
Recovery
Unit
Serial-toParallel
Parallelto-Serial
Transmitter
PLL
Reference
Clock
Reverse Serial
Loopback
Serial
Loopback
Enable
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 26. BIST 8B Parallel Loopback Path
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BIST Parallel Loopback Mode
The BIST parallel loopback path (see Figure 27) runs through the
transmitter synchronization FIFO, the multiplexer (optional), the 8B/10B
encoder (optional), the word aligner, the 8B/10B decoder (optional), the
demultiplexer (optional), and the receiver synchronization FIFO.
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Altera Corporation
Receiver
Transmitter
BIST
Pattern
Verifier
Demultiplexer
(1-to-2) and
Receiver FIFO
Reverse Parallel
Loopback
BIST
Pattern
Generator
8B/10B
Decoder
Rate
Matcher
and
Channel
Aligner
Multiplexer
(2-to-1) and
Transmitter FIFO
PRBS
Pattern
Verifier
Pattern
Detector
and Word
Aligner
Parallel
Loopback
8B/10B
Encoder
PRBS
Pattern
Generator
Receiver
PLL
Clock
Recovery
Unit
Serial-toParallel
Parallelto-Serial
Transmitter
PLL
Reference
Clock
Reverse Serial
Loopback
Serial
Loopback
Enable
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 27. BIST Parallel Loopback Path
39
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
BIST Serial Loopback Mode
The BIST serial loopback path (see Figure 28) runs through the transmitter
synchronization FIFO, the multiplexer (optional), the 8B/10B encoder
(optional), the serializer, the deserializer, the word aligner, the 8B/10B
decoder (optional), the demultiplexer (optional), and the receiver
synchronization FIFO.
40
Altera Corporation
Altera Corporation
Receiver
Transmitter
BIST
Pattern
Verifier
Demultiplexer
(1-to-2) and
Receiver FIFO
Reverse Parallel
Loopback
BIST
Pattern
Generator
8B/10B
Decoder
Rate
Matcher
and
Channel
Aligner
Multiplexer
(2-to-1) and
Transmitter FIFO
PRBS
Pattern
Verifier
Pattern
Detector
and Word
Aligner
Parallel
Loopback
8B/10B
Encoder
PRBS
Pattern
Generator
Receiver
PLL
Clock
Recovery
Unit
Serial-toParallel
Parallelto-Serial
Transmitter
PLL
Reference
Clock
Reverse Serial
Loopback
Serial
Loopback
Enable
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 28. BIST Serial Loopback Path
41
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
PRBS Generator & Verifier
The PRBS generator creates multiple data patterns, which can be verified
by the PRBS pattern verifier. (The PRBS generator bypasses the 8B/10B
encoder.) The PRBS pattern verifier also systematically generates
210 – 1 bit combinations (or 28 – 1 bit combinations) in the pseudo-random
data stream. This is a self-synchronized process because patterns are
repetitive after 1,023 patterns (or 255 patterns for 28 – 1 bit combinations);
also, the generator always sends a preamble of an “all ones” pattern before
sending the random sequence, and the verifier starts checking incoming
data only after it detects the “all ones” pattern.
The PRBS verifier compares the incoming data stream with the locally
generated data. If an error is detected, the BIST flag will be set, and the bit
error rate can be calculated using logic outside the transceiver. The PRBS
generator and verifier operate in two channel loopback modes (see
Figures 29 and 30):
■
■
42
PRBS parallel loopback
PRBS serial loopback
Altera Corporation
Altera Corporation
Receiver
Transmitter
BIST
Pattern
Verifier
Demultiplexer
(1-to-2) and
Receiver FIFO
Reverse Parallel
Loopback
BIST
Pattern
Generator
8B/10B
Decoder
Rate
Matcher
and
Channel
Aligner
Multiplexer
(2-to-1) and
Transmitter FIFO
PRBS
Pattern
Verifier
Pattern
Detector
and Word
Aligner
Parallel
Loopback
8B/10B
Encoder
PRBS
Pattern
Generator
Receiver
PLL
Clock
Recovery
Unit
Serial-toParallel
Parallelto-Serial
Transmitter
PLL
Reference
Clock
Reverse Serial
Loopback
Serial
Loopback
Enable
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 29. PRBS Parallel Loopback Path
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
The PRBS parallel loopback bypasses the 8B/10B encoder and goes
through the word aligner. The PRBS serial loopback mode also bypasses
the 8B/10B encoder, but it goes through the serializer, the CRU, the
deserializer, and the word aligner.
44
Altera Corporation
Altera Corporation
Receiver
Transmitter
BIST
Pattern
Verifier
Demultiplexer
(1-to-2) and
Receiver FIFO
Reverse Parallel
Loopback
BIST
Pattern
Generator
8B/10B
Decoder
Rate
Matcher
and
Channel
Aligner
Multiplexer
(2-to-1) and
Transmitter FIFO
PRBS
Pattern
Verifier
Pattern
Detector
and Word
Aligner
Parallel
Loopback
8B/10B
Encoder
PRBS
Pattern
Generator
Receiver
PLL
Clock
Recovery
Unit
Serial-toParallel
Parallelto-Serial
Transmitter
PLL
Reference
Clock
Reverse Serial
Loopback
Serial
Loopback
Enable
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Figure 30. PRBS Serial Loopback Path
45
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Other
Transceiver
Features
Other important features of the Stratix GX transceivers are the power
down and reset capabilities, the external voltage reference and bias
circuitry, and hot swapping.
Individual Power-Down & Reset for the Transmitter & Receiver
Stratix GX transceivers offer a power saving advantage with their ability
to shut off functions that are not needed. The device can individually reset
the receiver and transmitter blocks and the PLLs. Reset functions depend
on the Stratix GX logic array configuration, test, and functionality. The
Stratix GX device can either globally power down and reset the
transmitter and receiver channels or do each channel separately. Table 14
shows the Stratix GX transceiver resets and their corresponding
functional descriptions.
Power-down functions are static, i.e., they are implemented upon device
configuration and programmed, through the Quartus II software, to static
values. Resets can be static as well as dynamic inputs coming from the
logic array or pins. The reset functions are asynchronous signals.
Table 14. Resets & Functional Descriptions
Function
Signal Name
Description
Receiver analog reset
RXPMA[3:0]_RST
0: Normal mode
1: Reset all logic, bias, and receiver PLL
Transmitter PLL reset
TXPLL_RST
0: Normal mode
1: Reset transmitter PLL to begin lock acquisition
Receiver digital reset
RXPCS[3:0]_RST
0: Normal mode
1: Reset all low speed logic in receiver
Transmitter PCS reset
TXPCS[3:0]_RST
0: Normal mode
1: Reset all low speed logic in transmitter
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Altera Corporation
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Voltage Reference Capabilities
Stratix GX transceivers provide voltage reference and bias circuitry. To
set-up internal bias for controlling the transmitter output drivers’ voltage
swing—as well as to provide voltage/current biasing for other analog
circuitry—the internal bandgap voltage reference at 0.7 V is used. To
provide bias for internal pull-up PMOS resistors for I/O termination at
the serial interface of receiver and transmitter channels (independent of
power supply drift, process changes, or temperature variation) an
external resistor, which is connected to the external low voltage power
supply, is accurately tracked by the internal bias circuit (i.e., within ±3%).
Moreover, the reference voltage and internal resistor bias current is
generated and replicated to the analog circuitry in each channel.
Hot-Socketing Capabilities
Each Stratix GX device is capable of hot-socketing. Because Stratix GX
devices can be used in a mixed-voltage environment, they have been
designed specifically to tolerate any possible power-up sequence. Signals
can be driven into Stratix GX devices before and during power-up
without damaging the device. Once operating conditions are reached and
the device is configured, Stratix GX devices operate as specified by the
designer. This feature provides the Stratix GX transceiver line card
behavior so you can insert it into the system without powering the system
down, offering the designer more flexibility.
Applications/
Protocols
Supported with
Stratix GX
Devices
Each Stratix GX transceiver block is designed to operate at any serial bit
rate from 622 Mbps to 3.125 Gbps per channel. The wide, data rate range
allows Stratix GX transceivers to support a wide variety of standard and
future protocols such as: Gigabit Ethernet, 10 Gigabit Ethernet XAUI,
InfiniBand, Fibre Channel, and Serial RapidIO. Stratix GX devices are
ideal for many high-speed communication applications such as highspeed backplanes, chip-to-chip bridges, and high-speed serial
communications standards support.
Stratix GX Example Application Support
Stratix GX devices can be used for many applications, including:
■
■
■
Altera Corporation
Backplanes for traffic management & quality of service (QOS)
Switch fabric applications for complete set for backplane & switch
fabric transceivers
Chip-to-chip applications such as: 10 Gigabit Ethernet XAUI to
XGMII bridge, 10 Gigabit Ethernet XGMII to POS-PHY4 bridge, POSPHY4 to NPSI bridge, or NPSI to backplane bridge
47
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
1
Stratix GX devices provide complete backplane solutions for the
following applications: 10 Gigabit Ethernet XAUI Physical layer,
SONET backplane, InfiniBand Physical layer, Serial RapidIO, or
proprietary backplane applications.
High-Speed Serial Bus Protocols
With wide, serial-data-rate range and components and embedded blocks
in its transceivers, Stratix GX devices can support multiple, high-speed
serial bus protocols. Table 15 shows some of the protocols that Stratix GX
devices can support and Table 16 shows the transceiver dedicated
circuitry needed to support each protocol.
Table 15. High-Speed Serial Bus Protocols
Bus Transfer Protocol
Number of Data
Channels
Stratix GX
(Supports 3.125 Gbps)
SONET Backplane
4 to 16
2.488 Gbps
10 Gigabit Ethernet XAUI
Backplane
4 to 16
3.125 Gbps
10 Gigabit Ethernet XAUI Line
Side
4
3.125 Gbps
Gigabit Ethernet Backplane
1
1.25 Gbps
InfiniBand
1, 4, or 12
2.5 Gbps
2G Fibre Channel
1
2.125 Gbps
1G Fibre Channel
1
1.0625 Gbps
RapidIO (Serial)
1 or 4
1.25, 2.5, 3.125 Gbps
PCI Express
16
2.5 Gbps
SMPTE 292M
1
1.485 Gbps
SFI-5 (1)
17 or 18
2.488 to 3.125 Gbps
SPI-5 (1)
17 or 18
2.488 to 3.125 Gbps
™
Note to Table 15:
(1)
48
Stratix GX devices are SFI-5/SPI-5 compatible.
Altera Corporation
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Table 16. Dedicated Circuitry for Stratix GX Device Protocols
Transceiver Elements
Supported Interface Protocols
10 Gigabit
Ethernet XAUI
1 Gigabit
Ethernet
Serial
RapidIOTM
Fibre Channel
InfiniBand
CDR
v
v
v
v
v
SERDES
v
v
v
v
v
Pattern detector
v
v
v
v
v
Word aligner
v
v
v
v
v
8B/10B
encoder/decoder
v
v
v
v
v
Channel aligner
v
Rate matcher
v
v
Synchronizer
v
v
v
v
v
Word aligner state
machine (1)
v
v
Transmitter state
machine
v
Receiver state
machine
v
Note to Table 16:
(1)
For the InfiniBand, Fibre Channel, and Serial RapidIO interface protocols, the word aligner state machine can be
implemented in the logic array.
1
Stratix GX devices directly support 10 Gigabit Ethernet XAUI
and 1 Gigabit Ethernet with the dedicated circuitry to implement
these protocols inside the Stratix GX transceiver blocks.
Stratix GX transceiver blocks also support InfiniBand, Fibre
Channel, and Serial RapidIO protocols.
10 Gigabit Ethernet XAUI Protocol
10 Gigabit Ethernet XAUI is a protocol where all four transceiver channels
operate together. While in XAUI mode, the Stratix GX transceiver blocks
use all of their integrated circuitry blocks, including dedicated state
machines such as: XAUI transmitter, XAUI receiver, and XAUI deskew
state machines.
f
Altera Corporation
For more information about 10 Gigabit Ethernet XAUI implementations,
see AN 220: Implementing 10-Gigabit Ethernet Using Stratix Devices and
AN 249: Implementing XAUI Using Stratix GX Devices.
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
State Machine Blocks
This section explains how the aforementioned state machines are used to
support the 10 Gigabit Ethernet XAUI protocol.
The XAUI transmitter and receiver state machines conform to the IEEE
Draft P802.3ae/D3.2 document, Section 48.2.5.2.4. The state machines
provide Stratix GX devices a seamless integration of 10 Gigabit Ethernet
XAUI to XGMII.
XAUI Transmitter State Machine
The XAUI transmitter state machine interfaces to the 8B/10B encoder and
translates XGMII characters to 8B/10B characters. At reset, the XAUI
transmitter state machine transmits /A/, /K/, and /R/ characters. The
character //A// is sent after “r” non //A// columns, where “r” is a
random number between 16 and 31, generated by the PRBS polynomial of
X7 + X6 + 1. The characters //K// or //R// are sent based on “r” being
even or odd.
XAUI Receiver State Machine
The XAUI receiver state machine interfaces with the rate matcher and
translates 8B/10B characters to XGMII characters. At reset, the XAUI
receiver state machine transmits a Link Fault condition. The XAUI receiver
state machine translates /A/, /K/, and /R/ characters to XGMII IDLE’s,
and detects disparity error propagation to //T// and columns next to
//T// and substitutes /E/ characters.
XAUI Deskew State Machine
The XAUI deskew state machine meets the IEEE specification maximum
skew spec of 41 UI between receiver inputs (i.e., approximately 5 parallel
clock cycles). When XAUI is enabled, the deskew state machine, which
interfaces with the channel aligner’s deskew FIFO buffer, activates the
deskew FIFO when the character /A/ is found. When /A/ is found in all
4 channels, the deskew state machine enables the reading of data from the
deskew FIFO. Also, ALIGN_STATUS is set to OK. Afterwards, the deskew
state machine monitors the reception of /A/ columns that are not aligned
and responds as specified by the relevant 10 Gigabit Ethernet XAUI
standard clause.
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Altera Corporation
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
1 Gigabit Ethernet
The 1 Gigabit Ethernet mode operates as one transceiver block but unlike
the 10 Gigabit Ethernet XAUI mode, each transceiver channel operates
independently. Thus, the 1 Gigabit Ethernet mode does not need the
XAUI deskew state machine. The 1 Gigabit Ethernet mode does, however,
use the XAUI transmitter and receiver state machines.
Other Protocols
The InfiniBand, Fibre Channel, and Serial RapidIO protocols use the same
structure as 1 Gigabit Ethernet protocol with the following exceptions:
■
■
■
■
Stratix GX
Transceiver
I/O Signals
XAUI state machines are not used
Synchronization is implemented inside the logic array
The rate matching FIFO buffer is set to Generic FIFO mode, where the
designer controls the FIFO buffer using re and we signals from the
logic array.
InfiniBand protocol only: The transmitter uses the force disparity
mode to control the disparity of the 8B/10B encoder. The receiver has
a preprogrammed invalid code that allows the 8B/10B decoder to
recognize more invalid characters than the standard 8B/10B decoder.
Tables 17 and 18 describe the Stratix GX transceiver I/O ports. Table 17
describes the transceiver input ports.
Table 17. Stratix GX Input Ports (Part 1 of 3)
Port Name
Description
Note (1)
Comments
inclk[]
Transmitter PLL and receiver
PLL reference input clock.
Input port [NUMBER_OF_QUADS - 1..0] wide. If the
transmitter PLL and receiver PLL are used, the inclk[]
port is required. If the OPERATION_MODE parameter is set
to TX or DUPLEX, the inclk[] port is required.
coreclk[]
Clock from the device’s logic
array.
Input port [NUMBER_OF_CHANNELS - 1..0] wide. When
the OPERATION_MODE is set to TX or DUPLEX, the
coreclk port cannot be used.
pll_areset[]
Asynchronous clear for the
transmitter and receiver PLLs.
Input port [NUMBER_OF_QUADS - 1..0] wide.
rx_in[]
Receiver channel data input
port.
Input port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_cruclk[]
CRU reference input clock.
Input port [NUMBER_OF_QUADS - 1..0] wide.
Altera Corporation
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AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Table 17. Stratix GX Input Ports (Part 2 of 3)
Port Name
Description
Note (1)
Comments
rx_aclr[]
Asynchronous clear for the
receiver channels.
Input port [NUMBER_OF_CHANNELS - 1..0] wide. The
rx_aclr input port must connect to the
rxdigitalreset input port of the receiver channel.
rx_bitslip[]
Bit slippage input. Enables bit
slippage.
Input port [NUMBER_OF_CHANNELS - 1..0] wide. The
rx_bitslip input port can be used only when the
USE_AUTO_BIT_SLIP parameter is set to OFF.
rx_enacdet[]
Comma detection input.
Enables comma detection.
Input port [NUMBER_OF_CHANNELS - 1..0] wide. The
rx_enacdet input port can be used only when the
USE_AUTO_BIT_SLIP parameter is set to OFF.
rx_we[]
Write enable input. Enables
write operations from the rate
matching FIFO.
Input port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_re[]
Read enable input. Enables
read operations to the rate
matching FIFO.
Input port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_slpbk[]
Serial loopback input. Enables Input port [NUMBER_OF_CHANNELS - 1..0] wide. If the
serial loopback.
rx_slpbk input port is connected, the
OPERATION_MODE is set to DUPLEX and the
serialfdbk port of the receiver channel must be
connected.
rx_a1a2size[]
Comma detection input for
A1A2 or A1A1A2A2 commas.
rx_equalizerc
trl[]
Indicates whether to control the Input port [NUMBER_OF_CHANNELS - 1..0] wide.
equalizer.
rx_locktorefc
lk[]
Control signal for the receiver
PLL to lock the CRU.
Input port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_locktodata
[]
Control signal for the receiver
PLL to lock the received data.
Input port [NUMBER_OF_CHANNELS - 1..0] wide. The
rx_locktodata port can overwrite the
rx_locktorefclk port.
52
Input port [NUMBER_OF_CHANNELS - 1..0] wide. The
rx_a1a2size port can be used only when the PROTOCOL
parameter is set to SONET.
Altera Corporation
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Table 17. Stratix GX Input Ports (Part 3 of 3)
Port Name
Description
Note (1)
Comments
tx_in[]
Transmitter channel data input Input port [CHANNEL_WIDTH *
port.
NUMBER_OF_CHANNELS - 1..0] wide. If the
USE_8B_10B_MODE parameter is set to OFF and the
USE_DOUBLE_DATA_MODE parameter is set to ON, the
DESERIALIZATION_FACTOR parameter value is
CHANNEL_WIDTH. If the USE_8B_10B_MODE parameter
is set to OFF and the USE_DOUBLE_DATA_MODE
parameter is set to OFF, the
DESERIALIZATION_FACTOR parameter value is
CHANNEL_WIDTH / 2. If the USE_8B_10B_MODE
parameter is set to ON, the DESERIALIZATION_FACTOR
parameter value is 10.
tx_aclr[]
Asynchronous clear for the
transmitter channels.
Input port [NUMBER_OF_CHANNELS - 1..0] wide. The
tx_aclr input port must connect to the
txdigitalreset input port of the transmitter channel.
tx_ctrlenable
[]
Control character enable.
Enables 8B/10B encoder to
identify control characters.
Input port [NUMBER_OF_CHANNELS *
DWIDTH_FACTOR - 1..0] wide. If tx_ctrlenable
output port is high, the data being sent is a control
character and not data.
tx_forcedispa
rity[]
Disparity enable. Enables
8B/10B encoder to identify
disparity.
Input port [NUMBER_OF_CHANNELS *
DWIDTH_FACTOR - 1..0] wide. If tx_forcedisparity
input port is high, positive disparity (more 1s than 0s) is
used.
tx_srlpbk[]
Serial loopback input. Enables Input port [NUMBER_OF_CHANNELS - 1..0] wide.
serial loopback.
tx_vodctrl[]
Input port [NUMBER_OF_CHANNELS - 1..0] wide.
tx_preemphasi
sctrl[]
Input port [NUMBER_OF_CHANNELS - 1..0] wide.
txdigitalrese
t[]
Input port [NUMBER_OF_QUADS * 4 - 1..0] wide.
rxdigitalrese
t[]
Input port [NUMBER_OF_QUADS * 4 - 1..0] wide.
rxanalogreset
[]
Input port [NUMBER_OF_QUADS * 4 - 1..0] wide.
pllenable[]
Input port [NUMBER_OF_QUADS - 1..0] wide.
Note to Table 17:
(1)
For the most up-to-date Stratix GX input port descriptions, see the altgxb megafunction in the Quartus II software.
Altera Corporation
53
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Table 18 describes the transceiver output ports.
Table 18. Stratix GX Output Ports (Part 1 of 2)
Port Name
Description
Note (1)
Comments
pll_locked[]
Gives the status of the
transmitter PLL and receiver
PLL.
Output port [NUMBER_OF_QUADS - 1..0] wide. The
pll_locked port is available only when the transceiver
PLL is used.
coreclk_out[]
Output clock feed from the clk2 Output port [NUMBER_OF_QUADS - 1..0] wide. If a
port of the transmitter PLL or
transmitter PLL and receiver PLL are used, the
receiver PLL.
coreclk_out output port is used.
rx_channelaligned Channel alignment for the
[]
transmitter PLL or receiver
PLL.
Output port [NUMBER_OF_QUADS - 1..0] wide. When the
PROTOCOL parameter is “XAUI”, the
rx_channelaligned port must be connected.
rx_out[]
Deserialized data signal.
Output port [CHANNEL_WIDTH *
NUMBER_OF_CHANNELS - 1..0] wide. If the
USE_8B_10B_MODE parameter is set to OFF and
USE_DOUBLE_DATA_MODE is set to ON, the
DESERIALIZATION_FACTOR parameter value is
CHANNEL_WIDTH. If the USE_8B_10B_MODE parameter
is set to OFF and USE_DOUBLE_DATA_MODE is set to
OFF, the DESERIALIZATION_FACTOR parameter value
is CHANNEL_WIDTH / 2. If the USE_8B_10B_MODE
parameter is set to OFF, the
DESERIALIZATION_FACTOR parameter value is 10.
rx_clkout[]
Internal reference clock.
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_locked[]
Gives the status of the receiver Output port [NUMBER_OF_CHANNELS - 1..0] wide.
channel.
rx_freqlocked[]
Indicates whether receiver
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
channel has locked to the
receiver PLL frequency but not
to the rx_in port.
rx_rlv[]
Indicates whether the receiver Output port [NUMBER_OF_CHANNELS - 1..0] wide.
channel has violated the value
specified for the
RUN_LENGTH parameter.
rx_syncstatus[]
Gives the status of the pattern
detector and word aligner.
Output port [NUMBER_OF_CHANNELS *
DWIDTH_FACTOR - 1..0] wide.
rx_patterndetect[]
Indicates whether the pattern
detector detects a comma.
Output port [NUMBER_OF_CHANNELS *
DWIDTH_FACTOR - 1..0] wide.
rx_ctrldetect[]
Indicates whether the 8B/10B Output port [NUMBER_OF_CHANNELS *
decoder detects a control code. DWIDTH_FACTOR - 1..0] wide. If the USE_8B_10B_MODE
parameter is specified to "OFF", the rx_ctrldetect port
is not available.
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Altera Corporation
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Table 18. Stratix GX Output Ports (Part 2 of 2)
Port Name
Description
Note (1)
Comments
rx_errdetect[]
Indicates whether the 8B/10B
decoder detects a code error.
Output port [NUMBER_OF_CHANNELS *
DWIDTH_FACTOR - 1..0] wide. If the USE_8B_10B_MODE
parameter is specified to "OFF", the rx_errdetect port
is not available.
rx_disperr[]
Indicates whether the 8B/10B
decoder detects a disparity
error.
Output port [NUMBER_OF_CHANNELS *
DWIDTH_FACTOR - 1..0] wide.
rx_signaldetect[]
Indicates whether there is a
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
legal voltage level on the input
buffer.
rx_fifoempty[]
Indicates when the rate
matching FIFO is less than
4 bytes of data.
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_fifofull[]
Indicates when the rate
matching FIFO is equal to
13 bytes of data.
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_fifoalmostempt
y[]
Indicates when the rate
matching FIFO is less than
7 bytes of data.
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_fifoalmostfull[]
Indicates when the rate
matching FIFO is greater than
9 bytes of data.
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_bisterr[]
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_bistdone[]
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
rx_a1a2sizeout[]
tx_out[]
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
Serialized transmitter channel
data signal.
Output port [NUMBER_OF_CHANNELS - 1..0] wide.
Note to Table 18:
(1)
For the most up-to-date Stratix GX output port descriptions, see the altgxb megafunction in the Quartus II
software.
Altera Corporation
55
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Table 19 describes the Stratix GX I/O parameters.
Table 19. Stratix GX I/O Parameters (Part 1 of 2)
Parameter
Note (1)
Comments
OPERATION_MODE
Specifies the operation of the transmitter PLL and receiver PLL. Values are
“RX”, “TX”, and “DUPLEX”.
LOOPBACK_MODE
Specifies the operation of the loopback. Values are “NONE”, “SLB”, “PLB”,
and “P8LB”.
REVERSE_LOOPBACK_MODE
Specifies the operation of the reverse loopback. Values are “NONE”,
“RSLB”, and “RPLB”.
PROTOCOL
Specifies the protocol. Values are “XAUI”, “GIGE”, “RAPIDIO”,
“FIBRECHANNEL”, and “CUSTOM”.
NUMBER_OF_CHANNELS
Specifies the number of receiver channels.
NUMBER_OF_QUADS
Specifies the number of transceivers.
CHANNEL_WIDTH
Specifies the width of the receiver channel. Values are 8, 10, 16, and 20.
PLL_INCLOCK_PERIOD
Specifies the period or frequency of the transmitter PLL and receiver PLL.
When the PLL_INCLOCK_PERIOD parameter is specified, the
CRU_INCLOCK_PERIOD parameter cannot be used.
DATA_RATE
Specifies the rate of data from the transmitter channel.
DATA_RATE_REMAINDER
USE_8B_10B_MODE
Specifies whether to use the 8B/10B decoder.
USE_DOUBLE_DATA_MODE
Specifies whether to use double data mode. If the
USE_DOUBLE_DATA_MODE parameter is specified to ON, the
CHANNEL_WIDTH parameter value is 16 or 20. When the CHANNEL_WIDTH
parameter value is 8 or 16, the receiver channel is not in double data mode.
DWIDTH_FACTOR
Specifies the width of the double data factor.
DISPARITY_MODE
Specifies whether to use disparity mode.
CRU_INCLOCK_PERIOD
Specifies the period or frequency of the CRU. When the
CRU_INCLOCK_PERIOD is specified, the PLL_INCLOCK_PERIOD
parameter cannot be used.
RUN_LENGTH
Specifies the maximum run length allowed for the incoming data signal.
RUN_LENGTH_ENABLE
Specifies whether to use the run length detection.
USE_CHANNEL_ALIGN
Specifies whether to use the channel aligner. The USE_CHANNEL_ALIGN
parameter can only be used when the PROTOCOL parameter is specified to
XAUI.
USE_AUTO_BIT_SLIP
Specifies whether to use auto bit slippage.
USE_RATE_MATCH_FIFO
Specifies whether to use rate matching FIFO.
USE_SYMBOL_ALIGN
Specifies whether to use the the word aligner.
ALIGN_PATTERN
Specifies the value used by the comma detector for the
USE_SYMBOL_ALIGN parameter. If the USE_SYMBOL_ALIGN parameter is
specified to OFF, this value is not used.
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Altera Corporation
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
Table 19. Stratix GX I/O Parameters (Part 2 of 2)
Parameter
Note (1)
Comments
ALIGN_PATTERN_LENGTH
Specifies the length of the ALIGN_PATTERN parameter. Values are “7”,
“10”, or “16”.
INFINIBAND_INVALID_CODE
Specifies the codes that are illegal for the Infiniband protocol. Values are
“0”, “1”, “2”, or “3”.
CLK_OUT_MODE_REFERENCE
Specifies whether to use the clock that operates the post rate matching
FIFO buffer of the receiver channel.
USE_FIFO_MODE
Specifies whether to use FIFO mode.
SELF_TEST_MODE
USE_EQUALIZER_CTRL_SIGNAL
EQUALIZER_CTRL_SETTING
SIGNAL_LOSS_THRESHOLD_SEL
ECT
RX_BANDWIDTH_TYPE
RX_ENABLE_DC_COUPLING
Specifies whether to use force disparity mode.
FORCE_DISPARITY_MODE
USE_VOD_CTRL_SIGNAL
VOD_CTRL_SETTING
USE_PREEMPHASIS_CTRL_SIGN
AL
PREEMPHASIS_CTRL_SETTING
RX_USED
TX_USED
USE_CONTINUOUS_CALIBRATIO
N_MODE
RX_PPM_SETTING
Note to Table 19:
(1)
For the most up-to-date Stratix GX I/O parameter descriptions, see the altgxb megafunction in the Quartus II
software.
Conclusion
By providing a solution for complex, multi-gigabit designs, as well as a
flexible interface for high-speed serial bus protocols such as 10-Gigabit
Ethernet XAUI, InfiniBand, Gigabit Ethernet, Fibre Channel, and Serial
RapidIO, the Stratix GX device family meets the need for device flexibility
while also satisfying multi-gigabit data rate requirements.
The Stratix GX transceiver block enables high-speed backplane, line side,
and chip-to-chip applications that are rapidly emerging in high-speed,
data-intensive technologies. With its embedded IP blocks, low power
consumption, programmable features, and flexible architecture,
Stratix GX transceivers offer a powerful tool for system designers.
Altera Corporation
57
AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
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(800) 800-EPLD
Literature Services:
lit_req@altera.com
58
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