Documents by Type
March 2003
Data Sheets
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
a6850 Asynchronous Communications Interface Adapter Data Sheet
a8237 Programmable DMA Controller Data Sheet
a8251 Programmable Communications Interface Data Sheet
a8255 Programmable Peripheral Interface Adapter Data Sheet
a8259 Programmable Interrupt Controller Data Sheet
ACEX 1K Programmable Logic Family Data Sheet
Active Serial Memory Interface Data Sheet
Altera Device Package Information Data Sheet
Altera Programming Hardware Data Sheet
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20KC Programmable Logic Device Data Sheet
APEX 20KE PCI Development Board Data Sheet
APEX II Programmable Logic Device Family Data Sheet
APEX DSP Development Board (Professional Version) Data Sheet
APEX DSP Development Board (Starter Version) Data Sheet
APEX PCI Development Board Data Sheet
Excalibur Device Overview Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
Classic EPLD Family Data Sheet
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Cyclone FPGA Family Data Sheet
FLEX 10K Embedded Programmable Logic Data Sheet
FLEX 10KE Embedded Programmable Logic Data Sheet
Altera Corporation
1
Documents by Type
FLEX 8000 Programmable Logic Device Family Data Sheet
FLEX 6000 Programmable Logic Device Family Data Sheet
FLEX PCI Development Board Data Sheet
HardCopy Devices for APEX 20K Conversion
Legacy SDRAM Controller with Avalon Interface Data Sheet
MasterBlaster Serial/USB Communications Data Sheet
MAX 9000 Programmable Logic Device Family Data Sheet
MAX 7000 Programmable Logic Device Family Data Sheet
MAX 7000A Programmable Logic Device Family Data Sheet
MAX 7000B Programmable Logic Device Family Data Sheet
MAX 3000A Programmable Logic Device Family Data Sheet
Mercury Gigabit Transceiver MegaCore Function (M1GXCVR) Data Sheet
Mercury Programmable Logic Device Family Data Sheet
Nios 3.0 CPU Data Sheet
Nios Development Board, Stratix Edition Data Sheet
Nios DMA Data Sheet
Nios PIO Data Sheet
Nios SPI Data Sheet
Nios Timer Data Sheet
Nios Embedded Processor Development Board Data Sheet (APEX Device)
Nios Soft Core Embedded Processor Data Sheet
Nios UART Data Sheet
Operating Requirements for Altera Devices Data Sheet
PCI Compiler Data Sheet
QFP Carrier & Development Socket Data Sheet
SDRAM Controller with Avalon Interface Data Sheet
Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet
SignalTap Embedded Logic Analyzer Megafunction Data Sheet
SOPC Builder Data Sheet
Stratix Programmable Logic Device Family Data Sheet
Stratix GX FPGA Family Data Sheet
Application Notes
AN 33
2
Configuring FLEX 8000 Devices
Altera Corporation
Documents by Type
AN 36
Designing with FLEX 8000 Devices
AN 38
Configuring Multiple FLEX 8000 Devices
AN 39
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices
AN 42
Metastability in Altera Devices
AN 43
Designing with MAX 9000 Devices
AN 46
ATM Packet Scheduler in FLEX 8000 Devices
AN 49
Implementing CRCCs in Altera Devices
AN 51
Using Programmable Logic for Gate Array Designs
AN 71
Guidelines for Handling J-Lead, QFP & BGA Devices
AN 73
Implementing FIR Filters in FLEX Devices
AN 74
Evaluating Power for Altera Devices
AN 75
High-Speed Board Designs
AN 76
Understanding FLEX 8000 Timing
AN 77
Understanding MAX 9000 Timing
AN 78
Understanding MAX 5000 & Classic Timing
AN 80
Selecting Sockets for Altera Devices
AN 81
Reflow Soldering Guidelines for Surface-Mount Devices
AN 83
Binary Numbering Systems
AN 84
Implementing fft with On-Chip RAM in FLEX 10K Devices
AN 85
In-System Programming Times for MAX Devices
AN 86
Implementing the pci_a Master/Target in FLEX 10K Devices
AN 88
Using the Jam Language for ISP & ICR via an Embedded Processor
AN 90
SameFrame Pin-Out Designs for FineLine BGA Packages
AN 91
Understanding FLEX 10K Timing
AN 92
Understanding FLEX 6000 Timing
AN 94
Understanding MAX 7000 Timing
AN 95
In-System Programmability in MAX Devices
AN 98
Comparing Performance of Common Megafunctions
AN 99
Comparing Performance of Dual-Port Memory Functions
AN 100 In-System Programmability Guidelines
AN 101 Improving Performance in FLEX 10K Devices with the Synplify Software
AN 102 Improving Performance in FLEX 10K Devices with LeonardoSpectrum Software
AN 106 Designing with 2.5-V Devices
AN 107 Using Altera Devices in Multiple Voltage Systems
AN 109 Using the HP 3070 Tester for In-System Programming
Altera Corporation
3
Documents by Type
AN 110 Gate Counting Methodology for APEX 20K Devices
AN 111 Embedded Programming using the 8051 & Jam Byte-Code
AN 112 Integrating Product-Term Logic in APEX 20K Devices
AN 113 Plastic Package Reliability & Testing
AN 114 Designing with FineLine BGA Packages
AN 115 Using the ClockLock & ClockBoost Features in APEX Devices
AN 116 Configuring SRAM-Based LUT Devices
AN 117 Using Selectable I/O Standards in APEX 20KE, APEX 20KC & MAX 7000B Devices
AN 119 Implementing High-Speed Search Applications with Altera CAM
AN 120 Using LVDS in APEX 20KE Devices
AN 122 Using Jam STAPL for ISP & ICR via an Embedded Processor
AN 123 Using Timing Analysis in the Quartus Software
AN 128 Implementing Voice Over Internet Protocol
AN 129 Implementing a W-CDMA System with Altera Devices & IP Functions
AN 130 CDR in Mercury Devices
AN 131 Using General-Purpose PLLs with Mercury Devices
AN 132 Implementing Multiprotocol Label Switching with Altera PLDs
AN 133 QDR SRAM Controller Reference Design in APEX II Devices
AN 134 Using Programmable I/O Standards in Mercury Devices
AN 138 LVDS Signaling Using APEX Device I/O Pins
AN 141 Excalibur SolutionsUsing the SDRAM Controller
AN 142 Excalibur SolutionsUsing the Embedded Stripe Bridges
AN 143 Excalibur SolutionsUsing the Expansion bus Interface
AN 156 Using General-Purpose PLLs with APEX II Devices
AN 157 Using CDS in APEX II Devices
AN 159 Using HSDI in Source-Synchronous Mode in Mercury Devices
AN 161 Using the LogicLock Methodology in the Quartus II Design Software
AN 162 Increasing System Bandwidth with CDS
AN 164 LeonardoSpectrum and Quartus II LogicLock Design Flow
AN 165 Synplify and Quartus II LogicLock Design Flow
AN 166 Using High-Speed I/O Standards in APEX II Devices
AN 167 Using Flexible-LVDS I/O Pins in APEX II Devices
AN 168 Getting Started with the LeonardoSpectrum Software
AN 169 Simulating the PCI MegaCore Function Behavioral Models
AN 171 FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow
4
Altera Corporation
Documents by Type
AN 173 Excalibur SolutionsDPRAM Reference Design
AN 174 Excalibur SolutionsHello_world.c
AN 175 SignalTap Analysis in the Quartus II Software version 1.1
AN 176 OpenCore Plus Hardware Evaluation
AN 177 Excalibur SolutionsUsing the Excalibur Stripe PLLs
AN 178 Estimating Nios Resource Usage & Performance in Altera Devices
AN 181 Excalibur SolutionsMulti-Master Reference Design
AN 183 ZBT SRAM Controller Reference Design for APEX II Devices
AN 184 Simultaneous Multi-Mastering with the Avalon Bus
AN 185 Thermal Management Using Heat Sinks
AN 186 Using Flexible-LVDS Circuitry in Mercury Devices
AN 187 Excalibur SolutionsBooting Excalibur Devices
AN 188 Custom Instructions for the Nios Embedded Processor
AN 189 Simulating Nios Embedded Processor Designs
AN 191 Excalibur Solutions--Using the Embedded Stripe Interrupt Controller
AN 192 Excalibur SolutionsEmbedded Stripe Performance Designs
AN 193 Design Guidelines for Using DSP Blocks in the Synplify Software
AN 194 Design Guidelines for Using DSP Blocks in the LeonardoSpectrum Software
AN 195 Scripting with Tcl in the Quartus II Software
AN 196 Excalibur Software Debugging Solutions
AN 198 Timing Closure with the Quartus II Software
AN 200 Using PLLs in Stratix Devices
AN 201 Using Selectable I/O Standards in Stratix Devices
AN 202 Using High-Speed Differential I/O Interfaces in Stratix Devices
AN 203 Using TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
AN 204 Using ModelSim-Altera in a Quartus II Design Flow
AN 205 Understanding Altera Software Licensing
AN 206 Transitioning APEX Designs to Stratix Devices
AN 207 TriMatrix Memory Selection Using the Quartus II Software
AN 208 Configuring Stratix & Stratix GX Devices
AN 209 Using Terminator Technology in Stratix & Stratix GX Devices
AN 210 Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs
AN 211 QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices
AN 212 Implementing Double Data Rate I/O Signaling in Stratix & Stratix GX Devices
AN 214 Using the DSP Blocks in Stratix & Stratix GX Devices
Altera Corporation
5
Documents by Type
AN 215 Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices
AN 217 Using Remote System Configuration with Stratix & Stratix GX Devices
AN 218 Using Altera Enhanced Configuration Devices
AN 219 Implementing SFI-4 in Stratix Devices
AN 220 Implementing 10-Gigabit Ethernet Using Stratix Devices
AN 224 High-Speed Board Layout Guidelines
AN 225 LeonardoSpectrum & Quartus II Design Methodology
AN 226 Synplify & Quartus II Design Methodology
AN 229 Advanced Troubleshooting for Altera Software Licensing
AN 236 Using Source-Synchronous Signaling with DPA in Stratix GX Devices
AN 237 Using High-Speed Transceiver Blocks in Stratix GX Devices
AN 238 Quartus II Verilog HDL & VHDL Integrated Synthesis
AN 239 Using VCS with the Quartus II Software
AN 244 Using Run-From-Flash Mode with the Excalibur Bootloader
AN 246 Using Soft Multipliers with Stratix & Stratix GX Devices
AN 247 Stratix GX to Mercury Interoperability
AN 249 Implementing 10 Gigabit Ethernet XAUI in Stratix GX Devices
AN 250 Configuring Cyclone FPGAs
AN 251 Using PLLs in Cyclone Devices
AN 252 On-Chip Memory Implementations Using Cyclone Memory Blocks
AN 253 Using Selectable I/O Standards in Cyclone Devices
AN 254 Implementing LVDS in Cyclone Devices
AN 255 Guidelines to Migrating Spartan Designs to Cyclone Designs
AN 256 Implementing Double Data Rate I/O Signaling in Cyclone Devices
AN 258 Using Cyclone Devices in Multiple-Voltage Systems
AN 276 Generating Deliverables for HardCopy Devices
AN 280 Design Verification Using the SignalTap II Embedded Logic Analyzer
AN 282 Implementing PLL Reconfiguration in Stratix & Stratix GX Devices
AN 283 Simulating Altera Devices with IBIS Models
AN 284 Implementing Interrupt Service Routines in Nios Systems
AN 285 Excalibur Web Server Demonstration
AN 286 Implementing LED Drivers in MAX Devices
AN 287 Using Excalibur DMA Controllers for Video Imaging and Design Files
AN 293 Using MAX 7000B Devices to Replace I/O Drivers
AN 294 Crosspoint Switch Matrices in MAX 3000A Devices
6
Altera Corporation
Documents by Type
AN 295 Gold Code Generator Reference Design
AN 296 Using Verplex Conformal LEC for Formal Verification of Design Functionality
AN 298 Reconfiguring Excalibur Devices Under Processor Control
AN 299 System Development Tools for Excalibur Devices
Brochures
ACEX Device Brochure
APEX Device Brochure
APEX II Device Brochure
Automotive Solutions Brochure
Cyclone Device Brochure
Excalibur Brochure
HardCopy Brochure
MAX Family Brochure
Mercury Device Brochure
Stratix Device Brochure
Stratix GX Device Brochure
Customer Applications
Bailey Controls Uses Megafunctions to Solve the PCI Challenge Customer Application
Catalogs
LPM Quick Reference Guide
Errata Sheets
Excalibur EPXA1 Devices Errata Sheet
Excalibur EPXA4 Devices Errata Sheet
Excalibur EPXA10 Devices Errata Sheet
EPXA10 Development Kit Revision 2.1 Errata Sheet
Functional Specifications
FS 2
fp_add_sub Floating-Point Adder/Subtractor
FS 4
fp_mult Floating-Point Multiplier
FS 5
round Data Word Rounder
Altera Corporation
7
Documents by Type
FS 6
saturate Data Word Saturator
FS 8
Midbus Interface
FS 9
AIRbus Interface
FS 10
pci_mt64 MegaCore Function Reference Design
FS 12
pci_mt32 MegaCore Function Reference Design
FS 13
Atlantic Interface
General Information
About this CD-ROM
How to Contact Altera
Legal Notice
Ordering Information
PLL & Timing Glossary
Product Information Bulletins
PIB 21
Implementing Logic with the Embedded Array in FLEX 10K Devices
PIB 22
Design Tools for 100,000 Gate Programmable Logic Devices
PIB 23
Digital Signal Processing in FLEX Devices
Selector Guides
Component Selector Guide
CPLD Package & I/O Matrix Selector Guide
Design Software & Development Kit Selector Guide
IP Selector Guide
Technical Briefs
TB 3
FLEX Devices as Alternatives to ASSPs & ASICs
TB 4
Using FLEX Devices as DSP Coprocessors
TB 5
Implementing Multipliers in FLEX 10K EABs
TB 8
Implementing Multirate Filters in FLEX Devices
TB 15
Implementing a 100,000-Gate Gate Array Design in an EPF10K100 Device
TB 26
FLEX 10K & pci_a: The Complete PCI Solution
TB 29
Internal Tri-State Emulation
TB 31
The Advantages of FLEX 10K Devices Versus Lucent ORCA Devices
8
Altera Corporation
Documents by Type
TB 33
Evaluating MAX 7000S Device Utilization & Fitting
TB 34
MAX 7000S Power Consumption
TB 38
FLEX 10KA-1 Devices: The Fastest High-Density Devices Available
TB 41
Power Measurements: FLEX 10KA vs. XC4000 Devices
TB 58
In-Circuit Test Support with MAX 7000 Devices
TB 62
MAX 7000AE Performance Comparison
TB 63
Programming Time Comparison: MAX 7000AE vs. XC9500XL Devices
TB 65
Design Fitting: MAX 7000AE vs. ispLSI 2000VE Devices
TB 73
Archiving Projects with the Quartus II Development Tool
TB 74
Timing Driven Compilation in the Quartus II Development Tool
TB 75
MAX 7000B Devices: The Industry’s Only Product-Term Device to Support 1.8-V Interfaces
TB 77
Cross-Probing Between Synplicity & Quartus II Development Tools
TB 78
APEX II Clock-Data Synchronization (CDS) Competitive Advantage
TB 80
Multiple-Speed-Grade Timing Analysis for the Quartus II Software Version 1.1 & Higher
TB 81
Quartus II Software Advantages for MAX+PLUS II Software Users
TB 82
SignalProbe Compilation Enables Fast System Debugging with the Quartus II Software
TB 84
Differences in Logic Utilization between Quartus II & Synplify Report Files
User Guides & Software Manuals
10/100 Ethernet MAC MegaCore Function User Guide
8B10B Encoder/Decoder MegaCore Function User Guide
altpll Megafunction User Guide
APEX DSP Development Kit Getting Started User Guide
APEX PCI Development Kit Getting Started User Guide
ARM922T Technical Reference Manual
ARM9TDMI Technical Reference Manual
ARM Architecture Reference Manual
ARM-Based Embedded Processor PLDs Hardware Reference Manual
ARM-Based Hardware Design Tutorial
ATM Cell Processor 155 Mbps MegaCore Function User Guide
Avalon Bus Specification Reference Manual
Color Space Converter MegaCore Function User Guide
Common Switch Interface MegaCore Function (CSIX-L1) User Guide
Constellation Mapper/Demapper user guide
Altera Corporation
9
Documents by Type
Correlator MegaCore Function User Guide
DDR SDRAM Controller MegaCore Function User Guide
DSP Builder User Guide
Embedded Trace Macrocell (ETM9) Technical Reference Manual
EPXA1 Development Board Hardware Reference Manual
EPXA1 Development Kit Getting Started User Guide
EPXA10 Development Board Hardware Reference Manual
EPXA10 Development Kit Getting Started User Guide
EPXA10 DDR Development Kit Getting Started User Guide
Excalibur Bus Functional Model User Guide
Excalibur Stripe Simulator User Guide
GNUPro Toolkit User’s Guide for ARM and ARM/Thumb Development
Nios Development Kit, Stratix Edition Getting Started User Guide
Nios Embedded Processor 16-Bit Programmer’s Reference Manual
Nios Embedded Processor 32-Bit Programmer’s Reference Manual
Nios Embedded Processor Getting Started User Guide
Nios Embedded Processor Peripherals Reference Manual
Nios Embedded Processor Programmer’s Reference Manual
Nios Embedded Processor Software Development Reference Manual
Nios Ethernet Development Kit User Guide
PCI32 Nios Target MegaCore Function User Guide
PCI MegaCore Function User Guide
PCI Testbench User Guide
Plugs Ehternet Library Reference Manual
POS-PHY Level 4 MegaCore Function (POSPHY4) User Guide
PPP Packet Processor 622 Mbps MegaCore Function User Guide
PPP Packet Processor 155 Mbps MegaCore Function User Guide
Quartus II Installation & Licensing Manual for PCs
Quartus II Installation & Licensing Manual for UNIX & Linux Workstations
Reed-Solomon MegaCore Function User Guide
Simulating the a6402 Model with the Visual IP Software User Guide
Simulating the a8237 Model with the Visual IP Software User Guide
Simulating the a8251 Model with the Visual IP Software User Guide
Simulating the a8259 Model with the Visual IP Software User Guide
SONET STS-1 Framer MegaCore Function User Guide
10
Altera Corporation
Documents by Type
SONET/SDH STS-12c/STM-4 Framer MegaCore Function (STS12CFRM) User Guide
Symbol Interleaver/De-Interleaver MegaCore Function User Guide
T3 Framer MegaCore Function User Guide
Turbo Encoder/Decoder MegaCore Function User Guide
UTOPIA Level 2 Master MegaCore Function User Guide
UTOPIA Level 2 Slave MegaCore Function User Guide
Viterbi MegaCore Function User Guide
White Papers
64-Bit Options for the PCI/MT64 & PCI/T64 MegaCore Functions White Paper
An Analytical Review of FPGA Logic Efficiency in Stratix, Virtex-II & Virtex-II Pro Devices White
Paper
Arctan Function White Paper
Excalibur Embedded Processor PLD Stripe Power Consumption White Paper
Building Blocks for Rapid Communication System Development White Paper
Configuring PLDs with FLASH Memory White Paper
Co-Simulation of Embedded Systems Implemented in FPGAs White Paper
CORDIC Functions CDPP & CDPS White Paper
DES Cores White Paper
DSSS Modem White Paper
Filtering Lab White Paper
FPGAs Provide Reconfigurable DSP Solutions White Paper
Hadamard Transform Processor White Paper
High-Speed Rijndael Encryption/Decryption Processor White Paper
Implementing IEEE Std. 802.16 Compliant FEC Decoder White Paper
Implementing OFDM Using Altera Intellectual Property White Paper
LogicLock Methodology White Paper
Low-Speed Rijndael Encryption/Decryption Processors White Paper
MD5A Hash Function White Paper
OpenCore Plus Hardware Evaluation with the APEX DSP Development Kit White Paper
OpenCore Plus Hardware Evaluation with the Excalibur Solutions White Paper
Reed-Solomon Lab White Paper
SHA-1 Hash Function White Paper
Simulating Visual IP Models with the ModelSim Simulator for PCs White Paper
Altera Corporation
11
Documents by Type
Simulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim (UNIX) Simulators
White Paper
Stratix GX in Storage Applications White Paper
Stratix GX Overview White Paper
The Evolution of High-Speed Transceiver Technology White Paper
The Need for Dynamic Phase Alignment in High-Speed FPGAs White Paper
The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices White Paper
The Truth About Die Size: Comparing Stratix & Virtex-II Pro FPGAs
Timing Analysis in HardCopy Devices White Paper
Tips for 66-MHz PCI Designs
Traffic Management in Stratix GX Devices White Paper
u-Law Companders & A-Law Companders White Paper
Using APEX II Differential I/O Standards in the Quartus II Software White Paper
Using APEX 20K & APEX 20KE PLLs in the Quartus Software White Paper
Using Parity to Detect Memory Errors White Paper
Using PLDs for High-Performance DSP Applications White Paper
Using SignalTap II in the Quartus II Software
Using Stratix GX in HDTV Video Production Applications White Paper
Using Stratix GX in Switch Fabric Systems White Paper
12
Altera Corporation