CS 3220
Initialization, Clocking, and PLLs
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Let’s pretend our board is a wristwatch
Has display and two buttons (we’ll use KEY[0] and KEY[1])
Has three modes – clock display, clock set, and stopwatch
Clock display mode
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Display time on the HEX display in the HH:MM format
Show seconds in binary on LEDG
Time starts off at 00:00:00, hours shown in 24-hour format
Push KEY[0] to switch to stopwatch mode
Hold KEY[1] for 1s to enter clock-set mode (if released in less than 1s, ignore the key press)
Clock-set mode
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Display same as in clock display mode,
but HEX and LEDG display blinking (off for 0.5s, then show time for 0.5s)
When KEY[1] pushed and released in less than 1s,
increase time by 1 minute (and reset seconds to zero)
When KEY[1] is held for more than 1s,
increase time by 1 hour for each second that KEY[1] is held pressed
Push KEY[0] to go to clock display mode
CS 4290/6290 – Fall 2009 – Prof. Milos Prvulovic
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• Stopwatch mode
– Show stopwatch time in the MM:SS format on HEX display,
LEDG shows hundredths of a second in binary
– Initially stopwatch is in the “initial” state (shows 00:00.00)
– When KEY[1] is pushed while in the initial state, start stopwatch
– When KEY[1] is pushed while stopwatch running,
stop stopwatch (freeze the stopwatch time)
– When KEY[1] is pushed while stopwatch is stopped,
reset stopwatch to 00:00.00 and go back to “initial state
– When KEY[0] is pushed, switch to clock display mode
• Changing the mode just changes what is shown and what keys do!
– Stopwatch keeps running in all modes
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If stopwatch running when we leave stopwatch mode,
keep counting until we come back to stopwatch mode and push KEY[1] to stop
If stopwatch stopped when we leave stopwatch mode,
remember stopwatch time and re-display when we are back to this mode
– Clock keeps correct time in all modes!
CS 4290/6290 – Fall 2009 – Prof. Milos Prvulovic
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• Implement the “Watch” in Verilog
and test it on your DE1 board
– Use the provided .qar file as a starting point
– Submit your Project1.qar file in T-Square
– What’s a .qar file? We’ll see in one week!
• Submit a brief report (1-2 pages)
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Who did what?
Explain how is it working (one paragraph)
If something not entirely working, explain why
Discuss cost (how many PEs, can it be fewer PEs, …)
CS 4290/6290 – Fall 2009 – Prof. Milos Prvulovic
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module Lectures(LEDG, KEY);
output [0:0] LEDG;
input [3:0] KEY;
wire flip = ! KEY[3];
reg state;
always @(posedge flip)
state <= !state;
assign LEDG[0]=state;
endmodule
• Is LEDG[0] initially on or off?
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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module Lectures(LEDG, KEY);
output [0:0] LEDG;
input [3:0] KEY;
wire flip = ! KEY[3];
The initial value of the “state”
reg state=0;
flip-flop should be zero
always @(posedge flip)
state <= !state;
assign LEDG[0]=state;
endmodule
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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module Lectures(LEDG, KEY);
output [0:0] LEDG;
input [3:0] KEY;
wire flip = ! KEY[3];
reg state;
Same as previous slide, but allows for
initial begin
more complex initialization
state=0;
Usually you put the “initial” statement
end
where the “always” block for that FF is
always @(posedge flip)
state <= !state;
assign LEDG[0]=state;
endmodule
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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• Signals can briefly have wrong values
– Due to logic delays and how they play together
• Example: 4-bit adder
– Inputs were 0000 and 0000, output is 0000
– Inputs change to 0001 and 1111, output stays 0000
– Actually, output changes briefly, then becomes 0000
• Why?
– Let’s just look at the MSB part of the adder
– Takes two inputs and carry, produces output bit
– Problem: takes time for carry to arrive,
meanwhile MSB output is 1
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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reg [3:0] cntr1,cntr2;
initial begin
cntr1 = 4'h0;
cntr2 = 4'h0;
end
always @(posedge mykey[3]) begin
cntr1 <= cntr1+4'h1;
cntr2 <= cntr2-4'h1;
end
Two counters that
start at 0 and
count in opposite
directions
Remember: This
concatenates signals
from most to least
significant bits:
LEDG[7] is 0
LEDG[6] is sumnz
LEDG[5:2] is sum
LEDG[1:0] is nzCnt
wire [3:0] sum = cntr1 + cntr2; // Should always be 0000
wire sumnz = (sum != 0);
// Should always be 0
reg [1:0] nzCnt;
initial nzCnt = 0;
always @(posedge sumnz) nzCnt <= nzCnt + 2'b1;
Counts how many
times sumnz
became 1
assign LEDG = {1'b0,sumnz,sum,nzCnt}; // Display these values on LEDG
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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• Glitches and delays are very hard to deal with
• People came up with synchronous circuits
– There is a clock, all FFs trigger on clock edge
– All signals only matter at the clock edge
– Glitches and delays don’t matter, as long as
new value stabilizes before the next clock edge
– The clock signal had better not have any glitches!
• Alternative: asynchronous circuits – no clock
– Either design a glitch-free circuit, or
– Generates a glitch-free “ready” signal when outputs are
ready, use that to trigger next FF
– Not easy to get the timing of the “ready” signal right
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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• We will make synchronous (clocked) designs
– All FFs triggered by the same clock signal
– No need to worry about glitches
• What should be the clock frequency?
– Clock Cycle Time must be long enough to
accommodate delays along all paths in our design
– Quartus compiler automatically computes these delays
– So if our clock is too fast we get a Critical Warning
• Do not overclock designs you submit for Projects!
– Will lose points for doing that!
– Design may not work on other
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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Clock cycle time computed from clock frequency
Delays on all paths computed from your design
Slack – time left over after all delays
Timing requirement => no negative slack
Project designs must meet timing requirements
– Will lose points for submitting an overclocked design
– Design may work when you test it!
– But if it does not meet timing requirements,
it is not guaranteed to work at different temperatures
or on other boards
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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• Using timing analysis results!
• Compile design, look at Compilation Report
– Under “TimeQuest Timing Analyzer”,
Click on “Slow Model”, then “Fmax Summary”
– It tells you the max frequency for your design
• Fmax higher than your PLL’s frequency
– Increase the PLL frequency (faster processor)
• Fmax lower than your PLL’s frequency?
– There will be a critical warning
– Don’t submit projects that have this warning!
– Design will be graded as incorrect! Even if it works!
CS 3220 Spring 2011 - Prof. Milos Prvulovic
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• The board has a 50MHz clock (CLOCK_50)
– There are two others, at 24MHz and a 27MHz
• Will likely need a different clock frequency?
• Clock divider can get us some lower frequencies
– E.g. what if we flip a FF every cycle at 50MHz?
– We get a 25MHz clock signal!
• But what if we want 40MHz or 85MHz?
• Answer: PLL (Phase-Locked Loop)
CS 3220 Spring 2011 - Prof. Milos Prvulovic
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• Phase-Locked Loop
– Input: a clock signal at some frequency (e.g. 50MHz)
– PLL can multiply frequency then divide it (50MHz*X/Y)
• Cheap PLL: X and Y are fixed, can get some particular frequency
• Fancy PLL: X and Y can be programmed
– Lucky us – our board has a really fancy PLL 
• Using the 50MHz clock as input, we can get a frequency
that is just a bit lower to what we want
• Why not just a bit higher than what we want?
– Can also control the duty cycle and phase shift
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Duty cycle: What part of the cycle is clock HIGH (default is 50%)
Phase shift: Clock edge can be delayed relative to another clock
Don’t mess with these settings
If you need to change them, probably you are doing something wrong
CS 3220 Spring 2011 - Prof. Milos Prvulovic
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• PLLs is a specialized circuit, can’t synthesize
a really good one using logic gates and FFs
• But our FPGA chip includes 4 such circuits
– We just need to get Quartus to use one!
– Use a Verilog module that maps to a PLL,
then connect it properly
• Use Quartus MegaWizard to generate PLL code
– Tools -> Mega Wizard Plug-In Manager
– Select “Create a new custom megafunction variation”
– In the dialog, select Verilog, a file name (e.g. PLL.v) and
select Installed Plug-Ins -> I/O -> ALTPLL
CS 3220 Spring 2011 - Prof. Milos Prvulovic
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• Now we get to configure the PLL
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Leave speed grade alone (our chip is speed grade 7)
Set input frequency to 50MHz (we will use CLOCK_50)
Leave PLL type and operation mode alone
On the next page, disable “areset” signal option,
leave the option for the “locked” signal enabled,
and enter 5000 in the “Hold locked input low…” box
– Don’t create any additonal clock inputs
– For output clocks, we will only use c0
– Enter output clock frequency
• You give it a frequency, “Actual settings” displays what it can do
• Leave phase shift at 0 degrees and duty cycle at 50% for now
– Later on, enable creation of the “Instantiation Template File” and
click “Finish”
CS 3220 Spring 2011 - Prof. Milos Prvulovic
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• Need to create a PLL instance and wire it up
– Right-click in your Verilog code
– Select “Insert Template”
– In the dialog, go to “Megafunctions -> Instances”,
find the PLL and select it, then click “Insert”
– Now change the paramaters to match our processor
• E.g. we want “.inclk0(CLOCK_50)”
• Connect .c0 clock output to what you use as a clock (e.g. “.c0(clk)”)
• Now we have a clock signal for the FFs in our design
– Remember – synchronous design
– All FFs clocked with the same clock!
– Don’t use CLOCK_50 for some FFs and the PLL output for others!
• Hmmm… what is this “locked” signal that PLL is producing?
CS 3220 Spring 2011 - Prof. Milos Prvulovic
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• PLL takes time to achieve requested frequency
– While it is “locking in”, clock frequency is unstable
• Some clock cycles too long (which is OK)
• But some are too short (not good, remember timing requirements)
– Our design should wait until the clock is safe to use!
always @(posedge clk)
if(lock)
state <= …;
CS 3220 Spring 2011 - Prof. Milos Prvulovic
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• Need to create a PLL instance and wire it up
– Right-click in your Verilog code
– Select “Insert Template”
– In the dialog, go to “Megafunctions -> Instances”,
find the PLL and select it, then click “Insert”
– Now change the paramaters to match our processor
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E.g. we want “.inclk0(CLOCK_50)”
Connect .c0 clock output to what you use as a clock (e.g. “.c0(clk)”)
• What is the “locked” signal?
– The PLL takes time to achieve requested frequency
– While it is “locking in”, clock frequency is unstable
– Our CPU should wait until the clock is safe to use
– How? Don’t let any of the FFs latch new values until locked!
always @(posedge clk)
if(lock)
state <= new_state;
CS 3220 Spring 2011 - Prof. Milos Prvulovic
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• Initialization using “initial” is fine for our designs
– We program our design into the board
– The programming sets all FFs to initial values
• But a “real” design must power-up correctly
– FFs start at random values, logic must initialize them
– Typically a “reset” signal of some sort
• “Reset” is 1 for a few cycles after power-on, then becomes 0
• Can have a second way of setting reset to 1, e.g. a hard-reset button
• Can use the “locked” signal for our reset (assign reset=!locked)
CS 3220 Spring 2011 - Prof. Milos Prvulovic
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wire clk,lock;
Pll myPll(.inclk0(CLOCK_50),.c0(clk),
.locked(lock));
…
always @(posedge clk or negedge lock)
if(!lock) begin
some_var<=some_var_init_val;
end else begin
your normal code, e.g.
some_var <=…;
end
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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CS 3220 Fall 2011 - Prof. Milos Prvulovic
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• No, just the ones that matter
– Some FFs need no initialization
• Can leave those uninitialized and/or assign w/o checking PLL lock
• But easier to just init and lock-check everything
– If something needed initialization and/or lock-check but you
didn’t do it, the resulting bug is very hard to find
– Heisenbug – sometimes it manifests, sometimes not
– Whether a Heisenbug-infested design works or not depends on:
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Value that FF starts with
How many cycles the PLL needs to lock
Manufacturing variations (exact timing of gates on your board)
Temperature (changes speed of gates)
And many other things
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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always @(posedge clk or negedge lock)
if(!lock) begin
some_var<=some_var_init_val;
end else begin
your normal code, e.g.
some_var <=…;
end
• Same behavior… but…
– This puts initialization logic on every path!
– With “or negedge lock”, uses SET/CLR inputs on FFs
CS 3220 Fall 2011 - Prof. Milos Prvulovic
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CS 3220 Fall 2011 - Prof. Milos Prvulovic
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