The future of nano-computing
George Bourianoff
Intel Corporation
Presented to
International Engineering Consortium and
Electrical and Computer Engineering Department
Heads
Jan. 27, 2003
San Jose, Ca
2/5/2003
Intel Corp. George Bourianoff
1
Future of Nanocomputing
Scalable new
technology
criteria
Scalable new
technology
Silicon highway
criteria
limits
characteristics
origins
2/5/2003
taxonomy
elements
Intel Corp. George Bourianoff
2
Key messages
• CMOS scaling will continue for next 12 –15
years
• Alternative new technologies will emerge
and begin to be integrated on CMOS by
2015
• Nanoscience research is needed to facilitate
radical new scalable technologies beyond
2020
2/5/2003
Intel Corp. George Bourianoff
3
The future of nanocomputing
• Introduction
• Scaled CMOS
• Nano-computing, nano-technology and
nano-science
• Radical new technologies
• Challenges
• Conclusions
2/5/2003
Intel Corp. George Bourianoff
4
The foundations of microelectronics
Government funded
research in solid state
physics in 1930’s and 40’s
laid the foundation
Central Breakthroughs:
•Band structure concept
•Minute amounts of impurities
control properties
•Advances in purification and
high quality crystal growth of Si
and Ge
2/5/2003
Beginning about 1946, we
began to utilize this
knowledge base
Most basic semiconductor
devices were demonstrated
within 12 years
Bipolar transistor
1948
Field effect transistor
1953
LED
1955
Tunnel diode
1957
IC
1959
Laser
1960
Intel Corp. George Bourianoff
5
The beauty of silicon
For four decades, the semiconductor
industry has steadily reduced the
unit cost of IC components by
1. Scaling device
dimensions
downward
2. Scaling wafer
diameter
upward
2/5/2003
1990
1995
2000
DRAMs
4 MB
64 MB
1 GB
Feature size
0.8 µm
0.35 µm
0.15 µm
6”
8”
12”
Wafer diameter
Cost per
Megabit
$6.50
Intel Corp. George Bourianoff
$3.14
$0.10
6
Brick Walls on the ITRS
YEAR
TECHNOLOGY NODE
On-chip local frequency (MHz)
Number of metal levels - Logic
Number of optional levels
2
o
Jmax (A/cm ) - wire (at 105 C)
Local wiring pitch - DRAM non-contacted (nm)
Local wiring pitch - Logic (nm)
Local wiring AR-Logic (Cu)
Cu local dishing (nm)
Intermediate wiring pitch - Logic (nm)
Intermediate wiring h/w AR - Logic (Cu DD via/lin)
Cu intermediate wiring dishing 15 um wide wire (nm)
Dielectric erosion, intermediate wiring
50% density (nm)
Global wiring pitch - Logic (nm)
Global wiring h/w AR - Logic - Cu DD via/line (nm)
Cu global wiring dishing, 15 um wide wire (nm)
Contact aspect ratio - DRAM, stacked cap
Conductor effective resistivity (uohm -cm)
Barrier/cladding thickness (nm)
Interlevel metal insulator effective
dielectric constant (k) - Logic
2/5/2003
Solutions Exist
Solutions being pursued
No known solutions
1999
2002
2005
180 nm 130 nm 100 nm
1.25
2.10
3.50
6-7
7-8
8-9
0
2
2
5.8 E5 9.6 E5 1.4 E6
360
260
200
500
325
230
1.4
1.5
1.7
18
14
11
560
405
285
2.0/2.1 2.2/2.1 2.4/2.2
64
51
41
64
900
2.2/2.4
116
9.3
2.2
17
51
650
2.5/2.7
95
11.4
2.2
13
41
460
2.7/2.8
76
13
2.2
10
2008
70 nm
6.00
9
3
2.1 E6
140
165
1.9
9
210
2.5/2.3
30
2011
2014
50 nm 35 nm
10.00
13.50
9-10
10
4
4
3.7 E6 4.6 E6
100
70
120
85
2.1 2.2 - 2.3
7
5
145
110
2.7/2.4 2.9/2.5
22
17
0
0
0
330
240
170
2.8/2.9 2.9/3.0 3.0/3.1
55
38
20
14.1
16.1
23.1
1.8
< 1.8
< 1.8
0
0
0
4.0 - 3.5 3.5 - 2.7 2.2 - 1.6
Intel Corp. George Bourianoff
1.4
<1.5
<1.5
2008
70 nm
6.00
9
3
2.1 E6
140
165
1.9
9
210
2.5/2.3
30
2011
2014
50 nm 35 nm
10.00
13.50
9-10
10
4
4
3.7 E6 4.6 E6
100
70
120
85
2.1 2.2 - 2.3
7
5
145
110
2.7/2.4 2.9/2.5
22
17
0
0
0
330
240
170
2.8/2.9 2.9/3.0 3.0/3.1
55
38
20
14.1
16.1
23.1
1.8
< 1.8
< 1.8
0
0
0
1.4
<1.5
<1.5
7
Silicon
Nanotechnology
is
Here!
10000
10
Nominal feature size
1000
1
Micron
Gate Width
130nm
90nm
100
0.1
Nanotechnology
70nm
50nm
10
0.01
1970
1970
2/5/2003
Nanometer
1980
1980
1990
1990
2000
2000
Intel Corp. George Bourianoff
2010
2010
2020
2020
8
The ingredients of scaling
Material Evolution in MOS
New materials
0 ’s
20 0
Al-Cu
s
90 ’
s
80 ’
s
60 ’
Al-Cu
W
Al-Cu
W
Cu
s
70 ’
Al-Cu
W
Low K
ELK
Al-Si
Ti/TiN
Ti/TiN
Ti/TiN
Ti/TiN
TiSi2/Poly
CSi2/Poly
Al
Poly
WSi2/Poly
TiSi2/Poly
SiO2
SiO2
SiO2
SiO2
SiO2
SiO2/SiN
Silicon
Silicon
Silicon
Silicon
Silicon
Silicon
Improved processing
New geometries
Scaling Will continue as long as
(δ cost) /(δ performance) < alternate technologies
2/5/2003
Intel Corp. George Bourianoff
9
Demo: 2000
70nm
70nm transistor
for 0.13µm process
2001 production
Influenza virus
30nm
Drain Current (µA/µm)
Transistor Scaling
500
400
15nm NMOS
Vg = 0.8V
0.7V
300
0.6V
200
0.5V
100
0.4V
0.3V
0
0
0.2 0.4 0.6 0.8
Drain Voltage (V)
30nm transistor
Prototype
Source: CDC
15nm
100nm
15nm transistor
prototype
2/5/2003
Source:
Intel (IEDM, Dec 2001)
Intel Corp. George Bourianoff
10
New Materials
Changes
Made
Future
Options
Gate
High-k
gate
dielectric
Silicide
added
Channel
Strained
silicon
Transistor
New
transistor
structure
Source: Intel
The problem: High Ioff current
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Intel Corp. George Bourianoff
11
New Geometries
Gate
Gate
Drain
Drain
Source
Source
1.2
Silicon
Source: Intel
(ISSDM, Sep 2002)
Id (mA/µm)
1.0
0.8
0.6
0.4
0.2
0
2/5/2003
0.3
0.6
0.9
1.2
Vd (V)
Intel Corp.
George Bourianoff
Source: Intel
12
Improved processing
EUV Lithography
Prototype Exposure Tool
50nm Lines Printed
with EUV Lithography
EUV lithography in commercialization phase
Cost effectiveness is key challenge
2/5/2003
Intel Corp. George Bourianoff
Source: Sandia
13
The limits of logic scaling
• For an arbitrary switching device made of
of a single electron in a dual quantum well
– Operating at room temperature
• It can be shown a power dissipation limit of
100 W/cm**2
• Will limit the operational frequency to ~100
GHz at length scales ~ 4 nm
2/5/2003
Intel Corp. George Bourianoff
14
CMOS device circa 2016
• Cost
10-11 $/gate
• Size
8 nm / device
• Speed
0.2 ps /operation
• Energy
10-18 J/operation
2/5/2003
Intel Corp. George Bourianoff
15
The future of nanocomputing
– Introduction
– Scaled CMOS
– Nano-computing, nano-technology and nano-science
•
•
•
•
A taxonomy
New devices
New architectures
Alternative state variables
– Radical new technologies
– Challenges
– Conclusions
2/5/2003
Intel Corp. George Bourianoff
16
ch
e
t
bio
A taxonomy
for
nano-computing
s
ice
v
e
d
ory
Mem
sens
Heirarchy
ors
probabilities
patterns
associative
analogue
Data
represent
ations
Digital
Electric charge
Boolean
Molecular
state
CNN
Spin
orientation
Flux quanta
Crossbar
Quantum
state
Quantum
Scaled
CMOS
CNT
FETs
Molecular
Spintronics
Quantum
State
variables
Architecture
Devices
Time
2/5/2003
Intel Corp. George Bourianoff
17
The future of nanocomputing
– Introduction
– Scaled CMOS
– Nano-computing, nano-technology and nano-science
• A taxonomy
• New devices
• New architectures
• Alternative state variables
– Radical new technologies
– Challenges
– Conclusions
2/5/2003
Intel Corp. George Bourianoff
18
2/5/2003
Intel Corp. George Bourianoff
19
CNT-FET Device Structure
E-beam Ti/Au gate
Mo S/D
8 nm
ZrO2
1.4 nm diameter single wall CNT
McEuen et. al, . Cornell Universwity
2/5/2003
Intel Corp. George Bourianoff
20
Nanowire Gating Geometries
D
Back gate
S
SiO2
G
Si
D
Top gate
G
S
D
Coaxial gate
2/5/2003
G
S
Intel Corp. George Bourianoff
C. Leiber et. al. , Harvard U21
Top-gated p-Si Nanowire
Transistors
-2.5
SiOx
D
-2.0 VGS
-2.0
G
Si
S
IDS (µA)
-1.5 V GS
-1.5
-1.0 VGS
-1.0
-0.5 VGS
0.0 VGS
-0.5
+0.5 VGS
0.0
-4
C. Leiber et. al. , Harvard U
1 µm
S
-3
1500
-2
-1
VDS (V)
0
250 mV/dec
D
10
700 nA/V
1
500
1 µm
0
2/5/2003
100
1000
Intel Corp. George Bourianoff
-2
0.1
VDS = -1 V
-1
-IDS (nA)
-I DS (nA)
G
1000
0
VGS (V)
1
2
0.01
22
Crossed Nanowire Structures: A
Powerful Strategy for Creation &
Integration of Nanodevices
ƒ Nanowires serve dual purpose: both active devices and
interconnects.
ƒ All key nanoscale metrics are defined during synthesis and
subsequent assembly.
ƒ Crossed nanowire architecture provides natural scaling and
potential for integration at highest densities.
ƒ2/5/2003
No additional complexity
(with added material).
Intel Corp. George Bourianoff
23
C. Leiber et. al. , Harvard U
Current (nA)
400
200
Current (nA)
Crossed Nanowire FETs
10
2
10
0
Vg(V):
0
1
-2
10
2
3
0 1 2 3 4 5
Gate (V)
0
D
S
-200
G
-400
-1.0
-0.5
0.0
Bias (V)
0.5
1.0
ƒ In crossed nanowire FETs (cNW-FET), all critical nanoscale metrics
are defined by synthesis and assembly:
• channel width by the active nanowire diameter (to 2 nm)
• channel length by the gate nanowire diameter (to 1-2 nm)
• gate dielectric oxide coating on the nanowires (to 1 atomic layer)
ƒ The conductance of cNW-FETs can be changed by more than 105-times
with less than 0.1 V variation in the nano-gate.
2/5/2003
Intel Corp. George Bourianoff
24
Huang, Duan, Lieber et al., Science 294, 1313 (2001)
Device Demonstrated
P-N Junction
Lieber/Harvard
2/5/2003
Intel Corp. George Bourianoff
25
Room temperature Single
Electron Transistor (SET)
•Single electron
in “island”
controls current
flow from
source to drain
•Typical sizes
of the TiOx
lines are 15-25
nm widths and
30-50 nm
lengths.
•Typical island
sizes are 30-50
nm by 35-50
nm
2/5/2003
Courtesy, NEC, IEDM 2000, PP 481
Intel Corp. George Bourianoff
26
Spin resonance transistor (SRT)
• Transistors that control
spins rather than charge
• More energy efficient than
conventional transistors
• Combines magnetic and
electrostatic fields
• May enable quantum
computing
Courtesy Eli Yablanovitch, UCLA
2/5/2003
Intel Corp. George Bourianoff
27
A Molecular Electronic Switch
(2-amino-4-ethyinylphenyl-4-ethylphenyl-5nitro-1-benzenethiolate)
Au
1000 Self Assembled
Molecules (SEM)
Current (pA)
Silicon Nitride
1
1
Au
IV Characteristics
(@T=60K)
0.00 0.50 1.00 1.50 2.00 2.50 3.00
2/5/2003
Voltage (V)
Intel Corp. George Bourianoff
Source: M.Reed & others,Yale Univ and Rice Univ
28
The future of nanocomputing
– Introduction
– Scaled CMOS
– Nano-computing, nano-technology and nano-science
•
•
•
•
A taxonomy
New devices
New architectures
Alternative state variables
– Radical new technologies
– Challenges
– Conclusions
2/5/2003
Intel Corp. George Bourianoff
29
Emerging Research Architectures
ON2
H2N
ARCHITECTURE
3-D INTEGRATION
QUANTUM
CELLULAR
AUTOMATA
DEFECT
TOLERANT
ARCHITECTURE
MOLECULAR
ARCHITECTURE
CELLULAR
NONLINEAR
NETWORKS
QUANTUM
COMPUTING
CMOS with
dissimilar
material
systems
Arrays of
quantum dots
Intelligently
assembles
nanodevices
Molecular
switches and
memories
Single electron
array
architectures
ADVANTAGES
Less
interconnect
delay,
Enables mixed
technology
solutions
High functional
density. No
interconnects
in signal path
Supports
hardware with
defect densities
>50%
Supports
memory
based
computing
Enables
utilization of
single electron
devices at
room
temperature
Spin resonance
transistors,
NMR devices,
Single flux
quantum
devices
Exponential
performance
scaling,
Enables
unbreakable
cryptography
CHALLENGES
Heat removal,
No design
tools,
Difficult test
and
measurement
Limited fan out,
Dimensional
control (low
temperature
operation),
Sensitive to
background
charge
Requires precomputing test
Limited
functionality
Subject to
background
noise,
Tight
tolerances
Extreme
application
limitation,
Extreme
technology
MATURITY
Demonstration
Demonstration
Demonstration
Concept
Demonstration
Concept
DEVICE
IMPLEMENTATION
2/5/2003
Intel Corp. George Bourianoff
30
Quantum Cellular Automata
Adder circuit with carry
executed in QCA logic
Example of asynchronous,
CNN, nearest neighbor
architecture
Courtesy of Notre Dame
2/5/2003
Intel Corp. George Bourianoff
31
Fault tolerant architecture
• All-memory architecture
• Defect tolerant
• Potentially self-repairing and
reconfigurable
2/5/2003
Intel Corp. George Bourianoff
J. Heath, R. S. Williams
et al, UCLA and HP
32
Phase logic
• Store information in the
relative phase of 2 signals
• Multi-valued logic
possible depending on
frequencies of 2 signals
• Tunneling Phase logic
devices use RTDs to
create one of the signals
Courtesy: R Keihle, University of
Minnesota
2/5/2003
Intel Corp. George Bourianoff
33
Quantum Computer
A-Gate
J-Gate
- - -
A-Gate
+++
Barrier layer
28
Si
31
P
Selected technological
implementations
•Liquid-state NMR
•Linear ion trap
e31
P
•Coupled quantum dots
•Deterministically doped
semicondustor structures
2/5/2003
Intel Corp. George Bourianoff
34
The future of nanocomputing
– Introduction
– Scaled CMOS
– Nano-computing, nano-technology and nano-science
• A taxonomy
• New devices
• New architectures
• Alternative state variables
– Radical new technologies
– Challenges
– Conclusions
2/5/2003
Intel Corp. George Bourianoff
35
Alternative state variables
• Electric charge
• Molecular state
• Spin orientation
• Electric dipole
orientation
2/5/2003
•
•
•
•
•
Photon intensity
Photon polarization
Quantum state
Phase state
Mechanical state
Intel Corp. George Bourianoff
36
The future of nanocomputing
– Introduction
– Scaled CMOS
– Nano-computing, nano-technology and nano-science
• A taxonomy
• New devices
• New architectures
• Alternative state variables
– Radical new technologies
– Challenges
– Conclusions
2/5/2003
Intel Corp. George Bourianoff
37
Economic criteria
• Economic relevance criteria
– The risk adjusted ROI for any new technology must
exceed that of silicon
• Caution
– Sufficiently advanced technologies will create their
own applications. New technologies cannot
necessarily be justified by current day applications.
2/5/2003
Intel Corp. George Bourianoff
38
Technical criteria
• CMOS compatibility
• Energy efficiency
•
•
•
•
•
•
Scalability
Performance
Architectural compatibility
Sensitivity to parametric variation
Room temperature operation
Stability and reliability
2/5/2003
Intel Corp. George Bourianoff
39
Existence proof for alternate models
The brain is the
ultimate model for its
ability to deal with
complexity
• Little understanding on its architecture & organization
• It is however
–
–
–
–
–
–
2/5/2003
Orders of magnitude more powerful than the best microprocessor
Self assembled
Parallel operation
Self repairing to a significant degree
Fault tolerant
Runs on ~ 10W
Intel Corp. George Bourianoff
40
Breakthrough scientific
investigation is needed
1952 Achievements
2002 Needs
• Bulk band structure
of solids
• geometry dependent
energetic structure of
nanostructures
• Doping
• Crystal growth
2/5/2003
• precise location of atoms
• self organization of matter in
complex structures
Intel Corp. George Bourianoff
41
The integration challenge
Scalability
Node
Controller
Memory
Scalability
Port Switch
I/O
Bridge
Memory
Scalability
Port Switch
I/O
Bridge
I/O Hub
PCIPCI-(X)
Bridge
Scalability
Node
Controller
InfiniBand*
Bridge
I/O Hub
PCIPCI-(X)
Bridge
InfiniBand*
Bridge
Intel® 82870 4-way & 88-way Server Configurations
2/5/2003
Intel Corp. George Bourianoff
42
Conclusions
• CMOS scaling will continue for next 12 –15
years
• Alternative new technologies will emerge
and begin to be integrated on CMOS by
2015
• Nanoscience research is needed to facilitate
radical new scalable technologies beyond
2020
2/5/2003
Intel Corp. George Bourianoff
43
For further information on Intel's silicon technology,
please visit the Silicon Showcase at
www.intel.com/research/silicon
2/5/2003
Intel Corp. George Bourianoff
44
Backup
2/5/2003
Intel Corp. George Bourianoff
45
For about four decades now we have exploited
(mined) our investment in basic science and we
have continuously evolved the devices based
on this understanding
2/5/2003
Intel Corp. George Bourianoff
46
Nanotechnology for
Gate Dielectrics
Gate
Transistor gate oxide thickness trend
Dimension (nm)
100
Source: Intel
10
1.2nm SiO2
SiO2
Silicon substrate
Si-O bond:
0.16nm
High K
1
1970 1980 1990 2000 2010 2020
First year in production
90nm process
1X
Capacitance
1X
Leakage
Experimental high-k
1.6X
< 0.01X
Gate
3.0nm High-k
Silicon substrate
Leakage is the limiter to SiO2 scaling
Integration is the
key challenge to High K
2/5/2003
Intel Corp. George Bourianoff
47
What new basic science is
needed?
r
s→R
• Spin manipulation, e.g.
transport, storage, detection,
creation, …
• Geometry related quantum
effects, e.g. quantum wedge,
parabolic wells, …
Source
Drain
Si
P+
2/5/2003
P+
B-
• Precise location of atoms e.g.
coherent manipulation of
entangled wavefunctions
Intel Corp. George Bourianoff
48
Transport in Si-Ge Core-Shell
Structures
-2.5
SiOx
Ge
Si
G
-0.9
-2.0
IDS (µA)
D
VGS = -1.1 V
-0.7
-1.5
-1.0
-0.5
-0.5
-0.3
S
0.0
0.0
-4
-3
-2
-1
0
VDS (V)
1000
1000
G
500 nm
100
330 mV/dec
600
1300 nA/V
400
1
200
0.1
VDS= -1 V
0
2/5/2003
10
-IDS (nA)
D
S
-IDS (nA)
800
Intel Corp. George Bourianoff
-1.0
0.0
VGS (V)
1.0
0.01
49
Coaxially-Gated Si-Ge
-2.5
SiOx
Ge
IDS (µA)
-2.0
Si
-1.5
-2 VGS
-1.0
-1 VGS
-0.5
Ge
O VGS
0.0
0.5
-1.5
-1.0
-0.5
VSD (V)
3.0
0.0
450 mV/dec. 1000
2/5/2003
100
2.0
1.5
10
1.0 1.5 µA/V
0.5
1
0.0
-2
Intel Corp. George Bourianoff
+1 VDS
-1
0.1
0
VGS (V)
1
2
50
IDS (nA)
IDS (µA)
2.5
Devices Demonstrated
Nanowire FET
Lieber/Harvard
2/5/2003
Intel Corp. George Bourianoff
51
Photonic devices
Man-made crystals
produced by etching
precisely placed holes
in silicon or III-V
material
Can produce, detect and
manipulate light more
efficiently than
naturally occurring
materials
2/5/2003
Intel Corp. George Bourianoff
52
System software design needs to
facilitate emerging technologies
Challenge
• CMOS is based on Boolean logic and binary data
representation
• Alternative technologies will require “native”
logic systems and data representations to optimize
their performance
Solution?
• Design science must provide functional
abstractions and interfaces to couple multiple,
dissimilar technologies
intoBourianoff
a single functional
2/5/2003
Intel Corp. George
system
53
Nano-computing, nanotechnology and nano-science
2/5/2003
Intel Corp. George Bourianoff
54
Changing architectural paradigms
Current
Future
•
•
Boolean logic
Binary data
representation
•
•
•
•
•
•
2D
Homogeneous
Globally interconnected
Synchronous
Von Neuman
3 terminal
2/5/2003
• Neural networks, CNN,
QCA,…
• Associative, patterned,
memory based, … data
representations
• 3D
• Non homogeneous
• Nearest neighbor
• Asynchronous
• Integrated memory/logic
• 2 terminal
Intel Corp. George Bourianoff
55