International Technology Roadmap
for Semiconductors
2008 ITRS ORTC
[7/14-16 ITRS Meetings San Francisco]
A.Allan, Rev 1 (for 7/16 Public Conference Prep)
1
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
Agenda
• Moore’s Law and More
• Technology Pacing Trends Update
– Physical and Printed GL Focus
• Summary
•
Backup
–
–
–
–
Function Size, Moore’s Law on Track
Design On-Chip Frequency
SICAS Technology, Wafer Generation Demand Update
Definitions
2
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
2008 ITRS Executive Summary Fig 5
[updated for 2007]
Moore’s Law & More
More Diversification
than Moore: Diversification
Functional
(More than Moore)
[Geometrical & Equivalent scaling]
Baseline CMOS: CPU, Memory, Logic
More
Moore:
Miniaturization
Scaling
(More
Moore)
Traditional
ORTC Models
Facilitator:
Alan Allan
[2008 –
Update Definitions]
Analog/RF
HV
Power
HV
65nm
45nm
32nm
Biochips
Interacting with people
and environment
130nm
90nm
Sensors
Actuators
Passives
Power
Passives
Facilitator:
Mart Graef
CCoo
nmtib
niun
in
g SS
Information
Processing
Digital content
System-on-chip
(SoC)
Non-digital content
System-in-package
(SiP)
ooC
Ca
annd
dSSi
Pi:P
:HiHg
22nm
.
.
.
V
hige
hr eV
raV
lu
ael S
uey
sSt
eym
s
tsem
s
Beyond CMOS
Facilitator:
Jim Hutchby
SIP “White Paper”
A&P TWG
Chair: Bill Bottoms
www.itrs.net/
papers.html
3
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
2007 ITRS “Moore’s Law and More”
Alternative Definition Graphic
Baseline
CMOS
Memory
RF
HV
Power
Passives
Sensors,
Actuators
Bio-chips,
Fluidics
“More Moore”
“More than Moore”
Computing &
Data Storage
Sense, interact,
Empower
Heterogeneous Integration
System on Chip (SOC) and System In Package (SIP)
Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC)
Work in Progress – Do Not Publish
4
ITRS 2008 Update Preparation – July, San Francisco, USA
2008 ITRS “Beyond CMOS”
Baseline Ultimately
Functionally
CMOS
Scaled CMOS Enhanced CMOS
32nm
22nm
16nm
11nm
Ferromagnetic Spin Logic
Nanowire
Electronics Logic Devices Devices
8nm
Multiple gate MOSFETs
Channel Replacement Materials
Low Dimensional Materials Channels
New State Variable
New Devices
New Data Representation
New Data Processing
Algorithms
“More Moore”
“Beyond CMOS”
Computing and Data Storage Beyond CMOS
Source: Emerging Research Device Working Group
5
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
2007 - PIDS/FEP - Simplified Transistor Roadmap
electrostatic control
[Examples of “Equivalent Scaling” from ITRS PIDS/FEP TWGs] – Update in 2009
poly
metal
SiON
high k
gate stack
bulk
planar
3D
MuGFET
MuCFET
FDSOI
PDSOI
+ high µ
materials
+ substrate
engineering
stressors
65nm
[ ITRS DRAM/MPU Timing: 2007[7.5]
45nm
32nm
22nm
2010
2013
2016 ]
Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC)
Work in Progress – Do Not Publish
6
ITRS 2008 Update Preparation – July, San Francisco, USA
2007 Definition of the Half Pitch – 2008 unchanged
[No single-product “node” designation; DRAM half-pitch still litho driver; however,
other product technology trends may be drivers on individual TWG tables]
FLASH Poly Silicon ½ Pitch
= Flash Poly Pitch/2
Poly
Pitch
8-16 Lines
Typical flash
Un-contacted Poly
DRAM ½ Pitch
= DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch
= MPU/ASIC M1 Pitch/2
Metal
Pitch
Typical DRAM/MPU/ASIC
Metal Bit Line
Source: 2005 ITRS - Exec. Summary Fig 2
Work in Progress – Do Not Publish
7
ITRS 2008 Update Preparation – July, San Francisco, USA
2008 - Unchanged
Fig 3
Production Ramp-up Model and Technology Cycle Timing
100M
200K
Production
10M
20K
1M
100K
2K
Alpha
Tool
Beta Production
Tool
Tool
10K
1K
First
Conf.
Papers
-24
-12
Source: 2005 ITRS - Exec. Summary Fig 3
0
Months
Work in Progress – Do Not Publish
200
First Two
Companies
20
Reaching
Production
2
12
Volume (Wafers/Month)
Volume (Parts/Month)
Development
24
8
ITRS 2008 Update Preparation – July, San Francisco, USA
2007 ITRS Product Technology Trends Half-Pitch, Gate-Length
[WAS]
1000.0
Before 1998
.71X/3YR
Product Half-Pitch, Gate-Length
(nm)
After 1998
.71X/2YR
DRAM M1 1/2 Pitch
MPU M1
.71X/2.5YR
100.0
MPU & DRAM M1
& Flash Poly
.71X/3YR
MPU M1 1/2 Pitch
(2.5-year cycle)
Flash Poly 1/2 Pitch
Flash Poly
.71X/2YR
10.0
MPU Gate Length Printed
Gate Length
.71X/3YR
Nanotechnology (<100nm) Era Begins -1999
1.0
1995
2000
2005
2010
2015
MPUGate Length Physical
GLpr IS =
1.6818 x GLph
2020
2025
Year of Production
2007 - 2022 ITRS Range
Work in Progress – Do Not Publish
9
ITRS 2008 Update Preparation – July, San Francisco, USA
2008 ITRS Update - Technology Trends vs Actuals and Survey
Jeff Butterbaugh/FEP
GLphys Actuals
(leading):
1000
"More Moore"
Functional
Density
Complemente
d
by "Equivalent
Scaling"
Performance/
Power Mgt
[Copper IC;
Strain Si;
Metal Gate/
Hi-K;
UTB/FDSOI;
MUG; etc.]
nanometers (1e-9)
2.5-year
Cycle
[.5^(1/5yrs)]
100
Kwok Ng/PIDS
GLphys Survey
(leading):
Printed GL =
Physical GL
After 2019
2008
Update
M1 Half Pitch(nm)
MPU (ITRS 05-07)
[also DRAM M1 in
2008 Update]
M1 Half Pitch(nm)
DRAM (ITRS 05-07)
GLprinted =
[decreasing
Etch ratio]
10
2000
2008
Update
Glph(nm) MPU (ITRS
05-07)
3-year
Cycle
[.5^(1/6yrs)]
GLphysical =
~0.71x/ 3.8yrs
Glpr(nm) MPU (ITRS
05-07)
Poly Half Pitch(nm)
Flash (ITRS 07)
[Litho Driver after
2007 ]
“32nm” 2yr
GLph delay
“45nm” 1yr 2005
GLph delay
Work in Progress - Do
Not Publish!
GLph Proposal 2008
Update
“20nm” 3yr
GLph delay
2010
2015
Year
“10nm” 5yr
GLph delay
2007/08 ITRS: 2007-2022
2020
2025
Work in Progress - Do
Not Publish!
• GLphysical 2008 Update IS: 3.8yr cycle after 2007; enabled by “Equiv. Scaling”
• FEP and PIDS have proposed shifted/interpolated tables; full model redo in ‘09
• GLprinted parallel to MPU/DRAM M1 Half-Pitch; shrinking etch ratio to GLphy 10
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
ORTC Summary – 2008 Update Status
•
Flash Model un-contacted poly half-pitch trend
–
–
–
•
DRAM Model stagger-contacted M1 half-pitch updated to the MPU 2.5-year cycle*
through 2010/45nm [affects 2007, 2008, 2009], then
–
–
•
2.5-year cycle* through 2010/45nm, then 3-year cycle* (2016/22.5; 2022/11.25).
MPU/ASIC Printed Gate Length Updated
–
–
•
Only 2007-2009 years affected in 2008 Table Update.
Unchanged 2010-2022
MPU Model M1 stagger-contact half-pitch unchanged from 2007
–
•
Unchanged 3-year cycle* beginning 2010/45nm (2016/22.5; 2022/11.25);
Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip
DRAM function size, function density, and chip size models have been updated to
latest Product 2.5-year cycle scaling rate;
–
–
•
Unchanged 2-year cycle* through 2008/45nm, then 3-year cycle* (2014/22.5; 2020/11.25); ;
Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip
PIDS Flash Survey Team to report status of survey data update and proposals in July meetings.
1.6818 Etch Ratio in 2007;
Then variable Gpr/Gphy Etch Ratio (parallel to DRAM/MPU M1 Contacted Half Pitch) ‘07-’22.
MPU/ASIC High-Performance Physical Gate Length
–
–
–
–
3.8-year cycle* beginning 2007 Performance and Power needs manage.
FEP and Litho TWGs have agreed on new annual variable GLprinted/GLphysical ratio targets
Slower On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS ORTC) - need
updated transistor and design model alignment by PIDS, FEP, and Design – 2009 Renewal.
New drivers will be Ion/Width, CV/I – possibly add to ORTC - 2009 Renewal ORTC line items.
* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]
11
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
ORTC Summary – 2008 Update Status (cont.)
•
MPU/ASIC Low Operating Power Printed Gate Length
–
•
MPU/ASIC Low Standby Power Physical Gate Length [add to ORTC 1a,b]
–
•
–
–
•
•
No Change 2007, 2008; two-year delay 2009-2011 from High Performance; one-year delay in
2012; and no delay 2013-2022.
New 2008 “Moore’s Law and More” Working Groups and Definitions Work :
–
•
TBD
“More Moore” (“Moore’s Law;” typically digital computing) Functional and Performance scaling is
enabled by both “Geometrical” and also “Equivalent” scaling technologies; Design “Equivalent
Scaling” to be added in 2008
More than Moore “Functional diversification” text will be impacted (typically non-digital
sensing, interacting) system board-level migration/miniaturization is enabled by system-in-package
and system-on-chip
“Beyond CMOS” definition will be added, focused on the Computing and Storage Logic
Switch transition and consensus options at “Ultimately Scaled CMOS”
The average of the industry product “Moore’s Law” (2x functions/chip per 2 years) rate
forecast to continue throughout the latest 2007-2022 ITRS timeframe
Total MOS Capacity (SICAS) growing at >16% CAGR (SICAS); new “<80nm” data
split out; and 300mm Capacity Demand has ramped to over 40% of Total MOS
Industry Technology Capacity Demand (SICAS) – 1Q08 published status] continues on
a on 2-year cycle* rate at the leading edge.
* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]
12
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
Backup
•
•
•
•
Function Size; Moore’s Law on track
Design Frequency (2007)
SICAS Update (1Q08 data)
Definitions
13
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
Figure 9[’07] ITRS Product Function Size
2008 Update:
2007 ITRS Product Function Size Trends - [NO CHANGE to MPU and Flash;
Small change ’07-’09 to DRAM]
Cell Size, Logic Gate(4t) Size
1.E+01
Past ÅÆ Future
1.E+00
Cell, Logic Gate Size
(um2 )
DRAM Cell Size (u2)
Logic Gate: NO
Design Area
Factor Improvement
(Only Scaling)
SRAM: gradual
Design Area
Factor Improvement
DRAM - Small
Adjustments
In 2008
1.E-01
DRAM 6f2
Pull-in to ‘06
1.E-03
MPU Gate Size
(4t)(u2)
DRAM: 6f2 is last
Design Area
Factor Improvement
1.E-02
Flash Cell Size (u2)
SLC
Flash Eqv.bit Size(u2)
2bit MLC
Flash: 4f2 Last
Design Physical Area
Factor Improvement
Flash cell area
Reduced due to
2YR cycle
Extension
1.E-04
2000
2005
MPU SRAM Cell Size
(6t)(u2)
(@ 2 MLC bits/physical cell area)
Flash Eqv.bit Size(u2)
4bit MLC - New
Flash: (MLC @ 2 bits/cell =
2f2 Equivalent Area Factor)
2010
(@ 4 MLC bits/physical cell area)
2015
Year of Production
2020
2025
Flash 4 bits/cell
1f2 Beginning 2010
14
2007 - 2022 ITRS Range
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
Figure 10 ITRS Product Functions per Chip
2007 ITRS Product Technology Trends Functions per Chip
[Unchanged for 2008]
Flash Bits/Chip (Gbits)
Multi-Level-Cell (4bit
MLC)
1.E+03
Flash MLC
4 bits/chip
Added
Flash Bits/Chip (Gbits)
Multi-Level-Cell (2bit
MLC)
Product Functions/Chip
[ Giga (10^9) - bits, transistors ]
1.E+02
Flash Bits/Chip (Gbits)
Single-Level-Cell (SLC )
1.E+01
Flash SLC
Bits/chip
for 1-year
Pull-in
DRAM Bits/Chip (Gbits)
1.E+00
MPU GTransistors/Chip
- high-performance (hp)
DRAM
Bits/chip
1-year
Delay;
1.E-01
1.E-02
1995
2000
2005
2010
2015
Moore’s Law
On
Track!
MPU GTransistors/Chip
- cost-performanc (cp)
2020
Average Industry
"Moores Law“ :
2x Functions/chip Per 2 Years
2025
Year of Production
2007 - 2022 ITRS Range
Past Å Æ Future
Work in Progress – Do Not Publish
15
ITRS 2008 Update Preparation – July, San Francisco, USA
New Design TWG
2007 ITRS Frequency
Historical Data vs 2005 ITRS
And Proposed* Trend Ave ~8% CAGR
2022
~14.3Ghz
Past Å Æ Future
Actual
History vs ITRS
On-Chip?
~ 8%
CAGR
2005/06 ITRS
2007
~4.7Ghz
New Design TWG
2007 ITRS Final “IS”
Ave 8% CAGR
~ 21%
CAGR
2007 - 2022 ITRS Range
* Source: Various, per ITRS Design TWG ca August 2007
16
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
Performance and Power Management
Enabled by “Equivalent Scaling”
D e s ig n M a x O n -C h ip C lo c k F re q u e n c y
D e sig n
M a x.
F re q .
2001
IT R S
In c lu d in g 2 0 0 5 IT R S a n d F in a l (A u g '0 7 ) 2 0 0 7 D e s ig n T W G
1 0 0 .0
2005/06
ITRS
W
A S /IS
“WAS”
"G a p " D e la ye d
b y 3 ye a rs
in 2 0 0 5 IT R S
1 .1 7 x/ye a r
(2 x/4 .5 yrs )
Gamers
“Clock-Doubling?”
D e sig n
M a x.
F re q .
2003
IT R S
(Ghz)
IS : D e sig n /A rch ite ctu re : re d u ctio n o f
m a xim u m # 0 f in ve rte r d e la ys to fla t a t
1 2 b e g in n in g 2 0 0 7
W A S : (2 0 0 1 IT R S : fla t a t 1 6 a fte r 2 0 0 6 )
1 0 .0
E xtra p o la t
io n /In te rp
o la tio n o f
2005
W AS
IT R S
P ro p o sa l
1 .2 9 x/ye a r
(2 x/2 .5 yrs)
1 .4 1 x/ye a r
(2 x/2 yrs )
New Design TWG
2007 ITRS Final “IS”
Ave 8% CAGR
P a s t < -----> F u tu re
1 .0
1995
2000
2005
2010
2015
2020
2025
F in a l M a x
O n -C h ip
L o ca l
C lo c k
F re q
(A u g '0 7 )
Year
2007 Des TWG
Actual History of
Average On-Chip
~ 21% CAGR
2007 - 2022 ITRS Range
Work in Progress – Do Not Publish
17
ITRS 2008 Update Preparation – July, San Francisco, USA
2007 “Fig 4” Technology Cycle Timing Compared to Actual Wafer Production
Technology Capacity Distribution
Feature Size (Half Pitch) (μm)
10
[Updated
Through
2Q07]
W.P.C = Total W
Worldwide
Capacity;
Source:
SICAS*
.P.C.=Total WorldWafer
wide WaferProduction
ProductionCapacity*
Sources:SICA
S
W.P.C
W.P.C
W.P.C
W.P.C
W.P.C
W.P.C
W.P.C
W.P.C
W.P.C
W.P.C
W.P.C
2007 ITRS
MPU/ASIC
(2.5-yr Cycle)
SIA/SICAS
Data**:
1-yr
delay from
ITRS Cycle
Timing
to >20% of
MOS IC
Capacity
1
0.1
ITRS
Technology
Cycle
>0.7μm
720nm
0.7-0.4μm
510nm
0.4-0.3μm
360nm
0.3- 0.2μm
255nm
0.2- 0.16μm
180nm
0.16-.12μm
127nm
= 2005/06 ITRS DRAM Contacted M1 Half-Pitch Actual
= 2007 ITRS DRAM Contacted M1 Half-Pitch Target
= 2007 ITRS Flash Uncontacted Poly Half Pitch Target
3-Year Cycle
0.01
2-Year Cycle
<0.12μm
3-Yr Cycle
90nm
Note: Includes
<80nm split-out
Note: The wafer production capacity data are plotted from the Semiconductor Industry Association (SIA) Semiconductor Industry Capacity
(ITRS 65nm)
Statistics (SICAS) 4Q data for each year, except 2Q data for 2007.
to be added
The width of each of the production capacity bar corresponds to the MOS IC production start silicon area for that range
In the 2008
of the feature size (y-axis). Data are based upon capacity if fully utilized.
ITRS Upcate
** Source: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity
18by the
Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published
Semiconductor Industry Association (SIA), as of August, 2007. The detailed data are available to the public online at the SIA website, http://www.siaITRS 2008 Update Preparation – July, San Francisco, USA
Work in Progress – Do Not Publish
online.org/pre_stat.cfm .
1997
2002 2003
2003 2004
2004 2005
1997 1998
1998 1999
1999 2000
2000 2001
2001 2002
2005 2006
2006 2007
2007
Year
----
2010
SICAS 1Q08 Update (www.sia-online.org )
WSpW x1000
MOS Capacity by Dimensions
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
>=0.7µ
<0.7µ >=0.4µ
<0.4µ >=0.3µ
<0.3µ >=0.2µ
<0.2µ >=0.16µ
<0.16µ >=0.12µ
~33%
~33%
<0.12µ
<0.12µ >=0.08µ
2yr Cycle
~0.7x
<0.08µ
2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q
05 05 05 06 06 06 06 07 07 07 07 08
19
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
WSpW x1000
(8 inch equivalents)
SICAS 1Q08 Update (www.sia-online.org )
>16% CAGR
MOS Capacity by Wafer-size
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
~27Bcm2
~39Bcm2
~4Bcm2/16%
~5Bcm2/14%
~18Bcm2/46%
~17Bcm2/62%
~16Bcm2/41%
< 200m
200mm
~6Bcm2/22%
300mm
2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q
05 05 05 06 06 06 06 07 07 07 07 08
Work in Progress – Do Not Publish
20
ITRS 2008 Update Preparation – July, San Francisco, USA
2007 ITRS Definitions:
“More Moore” and “More than Moore”
1. Scaling (“More Moore”)
a. Geometrical (constant field) Scaling refers to the continued shrinking of
horizontal and vertical physical feature sizes of the on-chip logic and memory
storage functions in order to improve density (cost per function reduction)
and performance (speed, power) and reliability values to the applications and
end customers.
b. Equivalent Scaling which occurs in conjunction with, and also enables,
continued Geometrical Scaling, refers to 3-dimensional device structure
(“Design Factor”) Improvements plus other non-geometrical process
techniques and new materials that affect the electrical performance of the
chip.
2. Functional Diversification (“More than Moore”)
Functional Diversification refers to the incorporation into devices of
functionalities that do not necessarily scale according to "Moore's Law," but
provide additional value to the end customer in different ways. The "Morethan-Moore" approach typically allows for the non-digital functionalities (e.g.
RF communication, power control, passive components, sensors, actuators)
to migrate from the system board-level into a particular package-level
(SiP) or chip-level (SoC) potential solution.
Work in Progress – Do Not Publish
21
ITRS 2008 Update Preparation – July, San Francisco, USA
More than Moore Study Group 4/3/08
ORTC Summary – 2008 Update Status
Design TWG Proposed “More Moore” and “MtM” Text, 3 Apr 2008 Plenary v2a
[discussion leader – Andrew Kahng] – Proposal accepted at Koenigswinter.
• 1 = More Moore
–
–
–
–
1a = geometric scaling
1b = equivalent scaling
1c = Design equivalent scaling
NEED: quantifiable, specific Design Technologies that deal with More Moore
– “Design equivalent scaling occurs in conjunction with Equivalent Scaling and continued
Geometric Scaling, and refers to design technologies that enable high performance, low
power, high reliability, low cost, and high design productivity.”
– “Examples (not exhaustive) are: Design for variability; low power design (sleep modes,
hibernation, clock gating, multi-VDD, ...); and homogeneous and heterogeneous multicore
SOC architectures.”
– Request: Please remove “b) Multi-core MPU architecture” from 2 (MTM Functional
Diversification)
• 2 = More than Moore
– NEED: Design technologies to enable functional diversification
– “Design technologies enable new functionality that takes advantage of More than Moore
technologies.”
– “Examples (not exhaustive) are: Heterogeneous system partitioning and simulation; software;
analog and mixed signal design technologies for sensors and actuators; and new methods
and tools for co-design and co-simulation of SIP, MEMS, and biotechnology.”
22
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA
“Beyond CMOS” Definition
“Beyond CMOS” refers to emerging research devices, focused
on a “new switch*” used to process information, typically
exploiting a new state variable to provide functional scaling
substantially beyond that attainable by ultimately scaled CMOS.
Substantial scaling beyond CMOS is defined in terms of
functional density, increased performance, dramatically reduced
power, etc.
*The “New Switch” refers to an “information processing
element or technology”, which is associated with
compatible storage or memory and interconnect functions.
Examples of Beyond CMOS include: carbon-based nanoelectronics, spin-based devices, ferromagnetic logic, atomic
switch, NEMS switches, etc.
23
Work in Progress – Do Not Publish
ITRS 2008 Update Preparation – July, San Francisco, USA