Altera Digital Library
About the Altera Digital Library
Literature
The FLEX 10K Solution
How to Contact Altera
Copyright 1996 Altera Corporation
About the
Altera Digital Library
September 1996, ver. 1
The Altera Digital Library contains all current technical literature for the
FLEX 10K, FLEX 8000, MAX 9000, MAX 7000, FLASHlogic, MAX 5000,
Classic, and Configuration EPROM device families, MAX+PLUS II
development tools, and programming hardware. In addition, updates to
Altera literature are provided through links that allow you to jump
directly to the new information.
The Altera Digital Library also includes an interactive multimedia
presentation, The FLEX 10K Solution, which is available for PC users only,
and requires QuickTime for Windows 2.1.1. If you are running an older
version of QuickTime, please install QuickTime for Windows 2.1.1
provided on the Altera Digital Library CD-ROM to ensure that the
presentation runs properly.
For information on product availability, pricing, and order status, contact
your local Altera sales representative or see How to Contact Altera.
The following topics are covered in this section:
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About the Altera Digital Library
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About the Altera Digital Library
Altera
Literature
Updates
In the Altera Digital Library, each updated page contains an Updates
button that is linked to this section. The following list summarizes the
updated information contained in this section:
■
FLEX 10K Programmable Logic Device Family Data Sheet
Pages 85 and 86, Table 16
■
MAX 7000 Programmable Logic Device Family Data Sheet
Page 222, External Timing Parameters
Page 224, External Timing Parameters
Page 226, External Timing Parameters
■
AN 73 (Implementing FIR Filters in FLEX Devices)
Page 5, Figure 4
■
AN 74 (Evaluating Power for Altera Devices)
Page 429, Figure 1
Page 430, Figure 2
■
Component Selection Guide Data Sheet
Page 17, Table 2
Page 26, Table 11
■
Altera Programming Hardware Data Sheet
Page 574, FLEX Download Cable Ordering Code
FLEX 10K Programmable Logic Device Family Data Sheet
Pages 85 and 86, Table 16
Table 16 lists incorrect pin numbers for the 84-pin EPF10K10 in PLCC
packages. The following table provides updated pin-out information for
this package (updated information is highlighted in yellow).
Altera Corporation
3
About the Altera Digital Library
FLEX 10K Device Pin-Outs (Part 1 of 2)
Pin Name
Note (1)
84-Pin PLCC
EPF10K10
208-Pin PQFP
EPF10K10
208-Pin RQFP
EPF10K20
EPF10K30
EPF10K40
240-Pin RQFP
EPF10K20
EPF10K30
EPF10K40
EPF10K50
EPF10K70
MSEL0 (2)
31
108
MSEL1 (2)
32
107
107
123
nSTATUS (2)
55
52
52
60
108
124
nCONFIG (2)
34
105
105
121
DCLK (2)
13
155
155
179
CONF_DONE (2)
76
2
2
2
INIT_DONE (4)
69
19
19
26
nCE (2)
14
154
154
178
nCEO (2)
75
3
3
3
nWS (3)
80
206
206
238
nRS (3)
81
204
204
236
nCS (3)
78
208
208
240
CS (3)
79
207
207
239
RDYnBSY (3)
70
16
16
23
CLKUSR (3)
73
10
10
11
DATA7 (3)
5
166
166
190
DATA6 (3)
6
164
164
188
DATA5 (3)
7
162
162
186
DATA4 (3)
8
161
161
185
DATA3 (3)
9
159
159
183
DATA2 (3)
10
158
158
182
DATA1 (3)
11
157
157
181
DATA0 (2)
12
156
156
180
TDI (2)
15
153
153
177
TDO (2)
74
4
4
4
TCK (2)
77
1
1
1
TMS (2)
57
50
50
58
nTRST (2)
56
51
51
59
Dedicated Inputs
42, 44, 84, 2
78, 80, 182, 184
78, 80, 182, 184
90, 92, 210, 212
Dedicated Clock Pins
43,1
79, 183
79, 183
91, 211
DEV_CLRn (4)
3
180
180
209
DEV_OE (4)
83
186
186
213
4
Altera Corporation
About the Altera Digital Library
FLEX 10K Device Pin-Outs (Part 2 of 2)
Pin Name
VCCINT (5.0 V)
84-Pin PLCC
EPF10K10
Note (1)
208-Pin PQFP
EPF10K10
208-Pin RQFP
EPF10K20
EPF10K30
EPF10K40
240-Pin RQFP
EPF10K20
EPF10K30
EPF10K40
EPF10K50
EPF10K70
20, 33, 40, 45, 63, 4 6, 23, 35, 43, 76, 77, 6, 23, 35, 43, 76, 77, 5, 16, 27, 37, 47, 57,
106, 109, 117, 137, 106, 109, 117, 137, 77, 89, 96, 112, 122,
145, 181
145, 181
130, 140, 150, 160,
170, 189, 205, 224
VCCIO (5.0 V or 3.3 V) –
5, 22, 34, 42, 66, 84, 5, 22, 34, 42, 66, 84, –
98, 110, 118, 138,
98, 110, 118, 138,
146, 165, 178, 194 146, 165, 178, 194
GNDINT
26, 41, 46, 68, 82
21, 33, 49, 81, 82,
123, 129, 151, 185
21, 33, 49, 81, 82,
123, 129, 151, 185
10, 22, 32, 42, 52,
69, 85, 93, 104, 125,
135, 145, 155, 165,
176, 197, 216, 232
GNDIO
–
20, 32, 48, 59, 72,
91, 124, 130, 152,
171, 188, 201
20, 32, 48, 59, 72,
91, 124, 130, 152,
171, 188, 201
–
No Connect (N.C.)
Note (5)
–
7, 8, 9, 14, 15, 36,
37, 113, 114, 125,
126, 139, 140
–
–
Total User I/O Pins
59
134
147
189
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
All pins that are not listed are user I/O pins.
This pin is a dedicated pin; it is not available as a user I/O pin.
This pin can be used as a user I/O pin after configuration.
This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function.
To maintain pin compatibility when migrating from the EPF10K30 to the EPF10K10 in the 208-pin RQFP package,
do not use these pins as user I/O pins.
To maintain pin compatibility when migrating from the EPF10K50 to the EPF10K30 in the 356-pin BGA package,
do not use these pins as user I/O pins.
To maintain pin compatibility when migrating from the EPF10K100 to the EPF10K70 in the 503-pin PGA package,
do not use these pins as user I/O pins.
Altera Corporation
5
About the Altera Digital Library
MAX 7000 Programmable Logic Device Family Data Sheet
Page 222, External Timing Parameters
Page 224, External Timing Parameters
Page 226, External Timing Parameters
Some of the notes in the External Timing Parameters tables are numbered
incorrectly. An updated version is provided in the following tables and
notes.
Speed Grade
External Timing Parameters
MAX 7000E (-10P) MAX 7000 (-10)
MAX 7000S (-10) MAX 7000E (-10)
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
ns
tPD1
Input to non-registered output
C1 = 35 pF
10
10
tPD2
I/O input to non-registered output
C1 = 35 pF
10
10
tSU
Global clock setup time
7
8
ns
tH
Global clock hold time
0
0
ns
tFSU
Global clock setup time of fast input Note (3)
3
3
ns
0.5
ns
tFH
Global clock hold time of fast input Note (3)
tCO1
Global clock to output delay
tCH
Global clock high time
4
4
ns
tCL
Global clock low time
4
4
ns
tASU
Array clock setup time
2
3
ns
tAH
Array clock hold time
3
3
tACO1
Array clock to output delay
tACH
Array clock high time
4
4
ns
tACL
Array clock low time
4
4
ns
tODH
Output data hold time after clock
tCNT
Minimum global clock period
fCNT
Maximum internal global clock
frequency
tACNT
Minimum array clock period
fACNT
fMAX
6
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF, Note (4)
0.5
5
10
1
ns
5
ns
10
1
10
ns
ns
ns
10
ns
Note (5)
100
Maximum internal array clock
frequency
Note (5)
100
100
MHz
Maximum clock frequency
Note (6)
125
125
MHz
100
10
MHz
10
ns
Altera Corporation
About the Altera Digital Library
Speed Grade
External Timing Parameters
MAX 7000E (-12P) MAX 7000 (-12)
MAX 7000E (-12)
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
ns
tPD1
Input to non-registered output
C1 = 35 pF
12
12
tPD2
I/O input to non-registered output
C1 = 35 pF
12
12
tSU
Global clock setup time
7
10
ns
tH
Global clock hold time
0
0
ns
ns
ns
tFSU
Global clock setup time of fast input Note (3)
3
3
tFH
Global clock hold time of fast input Note (3)
1
1
tCO1
Global clock to output delay
tCH
Global clock high time
4
4
ns
tCL
Global clock low time
4
4
ns
tASU
Array clock setup time
3
4
ns
tAH
Array clock hold time
4
4
ns
tACO1
Array clock to output delay
tACH
Array clock high time
tACL
Array clock low time
tODH
Output data hold time after clock
tCNT
Minimum global clock period
fCNT
Maximum internal global clock
frequency
tACNT
Minimum array clock period
fACNT
fMAX
C1 = 35 pF
6
C1 = 35 pF
C1 = 35 pF, Note (4)
ns
6
12
12
ns
ns
5
5
ns
5
5
ns
1
1
11
ns
11
ns
Note (5)
90.9
Maximum internal array clock
frequency
Note (5)
90.9
90.9
MHz
Maximum clock frequency
Note (6)
125
125
MHz
Altera Corporation
90.9
11
MHz
11
ns
7
About the Altera Digital Library
Speed Grade
External Timing Parameters
-15
Symbol
Parameter
Conditions
Min
-15T
Max
Min
-20
Max
Min
Max
Unit
tPD1
Input to non-registered output
C1 = 35 pF
15
15
20
ns
tPD2
I/O input to non-registered
output
C1 = 35 pF
15
15
20
ns
tSU
Global clock setup time
11
11
12
ns
tH
Global clock hold time
0
0
0
ns
tFSU
Global clock setup time of fast
input
Note (3)
3
–
5
ns
tFH
Global clock hold time of fast
input
Note (3)
1
–
2
ns
tCO1
Global clock to output delay
C1 = 35 pF
tCH
Global clock high time
5
6
6
ns
tCL
Global clock low time
5
6
6
ns
tASU
Array clock setup time
4
4
5
ns
tAH
Array clock hold time
tACO1
Array clock to output delay
tACH
Array clock high time
6
6.5
8
ns
tACL
Array clock low time
6
6.5
8
ns
tODH
Output data hold time after
clock
1
1
1
ns
tCNT
Minimum global clock period
fCNT
Maximum internal global clock
frequency
tACNT
Minimum array clock period
fACNT
Maximum internal array clock
frequency
Note (5)
76.9
76.9
62.5
MHz
fMAX
Maximum clock frequency
Note (6)
100
83.3
83.3
MHz
8
4
C1 = 35 pF
C1 = 35 pF, Note (4)
8
4
15
76.9
5
15
13
Note (5)
12
13
ns
20
13
76.9
16
62.5
13
ns
ns
ns
MHz
16
ns
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
8
Operating conditions:
VCCINT = 5.0 V ± 5%, VCCIO = 5.0 V ± 5% (except where noted), TA = 0° C to 70° C for commercial use.
VCCINT = 5.0 V ± 10%, VCCIO = 5.0 V ± 10% (except where noted), TA = –40° C to 85° C for industrial use.
Timing parameters for some devices are preliminary. See Table 2 on page 193 of this data sheet for available speed
grades and Table 4 on page 195 for available packages.
This parameter applies only to MAX 7000E and MAX 7000S devices.
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
The fMAX values represent the highest frequency for pipelined data.
Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use.
The tLPA parameter must be added to the tLAD, tLAC, tIC, tACL, tEN, and tSEXP parameters for macrocells running in
the low-power mode.
Altera Corporation
About the Altera Digital Library
Application Note 73 (Implementing FIR Filters)
Page 5, Figure 4
The equation in Figure 4 is incorrect. Instead, the multiplier in the figure
below performs the following function:
[s(4) × h(4)] + [s(3) × h(3)] + [s(2) × h(2)] + [s(1) × h(1)]
Four 2-Bit Input Vector Multiplier
This multiplier performs the function [s(4) × h(4)] + [s(3) × h(3)] + [s(2) × h(2)] + [s(1) × h(1)]. Both LUTs consist of 4
FLEX 16 × 1 LUTs.
2
s(1)
2
s(2)
2
Black lines denote s(n)2.
2
s(3)
s(4)
Blue lines denote s(n)1.
LE
LE
LE
16 × 4 LUT2
LE
LE
LE
LE
LE
16 × 4 LUT1
4
4
P2
P1
Multiply by 2
4
6
y(n)
Application Note 74 (Evaluating Power for Altera Devices)
Page 429, Figure 1
In Figure 1, the units for the following variables should be as follows:
CAVE = _______ pF
PACOUT = _______mW
The following figure provides an updated worksheet for performing a
power evaluation.
Altera Corporation
9
About the Altera Digital Library
Power Evaluation Worksheet (Part 1 of 2)
Design:_______________________
Device:_______________________
Estimating the Power Consumption of the Application
Internal Power Calculation
FLEX 10K & FLEX 8000 Devices
Standby current (ICCSTANDBY)
Coefficient for ICC calculation. See the appropriate device family
ICCSTANDBY = _________mA
K = _________uA/MHz × LE
data sheet for this value.
Highest clock frequency of the device (fMAX)
Logic elements used (N)
fMAX = _________MHz
N = _________
Average ratio of logic cells toggling (togLC) at each clock (typically 0.125)
togLC = _________
Total internal current (ICCINT)
ICCINT = _________mA
ICCINT = ICCSTANDBY + K × fMAX × N × togLC
Total internal power (PINT)
PINT = _________ mW
PINT = VCC × ICCINT
MAX 9000 & MAX 7000 Devices
Coefficients for ICC calculation. See the appropriate device family
data sheet for these values.
A = _________
B = _________
C = _________
Macrocells with turbo bit on (MCTON)
MCTON = _________
Number of macrocells in the device (MCDEV)
MCDEV = _________
Number of macrocells in the design (MCUSED)
Highest clock frequency of the device (fMAX)
MCUSED = _________
fMAX = _________MHz
Average ratio of logic cells toggling (togLC) at each clock (typically 0.125)
togLC = _________
Total internal current (ICCINT)
ICCINT = _________mA
ICCINT = (A × MCTON) + (B × MCTOFF) + (C × MC × fMAX × togLC)
Total internal power (PINT)
PINT = _________mW
PINT = VCC × ICCINT
10
Altera Corporation
About the Altera Digital Library
Power Evalation Worksheet (Part 2 of 2)
External Power Calculation
Power consumed by the DC output load (PDCOUT)
OUT
PDCOUT = __________mW
PDCOUT = ∑ PDC
n=1
n
Average capacitive load (CAVE) at output pins
CAVE = __________pF
Number of output/bidirectional pins in design (OUT)
OUT = __________
Average ratio of I/O pins toggling (togIO) at each clock (typically 0.125)
togIO = __________
Power consumed by AC output load (PACOUT)
PACOUT = __________mW
PACOUT = 1/2 × OUT × CAVE × 3.8V × fMAX × togIO × 5V
Total external power (PIO)
PIO = __________mW
PIO = PDCOUT + PACOUT
Total Power Calculation
Estimated total power (PEST)
PEST = __________mW
PEST = PINT + PIO
Calculating Maximum Allowed Power for the Device & Package
Thermal resistance of the device
Maximum junction temperature (TJ) as specified in the appropriate
θJA = _________C/W
TJ = _________° C
device family data sheet
Ambient temperature (TA) of the design
Maximum power (PMAX) allowed for the device
TA = _________° C
PMAX = _________W
PMAX = TJ – TA
_______
θJA
Comparing Maximum Power Allowed & Estimated Power
Is PEST < PMAX?
Altera Corporation
Yes or No
11
About the Altera Digital Library
Page 430, Figure 2
In Figure 2, the PINT value for an EPF10K50GC403-4 device is 2785 mW.
Component Selection Guide Data Sheet
Page 17, Table 2
The following table provides additional information on the number of
EABs for each FLEX 10K device.
FLEX 10K Devices
Device
EPF10K10
Note (1)
Typical Packages Temp. Speed Process
Gates
(2)
(3)
Grade
10,000 L, T, Q
Logic Cells/
Registers
Ded.
Inputs
I/O Pins
Number
of Pins
EABs
C
C, I
-3
-4
SRAM 576 / 720
SRAM 576 / 720
6
6
59, 107,
134
84, 144,
208
3
C, I
-4
SRAM 576/720
6
59, 107,
134
84, 144,
208
3
-3
SRAM 1,152 / 1,344
6
147, 189
208, 240
208, 240
6
EPF10K20
20,000 R
C
CI
-4
SRAM 1,152 / 1,344
6
147, 189
208, 240
6
EPF10K30
30,000 R, B
C
-3
SRAM 1,728 / 1,968
6
147, 189,
246
208, 240,
356
6
C,I
-4
SRAM 1,728/1,968
6
147, 189,
246
208, 240,
356
6
C
-3
SRAM 2,304 / 2,576
6
147, 189
208, 240
8
C, I
-4
SRAM 2,304 / 2,576
6
147, 189
208, 240
8
C
-3
SRAM 2,880 / 3,184
6
189, 274,
310
240, 356,
403
10
C, I
-4
SRAM 2,880 / 3,184
6
189, 274,
310
240, 356,
403
10
C, I
-5
SRAM 2,880 / 3,184
6
189, 274,
310
240, 356,
403
10
C
-3
SRAM 3,744 / 4,096
6
189, 358
240, 503
9
C, I
-4
SRAM 3,744 / 4,096
6
189, 358
240, 503
9
C
-3
SRAM 4,992 / 5,392
6
406
503
12
C, I
-4
SRAM 4,992 / 5,392
6
406
503
12
EPF10K40
EPF10K50
EPF10K70
40,000 R
50,000 R, G, B
70,000 R, G
EPF10K100 100,000 G
12
Altera Corporation
About the Altera Digital Library
Page 26, Table 11
FLEX 10K devices in 84-pin PLCC and 240-pin RQFP packages do not
support 3.3-V/5.0-V I/O pins. The following table provides updated
information for these packages.
Devices with 3.3-V/5.0-V I/O Pins
Device Family
Mixed-Voltage Devices
FLEX 10K
All devices except 84-pin PLCC and 240-pin RQFP
packages
FLEX 8000
EPF8636A (except 84-pin PLCC packages), EPF8820A,
EPF81188A, and EPF81500A
MAX 9000
All devices
MAX 7000
All devices except 44-pin packages
FLASHlogic
All devices
Altera Programming Hardware Data Sheet
Page 574, FLEX Download Cable Ordering Code
The FLEX Download Cable is provided with the EPC1213 and EPC1064
programming adapters and does not have a separate ordering code.
PL-FDLC is the ordering code for the FLASHlogic Download Cable, not
the FLEX Download Cable.
Altera Corporation
13
Contents
®
About The Altera Digital Library
FLEX 10K Devices
FLEX 10K Embedded Programmable Logic Family Data Sheet
FLEX 10K Embedded Programmable Logic Family Data Sheet Supplement, ver. 2.1
FLEX 10K Embedded Programmable Logic Family Data Sheet Supplement, ver. 2.2
Configuration EPROMs for FLEX Devices Data Sheet
Altera Device Package Information Data Sheet
Altera Programming Hardware Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlaster Parallel Port Download Cable Data Sheet
MPLDs: Mask-Programmed Logic Devices Data Sheet
Operating Requirements for Altera Devices Data Sheet
AB 111 Accumulators in FLEX 8000 Devices, Note (1)
AB 113 Equality Comparators in FLEX 8000 Devices, Note (1)
AB 114 Full Comparators in FLEX 8000 Devices, Note (1)
AB 115 Carry Look-Ahead Counters in FLEX 8000 Devices, Note (1)
AB 117 Barrel Shifters in FLEX 8000 Devices, Note (1)
AB 118 Ripple-Carry Adders in FLEX 8000 Devices, Note (1)
AB 121 Designing Counters in FLEX 8000 Devices, Note (1)
AB 122 Carry Look-Ahead Counters in FLEX 8000 Devices, Note (1)
AB 123 Pipelined Carry Look-Ahead Counters in FLEX 8000 Devices, Note (1)
AB 124 Prescaled Counters in FLEX 8000 Devices, Note (1)
AB 125
Designing Adders, Accumulators & Subtractors in FLEX 8000 Devices, Note (1)
AB 126 Subtractors in FLEX 8000 Devices, Note (1)
AB 127 Designing Multipliers in FLEX 8000 Devices, Note (1)
AB 128 Multiplexers in FLEX 8000 Devices, Note (1)
Altera Corporation
Contents
AB 130 Parity Generators in FLEX 8000 Devices, Note (1)
AB 131 State Machine Encoding
AB 132 Ripple-Carry Multipliers in FLEX 8000 Devices, Note (1)
AB 133 Combinatorial Multipliers Using Booth’s Algorithm in FLEX 8000 Devices, Note (1)
AB 134 Pipelined Multipliers in FLEX 8000 Devices, Note (1)
AB 135 Ripple-Carry Gray Code Counters in FLEX 8000 Devices, Note (1)
AB 137 Ripple-Carry Counters in FLEX 8000 Devices, Note (1)
AB 140 PCI Compliance of Altera Devices
AN 39
JTAG Boundary-Scan Testing in Altera Devices
AN 41
PCI Bus Applications for Altera Devices
AN 42
Metastability in Altera Devices
AN 49
Implementing CRCCs in Altera Devices
AN 51
Using Programmable Logic for Gate Array Designs
AN 52
Implementing RAM Functions in FLEX 10K Devices
AN 53
Implementing Multipliers in FLEX 10K Devices
AN 59
Configuring FLEX 10K Devices
AN 65
Implementing Dual-Port RAM in FLEX 10K Devices
AN 66
Implementing FIFO Buffers in FLEX 10K Devices
AN 73
Implementing FIR Filters in FLEX Devices
AN 74
Evaluating Power for Altera Devices
AN 80
Selecting Sockets for Altera Devices
AN 81
Reflow Soldering Guidelines for Surface-Mount Devices
PIB 20
Benefits of Embedded RAM in FLEX 10K Devices
PIB 21
Implementing Logic with the Embedded Array in FLEX 10K Devices
PIB 22
Design Tools for 100,000-Gate Programmable Logic Devices
PIB 23
Digital Signal Processing in FLEX Devices
Note:
(1) Although this document was originally written for FLEX 8000 devices, it can also be used to design for FLEX 10K
devices.
Altera Corporation
Contents
FLEX 8000 Devices
FLEX 8000 Programmable Logic Device Family Data Sheet
Configuration EPROMs for FLEX Devices Data Sheet
Altera Device Package Information Data Sheet
Altera Programming Hardware Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlaster Parallel Port Download Cable Data Sheet
MPLDs: Mask-Programmed Logic Devices Data Sheet
Operating Requirements for Altera Devices Data Sheet
AB 111 Accumulators in FLEX 8000 Devices
AB 113 Equality Comparators in FLEX 8000 Devices, Note (1)
AB 114 Full Comparators in FLEX 8000 Devices, Note (1)
AB 115 Carry Look-Ahead Counters in FLEX 8000 Devices
AB 117 Barrel Shifters in FLEX 8000 Devices
AB 118 Ripple-Carry Adders in FLEX 8000 Devices
AB 121 Designing Counters in FLEX 8000 Devices
AB 122 Carry Look-Ahead Counters in FLEX 8000 Devices
AB 123 Pipelined Carry Look-Ahead Counters in FLEX 8000 Devices
AB 124 Prescaled Counters in FLEX 8000 Devices
AB 125 Designing Adders, Accumulators & Subtractors in FLEX 8000 Devices
AB 126 Subtractors in FLEX 8000 Devices
AB 127 Designing Multipliers in FLEX 8000 Devices
AB 128 Multiplexers in FLEX 8000 Devices
AB 130 Parity Generators in FLEX 8000 Devices
AB 131 State Machine Encoding
AB 132 Ripple-Carry Multipliers in FLEX 8000 Devices
AB 133 Combinatorial Multipliers Using Booth’s Algorithm in FLEX 8000 Devices
AB 134 Pipelined Multipliers in FLEX 8000 Devices
AB 135 Ripple-Carry Gray Code Counters in FLEX 8000 Devices
AB 137 Ripple-Carry Counters in FLEX 8000 Devices
AB 140 PCI Compliance of Altera Devices
AN 33
Configuring FLEX 8000 Devices
AN 36
Designing with FLEX 8000 Devices
AN 38
Configuring Multiple FLEX 8000 Devices
AN 39
JTAG Boundary-Scan Testing in Altera Devices
Altera Corporation
Contents
AN 41
PCI Bus Applications for Altera Devices
AN 42
Metastability in Altera Devices
AN 46
ATM Packet Scheduler in FLEX 8000 Devices
AN 49
Implementing CRCCs in Altera Devices
AN 51
Using Programmable Logic for Gate Array Designs
AN 73
Implementing FIR Filters in FLEX Devices
AN 74
Evaluating Power for Altera Devices
AN 75
High-Speed Board Designs
AN 76
Understanding FLEX 8000 Timing
AN 80
Selecting Sockets for Altera Devices
AN 81
Reflow Soldering Guidelines for Surface-Mount Devices
PIB 23
Digital Signal Processing in FLEX Devices
MAX 9000 Devices
MAX 9000 Programmable Logic Device Family Data Sheet
Altera Device Package Information Data Sheet
Altera Programming Hardware Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlaster Parallel Port Download Cable Data Sheet
MPLDs: Mask-Programmed Logic Devices Data Sheet
Operating Requirements for Altera Devices Data Sheet
QFP Carrier & Development Socket Data Sheet
AB 140 PCI Compliance of Altera Devices
AB 141 In-System Programmability in MAX 9000 Devices
AN 39
JTAG Boundary-Scan Testing in Altera Devices
AN 41
PCI Bus Applications for Altera Devices
AN 42
Metastability in Altera Devices
AN 43
Designing for MAX 9000 Devices
AN 74
Evaluating Power for Altera Devices
AN 77
Understanding MAX 9000 Timing
AN 80
Selecting Sockets for Altera Devices
AN 81
Reflow Soldering Guidelines for Surface-Mount Devices
Altera Corporation
Contents
MAX 7000 Devices
MAX 7000 Programmable Logic Device Family Data Sheet
Altera Device Package Information Data Sheet
Altera Programming Hardware Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlaster Parallel Port Download Cable Data Sheet
Operating Requirements for Altera Devices Data Sheet
QFP Carrier & Development Socket Data Sheet
AB 140 PCI Compliance of Altera Devices
AB 145 Designing for In-System Programmability in MAX 7000S Devices
AN 41
PCI Bus Applications for Altera Devices
AN 42
Metastability in Altera Devices
AN 74
Evaluating Power for Altera Devices
AN 78
Understanding MAX 7000, MAX 5000 & Classic Timing
AN 80
Selecting Sockets for Altera Devices
AN 81
Reflow Soldering Guidelines for Surface-Mount Devices
FLASHlogic Devices
FLASHlogic Programmable Logic Device Family Data Sheet
Altera Device Package Information Data Sheet
Altera Programming Hardware Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlaster Parallel Port Download Cable Data Sheet
MPLDs: Mask-Programmed Logic Devices Data Sheet
Operating Requirements for Altera Devices Data Sheet
AB 140 PCI Compliance of Altera Devices
AN 39
JTAG Boundary-Scan Testing in Altera Devices
AN 41
PCI Bus Applications for Altera Devices
AN 42
Metastability in Altera Devices
AN 45
Configuring FLASHlogic Devices
AN 74
Evaluating Power for Altera Devices
Altera Corporation
Contents
AN 79
Understanding FLASHlogic Timing
AN 80
Selecting Sockets for Altera Devices
AN 81
Reflow Soldering Guidelines for Surface-Mount Devices
MAX 5000 Devices
MAX 5000 Programmable Logic Device Family Data Sheet
Altera Device Package Information Data Sheet
Altera Programming Hardware Data Sheet
MPLDs: Mask-Programmed Logic Devices Data Sheet
Operating Requirements for Altera Devices Data Sheet
QFP Carrier & Development Socket Data Sheet
AB 140 PCI Compliance of Altera Devices
AN 41
PCI Bus Applications for Altera Devices
AN 42
Metastability in Altera Devices
AN 74
Evaluating Power for Altera Devices
AN 78
Understanding MAX 7000, MAX 5000 & Classic Timing
AN 80
Selecting Sockets for Altera Devices
AN 81
Reflow Soldering Guidelines for Surface-Mount Devices
Classic Devices
Classic EPLD Family Data Sheet
EP220 & EP224 Classic EPLDs Data Sheet
EP312 & EP324 Classic EPLDs Data Sheet
Altera Device Package Information Data Sheet
Altera Programming Hardware Data Sheet
Operating Requirements for Altera Devices Data Sheet
AN 42
Metastability in Altera Devices
AN 74
Evaluating Power for Altera Devices
AN 78
Understanding MAX 7000, MAX 5000 & Classic Timing
AN 80
Selecting Sockets for Altera Devices
AN 81
Reflow Soldering Guidelines for Surface-Mount Devices
Altera Corporation
Contents
Megafunctions & Reference Designs
AMPP Catalog
FS 1
FIR Filters
FS 2
fp_add_sub Floating-Point Adder/Subtractor
FS 3
Integer Dividers
FS 4
fp_mult Floating-Point Multiplier
Tools
EDA Software Support
MAX+PLUS II Programmable Logic Development System & Software Data Sheet
Cadence & MAX+PLUS II Software Interface Guide
Mentor Graphics & MAX+PLUS II Software Interface Guide
Synopsys & MAX+PLUS II Software Interface Guide
Viewlogic Powerview & MAX+PLUS II Software Interface Guide
Altera/Synopsys User Guide
DSP
AMPP Catalog
AN 53
Implementing Multipliers in FLEX 10K Devices
AN 73
Implementing FIR Filters in FLEX 10K Devices
AN 75
High-Speed Board Designs
FS 1
FIR Filters
FS 2
fp_add_sub Floating-Point Adder/Subtractor
FS 3
Integer Dividers
FS 4
fp_mult Floating-Point Multiplier
PIB 23
Digital Signal Processing in FLEX Devices
PCI
AMPP Catalog
AB 140 PCI Compliance of Altera Devices
AN 41
PCI Bus Applications for Altera Devices
Altera Corporation
Contents
Communications
AMPP Catalog
AN 46
ATM Packet Scheduler in FLEX 8000 Devices
AN 49
Implementing CRCCs in Altera Devices
Application Briefs
AB 111 Accumulators in FLEX 8000 Devices
AB 113 Equality Comparators in FLEX 8000 Devices
AB 114 Full Comparators in FLEX 8000 Devices
AB 115 Carry Look-Ahead Counters in FLEX 8000 Devices
AB 117 Barrel Shifters in FLEX 8000 Devices
AB 118 Ripple-Carry Adders in FLEX 8000 Devices
AB 121 Designing Counters in FLEX 8000 Devices
AB 122 Carry Look-Ahead Counters in FLEX 8000 Devices
AB 123 Pipelined Carry Look-Ahead Counters in FLEX 8000 Devices
AB 124 Prescaled Counters in FLEX 8000 Devices
AB 125 Designing Adders, Accumulators & Subtractors in FLEX 8000 Devices
AB 126 Subtractors in FLEX 8000 Devices
AB 127 Designing Multipliers in FLEX 8000 Devices
AB 128 Multiplexers in FLEX 8000 Devices
AB 130 Parity Generators in FLEX 8000 Devices
AB 131 State Machine Encoding
AB 132 Ripple-Carry Multipliers in FLEX 8000 Devices
AB 133 Combinatorial Multipliers Using Booth’s Algorithm in FLEX 8000 Devices
AB 134 Pipelined Multipliers in FLEX 8000 Devices
AB 135 Ripple-Carry Gray Code Counters in FLEX 8000 Devices
AB 137 Ripple-Carry Counters in FLEX 8000 Devices
AB 140 PCI Compliance of Altera Devices
AB 141 In-System Programmability in MAX 9000 Devices
AB 145 Designing for In-System Programmability in MAX 7000S Devices
Altera Corporation
Contents
Application Notes
AN 33
Configuring FLEX 8000 Devices
AN 36
Designing with FLEX 8000 Devices
AN 38
Configuring Multiple FLEX 8000 Devices
AN 39
JTAG Boundary-Scan Testing in Altera Devices
AN 41
PCI Bus Applications for Altera Devices
AN 42
Metastability in Altera Devices
AN 43
Designing for MAX 9000 Devices
AN 45
Configuring FLASHlogic Devices
AN 46
ATM Packet Scheduler in FLEX 8000 Devices
AN 49
Implementing CRCCs in Altera Devices
AN 51
Using Programmable Logic for Gate Array Designs
AN 52
Implementing RAM Functions in FLEX 10K Devices
AN 53
Implementing Multipliers in FLEX 10K Devices
AN 59
Configuring FLEX 10K Devices
AN 65
Implementing Dual-Port RAM in FLEX 10K Devices
AN 66
Implementing FIFO Buffers in FLEX 10K Devices
AN 71
Guidelines for Handling J-Lead & QFP Devices
AN 73
Implementing FIR Filters in FLEX Devices
AN 74
Evaluating Power for Altera Devices
AN 75
High-Speed Board Designs
AN 76
Understanding FLEX 8000 Timing
AN 77
Understanding MAX 9000 Timing
AN 78
Understanding MAX 7000, MAX 5000 & Classic Timing
AN 79
Understanding FLASHlogic Timing
AN 80
Selecting Sockets for Altera Devices
AN 81
Reflow Soldering Guidelines for Surface-Mount Devices
Altera Corporation
Contents
Catalog
AMPP Catalog
Data Sheets & Data Sheet Supplements
DS
FLEX 10K Embedded Programmable Logic Family
DSS
FLEX 10K Embedded Programmable Logic Family, ver. 2.1
DSS
FLEX 10K Embedded Programmable Logic Family, ver. 2.2
DS
FLEX 8000 Programmable Logic Device Family
DS
MAX 9000 Programmable Logic Device Family
DS
MAX 7000 Programmable Logic Device Family
DS
FLASHlogic Programmable Logic Device Family
DS
MAX 5000 Programmable Logic Device Family
DS
EP312 & EP324 Classic EPLDs
DS
EP220 & EP224 Classic EPLDs
DS
Altera Device Package Information
DS
Altera Programming Hardware
DS
BitBlaster Serial Download Cable
DS
ByteBlaster Parallel Port Download Cable
DS
Classic EPLD Family
DS
Component Selection Guide
DS
Configuration Elements & Reliability
DS
Configuration EPROMs for FLEX Devices
DS
MAX+PLUS II Programmable Logic Development System & Software
DS
MPLDs: Mask-Programmed Logic Devices
DS
Operating Requirements for Altera Devices
DS
QFP Carrier & Development Socket
General Information
EDA Software Support
Ordering Information
Programming Hardware Manufacturers
Sales Offices, Distributors & Representatives
Altera Corporation
Contents
Technical Support from Altera Applications
Copyright
Glossary
PIB 18
CPLDs vs. FPGAs: Comparing High-Capacity Programmable Logic
Functional Specifications
FS 1
FIR Filters
FS 2
fp_add_sub Floating-Point Adder/Subtractor
FS 3
Integer Dividers
FS 4
fp_mult Floating-Point Multiplier
Product Information Bulletins
PIB 18
CPLDs vs. FPGAs Comparing High-Capacity Programmable Logic
PIB 20
Benefits of Embedded RAM in FLEX 10K Devices
PIB 21
Implementing Logic with the Embedded Array in FLEX 10K Devices
PIB 22
Design Tools for 100,000-Gate Programmable Logic Devices
PIB 23
Digital Signal Processing in FLEX Devices
Software Interface Guides
Cadence & MAX+PLUS II
Mentor Graphics & MAX+PLUS II
Synopsys & MAX+PLUS II
Viewlogic Powerview & MAX+PLUS II
User Guide
Altera/Synopsys User Guide
Altera Corporation
How to Contact Altera
®
September 1996
For additional information about Altera products, consult the sources
shown in Table 1.
Table 1.
Information Type
Literature
Non-technical customer
service
Technical Support
Access
USA & Canada
All Other Locations
Altera Express
(800) 5-ALTERA
(408) 894-7850
Altera Literature Services
(888) 3-ALTERA (1)
lit_req@altera.com
(888) 3-ALTERA (1)
lit_req@altera.com
Telephone hotline
(800) SOS-EPLD
(408) 894-7000
Fax
(408) 954-8186
(408) 954-8186
Telephone hotline
(8:00 a.m. to 5 p.m.
Pacific Time)
(800) 800-EPLD
(408) 894-7000 (1)
Fax
(408) 954-0348
(408) 954-0348 (1)
Bulletin board service
(408) 954-0104
(408) 954-0104
sos@altera.com
Electronic mail
sos@altera.com
FTP site
ftp.altera.com
ftp.altera.com
CompuServe
go altera
go altera
General product
Telephone
(408) 894-7104
(408) 894-7104 (1)
information
World-wide web
http://www.altera.com
http://www.altera.com
Note:
(1)
You can also contact your local Altera sales office or sales representative. See Sales Offices, Distributors &
Representatives in this CD-ROM.
Altera Corporation
i