CS 320
Hour Exam 1
Take Home Portion
Name_________________________
January 29, 2016
1. A computer system has just 64K of main memory with a 1K cache. Words are just
one byte long.
A) If the cache is direct mapped and the block size is 4 bytes long how is the 16-bit
main memory address broken into Tag, Line, and Word?
B) If the cache is associatively mapped and the block size is 4 bytes long how is the
16-bit main memory address broken into the Tag and Word?
C) If the cache mapping is set associative and the block size is 4 bytes with a set size
of 32 bytes, how is the 16-bit main memory address broken into the Tag, Set, and
Word?
2. Consider a memory system that consists of only 4 blocks and there is a 2 line cache. The
cache is fully associative and requires the sequence of blocks shown below.
A) Show what is in the cache as the program runs if LRU is used?
0
1
1
3
2
2
1
0
1
2
3
2
3
B) What is the hit ratio of the cache for this system.
3. A main memory system has just 1 Mbyte of RAM = 220 bytes. The system has a direct
mapped cache which is 4 Kbytes = 212. If the block size is 8 bytes, what is the cache
address if the main memory address is 0x1A0F9?
4. A computer system has a two-level cache with the following parameters:
tc1 – level-1 access time = 20 nsec
tc2 – level-2 access time = 30 nsec
tm – main memory access time = 70 nsec
h1 – hit ratio for level 1 cache = 0.90
h2 – hit ratio for level 2 cache = 0.93
Find the effective memory access time. You may assume that if there is a miss from one
of the caches, the data is loaded into the cache and into the CPU in parallel.
5. The flow chart below shows the sequence of operations for a memory making use of a single
cache. Note that when there is a cache miss, a block is loaded into the cache and simultaneously
the data is delivered to cpu. In this case the effective access time of the memory system is given
by teff  h  tc  (1  h)  tm
where teff is the effective access time, tc is the cache access time, tm is the main memory access
time, and h is the hit ratio. What is the equation for the effective access time if, in the event of a
cache miss, the cache is loaded first followed by the data being sent to the cpu so that the two
events are in series rather than in parallel?
6. On most machines it is not possible to interrupt the processor until after the current instruction
is complete? Why not?
7. On many microcontroller systems the code memory is read only. List at least three
advantages to doing this.
8. Use the principle of locality of reference to justify have separate instruction and data
caches rather than a single mixed cache that is twice as big.
9. Consider a hypothetical 32-bit computer having 32-bit instructions that have two formats
shown below. Format 1 instructions are used for instructions where the operand is either
immediate data or a memory address of data. Format 2 instruction are used for instructions
which do operations on 3 register operands. Answer the following questions about these two
instruction formats:
A) How many different instructions are possible if these are the only two formats permitted?
B) What is the maximum directly addressable memory capacity (in bytes).
C) What is the maximum number of registers that this machine can have?
10. Consider the following statement: "Using a faster processor chip results in a corresponding
increase in performance of a computer even if the main memory speed remains the same."
A) Under what conditions might this statement be true or approximately true?
B) Under what conditions might this statement be false or mostly false?