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6.004 Computation Structures
Spring 2009
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Sequential Logic:
6.004: Progress so far…
adding a little state
PHYSICS: Continuous
variables, Memory, Noise,
f(RC) = 1 - e-t/RC
COMBINATIONAL: Discrete,
memoryless, noise-free,
lookup table functions
C
0
0
0
0
1
1
1
1
2.71354 volts
B
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Y
0
1
0
1
0
0
1
1
01101
Lab #1 is due tonight
(checkoff meeting by next Thursday).
What other
building
blocks do we
need in order
to compute?
QUIZ #1 Tomorrow!
(covers thru L4/R5)
2/19/09
6.004 – Spring 2009
modified 2/17/09 10:26
L05 – Sequential Logic 1
2/19/09
6.004 – Spring 2009
Digital State
Something We Can’t Build (Yet)
One model of what we’d like to build
What if you were given the following design specification:
button
When the button is pushed:
1) Turn on the light if
it is off
2) Turn off the light if
it is on
L05 – Sequential Logic 2
New
State
Memory
Device
Current
State
LOAD
light
The light should change
state within a second
of the button press
Combinational
Logic
Input
What makes this circuit so different
from those we’ve discussed before?
Output
Plan: Build a Sequential Circuit with stored digital STATE –
• Memory stores CURRENT state, produced at output
• Combinational Logic computes
1. “State” – i.e. the circuit has memory
2. The output was changed by a input
“event” (pushing a button) rather
than an input “value”
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 3
• NEXT state (from input, current state)
• OUTPUT bit (from input, current state)
• State changes on LOAD control input
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 4
Needed: Storage
Storage: Using Capacitors
Combinational logic is stateless:
We’ve chosen to encode information using voltages and we know
from 6.002 that we can “store” a voltage as charge on a capacitor:
valid outputs always reflect current inputs.
To build devices with state, we need components which store
information (e.g., state) for subsequent access.
ROMs (and other combinational logic) store information “wired in” to their
truth table
Read/Write memory elements are required to build devices capable of
changing their contents.
Mechanics: holes in cards/tapes
Optics: Film, CDs, DVDs, …
Magnetic materials
Delay lines; moonbounce
Stored charge
2/19/09
6.004 – Spring 2009
Bit
line
N-channel fet serves
as access switch
L05 – Sequential Logic 5
It’s easy to build a settable storage element (called a latch)
using a lenient MUX:
Here’s a feedback path,
VOUT
VOUT
VIN
6.004 – Spring 2009
A
0
D
B
1
Not affected
by noise
G D QIN QOUT
Q
Y
Three solutions:
two end-points are stable
middle point is unstable
“state” signal
appears as both
input and output
so it’s no longer a
combinational circuit.
Result: a bistable
storage element
Feedback constraint:
VIN = VOUT
L05 – Sequential Logic 6
Settable Storage Element
IDEA: use positive feedback to maintain storage indefinitely.
Our logic gates are built to restore marginal signal levels, so
noise shouldn’t be a problem!
VTC for
inverter pair
Suppose we refresh
CONTINUOUSLY?
2/19/09
6.004 – Spring 2009
Storage: Using Feedback
VIN
VREF
To write:
Drive bit line, turn on access fet,
force storage cap to new voltage
To read:
precharge bit line, turn on access fet,
detect (small) change in bit line voltage
How can we store – and subsequently access -- a bit?
•
•
•
•
•
Pros:
compact – low cost/bit
(on BIG memories)
Cons:
complex interface
stable? (noise, …)
it leaks! refresh
word line
0
0
1
1
G
S
--0
1
0
1
---
0
1
0
1
Q stable
Q follows D
We’ll get back to this!
2/19/09
L05 – Sequential Logic 7
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 8
New Device: D Latch
A Plea for Lenience…
G=1:
Q follows D
Q’
A
0
D
1
D
Q
Y
V1
G=0:
Q holds
V2
A
Q’
0
D
1
Q
Y
G
G
G
D
Q’
Q
1
0
X
0
1
1
X
1
X
0
0
0
X
1
1
1
0
X
0
0
0
X
1
1
D
V1
G
Q
V1
TPD
G
Q
D
V1
V2
Assume LENIENT Mux, propagation
delay of TPD
Q
TPD
TPD
G
BUT… A change in D or G
contaminates Q, hence Q’
… how can this possibly
work?
G=1: Q Follows D, independently of Q’
G=0: Q Holds stable Q’, independently of D
• Q’=D stable for TPD ,
independently of G; or
Q(D,G)
V2
TPD
Does lenience guarantee a
working latch?
Q(D,Q’)
Q(G,Q’)
What if D and G
change at about the
same time…
• G=0, Q’ stable for TPD ,
independently of D
2/19/09
6.004 – Spring 2009
Then output valid when
• G=1, D stable for TPD,
independently of Q’; or
V2
L05 – Sequential Logic 9
2/19/09
6.004 – Spring 2009
… with a little discipline
L05 – Sequential Logic 10
Lets try it out!
D Stable
Q’
A
0
D
1
Q
Y
G
D
New
State
V2
D
G
Q
G
V2
To reliably latch V2:
TPD TPD
• Apply V2 to D, holding G=1
TPD
Combinational
Logic
Input
Dynamic Discipline for our latch:
• Set G=0, while Q’ & D hold Q=D
TSETUP = 2TPD: interval prior to G
transition for which D must be
stable & valid
• After another TPD, G=0 and Q’
are sufficient to hold Q=V2
independently of D
THOLD = TPD: interval following G
transition for which D must be
stable & valid
6.004 – Spring 2009
Current
State
Output
TSETUP THOLD
• After TPD, V2 appears at Q=Q’
• After another TPD, Q’ & D both valid
for TPD; will hold Q=V2 independently of
G
Q
2/19/09
L05 – Sequential Logic 11
Plan: Build a Sequential Circuit with one bit of STATE –
• Single latch holds CURRENT state
What happens
when G=1?
• Combinational Logic computes
• NEXT state (from input, current state)
• OUTPUT bit (from input, current state)
• State changes when G = 1 (briefly!)
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 12
Flakey Control Systems
Combinational Cycles
New
State
D
G
1
Q
Current
State
Combinational
Logic
Input
Here’s a strategy
for saving 3 bucks
on the Sumner
Tunnel!
Output
Looks like a stupid
Approach to me…
When G=1, latch is Transparent…
… provides a combinational path from D to Q.
Can’t work without tricky timing constrants on G=1 pulse:
Figure by MIT OpenCourseWare.
• Must fit within contamination delay of logic
• Must accommodate latch setup, hold times
Want to signal an INSTANT, not an INTERVAL…
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 13
2/19/09
6.004 – Spring 2009
Escapement Strategy
L05 – Sequential Logic 14
Edge-triggered Flip Flop
The gate of this
latch is open when
the clock is low
The Solution:
Add two gates
and only open
one at a time.
D
D0
1
Q
S
G
What does
that one do?
D
Q
master
G
D
Q
Q
D
D
Q
Q
slave
CLK
G
The gate of this
latch is open when
CLK
the clock is high
Observations:
Transitions mark
only one latch “transparent” at any time:
instants, not intervals
master closed when slave is open
slave closed when master is open
no combinational path through flip flop
(the feedback path in one of the master or slave latches is always active)
Q only changes shortly after 0 1
transition of CLK, so flip flop appears
to be “triggered” by rising edge of CLK
Figure by MIT OpenCourseWare.
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 15
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 16
Flip Flop Waveforms
Um, about that hold time…
The master’s contamination
delay must meet the hold
time of the slave
D
D
Q
master
G
D
Q
Q
D
D
Q
D
Q
Q
D
Q
Q
slave
G
CLK
G
D
master
slave
G
CLK
CLK
Consider HOLD TIME requirement for slave:
D
• Negative (1 0) clock transition slave freezes data:
CLK
• SHOULD be no output glitch, since master held constant data; BUT
• master output contaminated by change in G input!
• HOLD TIME of slave not met, UNLESS we assume sufficient
contamination delay in the path to its D input!
Q
master closed
slave open
Accumulated tCD thru inverter, G Q path of master must cover
slave tHOLD for this design to work!
slave closed
master open
2/19/09
6.004 – Spring 2009
L05 – Sequential Logic 17
2/19/09
6.004 – Spring 2009
Flip Flop Timing - I
Single-clock Synchronous Circuits
<tPD
D
D
Q
>tCD
Q
Does that
symbol
register?
Q
We’ll use Flip Flops and Registers – groups of FFs sharing a clock
input – in a highly constrained way to build digital systems:
Single-clock Synchronous Discipline
CLK
CLK
• No combinational cycles
• Single clock signal shared among
all clocked devices
D
tPD: maximum propagation delay, CLK Q
L05 – Sequential Logic 18
• Only care about value of register data
inputs just before rising edge of clock
>tSETUP >tHOLD
tCD: minimum contamination delay, CLK Q
• Period greater than every
combinational delay
tSETUP: setup time
guarantee that D has propagated through feedback path before master closes
• Change saved state after noiseinducing logic transitions have
stopped!
tHOLD: hold time
guarantee master is closed and data is stable before allowing D to change
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 19
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 20
Flip Flop Timing - II
D
Q
QR1
D
1
reg1
Questions for register-based designs:
how much time for useful work
(i.e. for combinational logic
delay)?
Q
reg2
CLK
t1
does it help to guarantee a
minimum tCD? How ‘bout
designing registers so that
tCD,reg > tHOLD,reg?
t2
tPD,reg1
CLK
tCD,reg1
QR1
tCD, 1
Model: Discrete Time
tPD, 1
New
State
Memory
Device
t2 = tPD,reg1 + tPD,1 < tCLK - tSETUP,reg2
Combinational
Logic
Clock
Input
Output
Active Clock Edges punctuate time ---
what happens if CLK signal
doesn’t arrive at the two
registers at exactly the
same time (a phenomenon
known as “clock skew”)?
t1 = tCD,reg1 + tCD,1 > tHOLD,reg2
Current
State
• Discrete Clock periods
• Discrete State Variables
• Discrete specifications (simple rules – eg tables – relating
outputs to inputs, state variables)
• ABSTRACTION: Finite State Machines (next lecture!)
2/19/09
6.004 – Spring 2009
L05 – Sequential Logic 21
“Sequential” Circuits (with memory):
New
State
Current
State
Combinational
Logic
Clock
tCD,L = ?
tPD,L = 5ns
Input
L05 – Sequential Logic 22
Summary
Sequential Circuit Timing
tCD,R = 1ns
tPD,R = 3ns
tS,R = 2ns
tH,R = 2ns
2/19/09
6.004 – Spring 2009
Output
>ts
Basic memory elements:
• Feedback, detailed analysis => D
basic level-sensitive devices
Clk
(eg, latch)
• 2 Latches => Flop
Q
• Dynamic Discipline:
constraints on input timing
>th
>tcd
<tpd
Synchronous 1-clock logic:
•
Questions:
• Constraints on TCD for the logic?
> 1 ns
• Minimum clock period?
> 10 ns (TPD,R+TPD,L+ TS,R)
• Setup, Hold times for Inputs?
TS = TPD,L +TS,R
TH = TH,R -TCD,L
•
Simple rules for sequential
circuits
Yields clocked circuit with TS, TH
constraints on input timing
In
DQ
Combinational
logic
DQ
Out
Clk
Finite State Machines
Next Lecture Topic!
This is a simple Finite State Machine … more next lecture!!
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 23
6.004 – Spring 2009
2/19/09
L05 – Sequential Logic 24