6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­1
Lecture 26 ­ 6.012 Wrap­up
December 13, 2005
Contents:
1. 6.012 wrap­up
Announcements:
Final exam TA review session: December 16, 7:30­9:30
PM,
Final exam: December 19, 1:30­4:30 PM, duPont; open
book, calculator required; entire subject under examina­
tion but emphasis on lectures #19­26.
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­2
1. Wrap up of 6.012
�The amazing properties of Si
• two types of carriers: electrons and holes
–however, can make good electronic devices with
just one, i.e. MESFET (Metal­Semiconductor Field­
Effect Transistor), or HEMT (High Electron Mo­
bility Transistor)
–but, can’t do complementary logic (i.e. CMOS)
without two
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­3
• carrier concentrations can be controlled by addition
of dopants
– over many orders of magnitude (about 20!)
– and in short length scales (nm range)
Image removed due to copyright restrictions.
37 nm gate length MOSFET from Intel (IEDM ’05).
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­4
• carrier concentrations can be controlled electrostati­
cally over many orders of magnitude (easily 10!)
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­5
• carriers are fast:
– electrons can cross L = 0.1 µm in about:
L
0.1 µm
= 1 ps
τ= = 7
ve 10 cm/s
–high current density:
Je = qnve = 1.6 × 10−19 C × 1017 cm−3 × 107 cm/s
= 1.6 × 105 A/cm2
⇒ high current drivability to capacitance ratio
• extraordinary physical and chemical properties
–can control doping over 8 orders of magnitude (p
type and n type)
–can make very low resistance ohmic contacts
–can effectively isolate devices by means of pn junc­
tions, trenches and SOI
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­6
�The amazing properties of Si MOSFET
body
polysilicon gate
source
drain
gate
n+
p+
n+
n+
p
n
inversion layer�
channel
gate oxide
• ideal properties of Si/SiO2 interface:
–can drive surface all the way from accumulation
to inversion (carrier density modulation over 16
orders of magnitude)
–not possible in GaAs, for example
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­7
• performance improves as MOSFET scales down in
size; as L, W ↓:
– current:
W
µCox (VGS − VT )2 unchanged
2L
– capacitance:
ID =
Cgs = W LCox ↓↓
– figure of merit for device switching delay:
CgsVDD
2VDD
2
=L
↓↓
ID
µ(VGS − VT )2
• No gate current.
• VT can be engineered.
• MOSFETs come in two types: NMOS and PMOS.
• Easy to integrate.
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­8
� The amazing properties of Si CMOS
• Rail­to­rail logic: logic levels are 0 and VDD .
• No power consumption while idling in any logic state.
• Scales well.
As L, W ↓:
– Power consumption (all dynamic):
2
2
Pdiss = f CLVDD
∝ f W LCoxVDD
↓↓
– Propagation delay:
tP ∝
CLVDD
↓↓
W
2
µCox (VDD − VT )
L
–Logic density:
1
1
Density ∝ =
↑↑
A WL
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­9
Cell Area (um2)
100
10
0.57 um2
cell on 65 nm
generation
0.5x every
2 years
1
0.1
1993 1995
1997
1999
2001
2003
2005
Transistor density continues to double every 2 years
INTEL 6-T SRAM CELL SIZE TREND
Figure by MIT OCW.
2007
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­10
Transistors
1,000,000,000
Itanium R 2 Processor
Itanium R Processor
100,000,000
Pentium R 4 Processor
Pentium R III Processor
Pentium R II Processor
10,000,000
Pentium R Processor
286
8086
8008
486TM DX Processor
386TM Processor
100,000
10,000
8080
4004
1970
1975
1,000,000
1980
1985
1990
1995
MOORE'S LAW
Figure by MIT OCW.
2000
1,000
2005
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­11
� MOSFET scaling
Straight MOSFET scaling doesn’t work.
• electric field increases
Ey �
VDD
↑
L
• power density increases
2
Pdiss
f W LCoxVDD
2
= f CoxVDD
∝
device area
WL
But
Pdiss
↑↑⇒ T ↑↑
tP ↓↓⇒ f ↑↑⇒
device area
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­12
• total power increases
Power (watts)
100
10
0
1985 1987 1989 1991 1993 1995 1997 1999 2001 2003
Year
INTEL POWER OVER TIME
Figure by MIT OCW.
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
⇒ must scale VDD
Lecture 26­13
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Where is this going?
Image removed due to copyright restrictions.
Lecture 26­14
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­15
The future of microelectronics according to Intel:
Image removed due to copyright restrictions.
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­16
� Exciting times ahead in Si IC technology:
• analog electronics (since ∼ 50� s): amplifiers, mixers,
oscillators, DAC, ADC, etc.
• digital electronics (since ∼ 60� s): computers, micro­
controllers, random logic, DSP
• solid­state memory (since ∼ 60� s): dynamic random­
access memory, flash
• energy conversion (since ∼ 70� s): solar cells
• power control (since ∼ 70� s): ”smart” power
• communications (since ∼ 80� s): VHF, UHF, RF
front ends, modems, fiber­optic systems
• sensing, imaging (since ∼ 80� s): photodetectors, CCD
cameras, CMOS cameras, many kinds of sensors
• micro­electro­mechanical systems (since ∼ 90� s): ac­
celerometers, movable mirror displays
• biochip (from ∼ 2000): DNA sequencing, µfluidics
• vacuum microelectronics (from ∼ 2000?): field­emitter
displays
• ??????? (microreactors, microturbines, etc.)
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­17
� Circuit design lessons from 6.012:
1. Importance of optimum level of abstraction:
• device physics equations, i.e.:
W
µCox (VGS − VT )2 , etc.
ID =
2L
• device equivalent circuit models, i.e.:
id
Cgd
G
D
+
vgs
Cgs
Cgb
gmbvbs
gmvgs
ro
-
S
-
vbs
B
Csb
+
Cdb
• device SPICE models, i.e.:
drain
− qBD+
ID
RD
+ qGD−
−
D′
vGD′
gate
+
− vBD′ +
IS
IDS(VGS,VDS,VBS)
+ qGS−
S′
+ qGB−
IS
− vBS' +
RS
− qBS+
source
bulk
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­18
2. Many considerations in circuit design:
• multiple performance specs:
–in analog systems: gain, bandwidth, power con­
sumption, swing, noise, etc.
–in digital systems: propagation delay, power, ease
of logic synthesis, noise, etc.
• need to be immune to temperature variations and de­
vice parameter variations (i.e.: differential amplifier)
• must choose suitable technology: CMOS, BJT, CBJT,
BiCMOS, etc.
• must avoid costly components (i.e.: resistors, capac­
itors)
3. Trade­offs:
• gain­bandwidth trade­off in amplifiers (i.e.: Miller ef­
fect)
• performance­power trade­off (i.e.: delay in logic cir­
cuits, gain in amplifiers)
• performance­cost trade­off (cost=design complexity,
Si area, more aggressive technology)
• accuracy­complexity trade­off in modeling
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­19
� Exciting times ahead in circuit design too:
• Numbers of transistors available outstrips ability to
design by 3 to 1!
• Operational frequency of logic, analog, and communi­
cations circuits increasing very fast.
• Operational voltage shrinking quickly.
• New device technologies: GaAs HEMT, InP HBT,
GaN HEMT, etc
6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005
Lecture 26­20
More subjects in microelectronics at MIT
• 6.152J ­ Micro/Nano Processing Technology. The­
ory and practice of IC technology. Carried out in
clean rooms of Microsystems Technology Laborato­
ries. Fulfills Institute or EECS Lab requirement. Fall
and Spring.
• 6.301 ­ Solid­State Circuits. Analog circuit design.
Design project. Spring. G­level.
• 6.334 ­ Power Electronics. Power electronics devices
and circuits. Spring. H­level.
• 6.374 ­ Analysis and Design of Digital Integrated
Circuits. Digital circuit design. Design projects. Fall.
H­level.
• 6.720J ­ Integrated Microelectronic Devices. Mi­
croelectronic device physics and design. Emphasis on
MOSFET. Design project. Fall. H­level.