6.976
High Speed Communication Circuits and Systems
Lecture 21
MSK Modulation and
Clock and Data Recovery Circuits
Michael Perrott
Massachusetts Institute of Technology
Copyright © 2003 by Michael H. Perrott
Recall Constant Envelope Modulation from Lecture 19
Baseband
Input
Baseband to RF Modulation
Power Amp
Transmit
Filter
Transmitter
Output
Constant-Envelope Modulation
ƒ
Popular for cell phones and cordless phones due to
the reduced linearity requirements on the power amp
- Allows a more efficient power amp design
ƒ Transmitter power is reduced
M.H. Perrott
MIT OCW
Frequency Shift Keying
data(t)
Transmit
Filter
v(t)
out(t)
Assume infinite bandwidth
in this example
1
data(t)
-1
out(t)
Sout(f)
2∆f
out(t)
fo
ƒ
GHz
Sends information encoded in instantaneous frequency
- Can build simple transmitters and receivers
ƒ Pagers use this modulation method
ƒ
Issue – want to obtain high spectral efficiency
- Need to choose an appropriate transmit filter
- Need to choose an appropriate value of ∆f
M.H. Perrott
MIT OCW
Transmit Filter Selection
Sa(f)
cos(Φmod(t))
SΦmod(f)
it(t)
0
Φmod(t)
0
sin(Φmod(t))
ƒ
y(t)
sin(2πf2t)
-fo
qt(t)
0
ƒ
cos(2πf2t)
Sb(f)
f
Sy(f)
f
0
fo
f
f
Recall from Lecture 19 that output spectrum is related
in a nonlinear manner to transmit filter
- Raised cosine filter is not necessarily the best choice
We’ll come back to this issue
- Focus instead on choosing ∆f
M.H. Perrott
MIT OCW
A More Detailed Model
Assume DC gain = 1
data(t)
h
2Td
Transmit fmod(t)
2π
Filter
Φmod(t)
Td
Td
1
-1
cos(Φmod(t))
sin(Φmod(t))
h
2Td
for infinite
transmit filter
bandwidth
I(t)
h
2Td
Q(t)
Td
hπ
ƒ
By inspection of figure
ƒ
The choice of ∆f is now parameterized by h and Td
- h is called the modulation index, T
d
M.H. Perrott
is symbol period
MIT OCW
MSK Modulation
Q
I
ƒ
Choose h such that the phase rotates ± 90o each
symbol period
- Based on previous slide, we need h = 1/2
- Note: 1-bit of information per symbol period
ƒ Bit rate = symbol rate
M.H. Perrott
MIT OCW
A More Convenient Model for Analysis
Assume DC gain = 1
cos(Φmod(t))
Td
x(t)
data(t)
1
0
h
2Td
Transmit fmod(t)
2π
Filter
sin(Φmod(t))
h
2Td
1
-1
Φmod(t)
Td
Td
for infinite
transmit filter
bandwidth
h
2Td
I(t)
Q(t)
Td
hπ
ƒ
Same as previous model, but we represent data as
impulses convolved with a rectangular pulse
- Note that h = 1/2 for MSK
M.H. Perrott
MIT OCW
Impact of Sending a Single Data Impulse
Assume DC gain = 1
cos(Φmod(t))
Td
x(t)
data(t)
1
0
1
4Td
Transmit fmod(t)
2π
Filter
sin(Φmod(t))
1
4Td
0
1
-1
Φmod(t)
Td
Td
for infinite
transmit filter
bandwidth
I(t)
Q(t)
Td
π/2
ƒ
To achieve MSK modulation, resulting phase shift
must be ± 90o (i.e., π/4)
M.H. Perrott
MIT OCW
Include Influence of Transmit Filter
rect(Td,t)
Td
x(t)
cos(Φmod(t))
p(t)
data(t)
1
0
1
4Td
Transmit fmod(t)
2π
Filter
sin(Φmod(t))
1
4Td
0
1
-1
Φmod(t)
Td
Td
Transmit filter
bandwidth = B Hz
I(t)
Q(t)
Td
π/2
ƒ
For MSK modulation
- Where * denotes convolution
M.H. Perrott
MIT OCW
Gaussian Minimum Shift Keying
ƒ
Definition
- Minimum shift keying in which the transmit filter is chosen
to have a Gaussian shape (in time and frequency) with
bandwidth = B Hz
ƒ
Key parameters
- Modulation index: as previously discussed
ƒ h = 1/2
- BT product: ratio of transmit filter bandwidth to data rate
d
ƒ For GSM phones: BTd = 0.3
M.H. Perrott
MIT OCW
Project 2
ƒ
ƒ
Simulate a GMSK transmitter and receiver
What you’ll learn
- How GMSK works at the system level
- Behavioral level simulation of a communication system
- Generation of eye diagrams and spectral plots
- Analysis and simulation of discrete-time version of loop
filter and other signals
ƒ
Note: you’ll also be exposed a little to GFSK
modulation
- Popular for cordless phones
- Similar as GMSK, but frequency is the important variable
rather than phase
ƒ Typical GFSK specs: h = 0.5 ± 0.05, BTd = 0.5
M.H. Perrott
MIT OCW
High Speed Data Links
Zin
From Broadband
Transmitter
PC board
trace
Zo
Data
Package
Interface
In
Amp
Clock and
Data
Recovery
Clk
Data Out
Data In
Phase
Detector
Clk Out
Loop
Filter
VCO
ƒ
A challenging component is the clock and data
recovery circuit (CDR)
- Two primary functions
ƒ Extract the clock corresponding to the input data signal
ƒ Resample the input data
M.H. Perrott
MIT OCW
PLL Based Clock and Data Recovery
retimed
data(t)
data(t)
PD
e(t) Charge
Pump
Loop
Filter
v(t)
clk(t)
VCO
ƒ
ƒ
Use a phase locked loop to tune the frequency and
phase of a VCO to match that of the input data
Performance issues
ƒ
Let’s focus on specifications for OC-192
- Jitter
- Acquisition time
- Bit error rate (at given input levels)
- i.e., 10 Gbit/s SONET
M.H. Perrott
MIT OCW
Jitter Generation
retimed
data(t)
data(t)
PD
e(t) Charge
Pump
Loop
Filter
v(t)
clk(t)
VCO
ƒ
Definition
- The amount of jitter at the output of the CDR when no
jitter (i.e., negligible jitter) is present on the data input
ƒ
SONET requires
ƒ
Note: UI is unit interval, and is defined as the period
of the clk signal (i.e., 100 ps for 10 Gbit/s data rates)
- < 10 mUI rms jitter
- < 100 mUI peak-to-peak jitter
M.H. Perrott
MIT OCW
Jitter Tolerance
retimed
data(t)
data(t)
PD
e(t) Charge
Pump
Loop
Filter
v(t)
clk(t)
VCO
ƒ
Definition
- The maximum amount of jitter allowed on the input while
still achieving low bit error rates (< 10e-12)
ƒ
SONET specifies jitter tolerance according to the
frequency of the jitter
- Low frequency jitter can be large since it is tracked by PLL
- High frequency jitter (above the PLL bandwidth) cannot be
as high (PLL can’t track it out)
ƒ Limited by setup and hold times of PD retiming register
M.H. Perrott
MIT OCW
Example Jitter Tolerance Mask
Jitter Tolerance U.I.
OC -192 Jitter Tolerance Mask
15 UI
Acceptable
Region
1.5 UI
0.15 UI
2.4 kHz
24 kHz
400 kHz
4 MHz
100 MHz
Jitter Frequency (Hz)
ƒ
CDR tested for tolerance compliance by adding sine wave
jitter at various frequencies (with amplitude greater than
mask) to the data input and observing bit error rate
M.H. Perrott
MIT OCW
Jitter Transfer
retimed
data(t)
data(t)
PD
e(t) Charge
Pump
Loop
Filter
v(t)
clk(t)
VCO
ƒ
Definition
- The amount of jitter attenuation that the CDR provides
from input to output
ƒ
SONET specifies jitter transfer by placing limits on its
transfer function behavior from input to output
- Peaking behavior: low frequency portion of CDR transfer
function must be less than 0.1 dB
- Attenuation behavior: high frequency portion of CDR
transfer function must not exceed a mask limit
M.H. Perrott
MIT OCW
Example Jitter Transfer Mask
OC-192 Jitter Transfer Mask
0.1
-5
Maximum Allowed "Peaking" = 0.1 dB
Magnitude (dB)
-10
-15
Acceptable
Region
-20
-25
-30
-35
10 kHz
100 kHz
1 MHz
8 MHz
100 MHz
Frequency (Hz)
ƒ
CDR tested for compliance by adding sine wave jitter
at various frequencies and observing the resulting
jitter at the CDR output
M.H. Perrott
MIT OCW
Summary of CDR Performance Specifications
ƒ
Jitter
ƒ
Acquisition time
ƒ
Bit error rates
- Jitter generation
- Jitter tolerance
- Jitter transfer (and peaking)
- Must be less than 10 ms for many SONET systems
- Must be less than 10e-12 for many SONET systems
M.H. Perrott
MIT OCW
Phase Detectors in Clock and Data Recovery Circuits
retimed
data(t)
data(t)
PD
e(t) Charge
Pump
Loop
Filter
v(t)
clk(t)
VCO
ƒ
Key issue
- Must accommodate “missing” transition edges in input
data sequence
ƒ
Two styles of detection
- Linear – PLL can analyzed in a similar manner as
frequency synthesizers
- Nonlinear – PLL operates as a bang-bang control
system (hard to rigorously analyze in many cases)
M.H. Perrott
MIT OCW
Popular CDR Phase Detectors
Hogge Detector (Linear)
Bang-Bang Detector (Nonlinear)
e(t)
data(t)
Reg
Reg
D
D
Q
retimed
data(t)
Q
clk(t)
data(t)
Reg
Latch retimed
data(t)
Reg
Latch
D
D
D
D
clk(t)
ƒ
e(t)
Q
Q
Q
Q
clk(t)
Linear
- Hogge detector produces an error signal that is
proportional to the instantaneous phase error
ƒ
Nonlinear
- Alexander (Bang-bang) detector produces an error signal
that corresponds to the sign of the instantaneous phase
error
M.H. Perrott
MIT OCW
A Closer Look at the Hogge Detector
Hogge Detector (Linear)
e(t)
B
C
data(t)
clk(t)
A(t)
retimed data(t)
A
data(t)
Reg
Latch retimed
data(t)
D
D
Q
C(t)
Q
e(t)
clk(t)
ƒ
B(t)
1
0
-1
Error output, e(t), consists of two pulses with
opposite polarity
- Positive polarity pulse has an area that is proportional
to the phase error between the data and clk
- Negative polarity pulse has a fixed area corresponding
to half of the clk period
- Overall area is zero when data edge is aligned to falling
M.H. Perrott
clk edge
MIT OCW
Example CDR Settling Characteristic with Hogge PD
Instantaneous Phase Error vs Time for CDR 1 (Hogge Detector)
(Steady-State RMS Jitter = 3.0756 mUI)
Instantaneous Phase Error (UI)
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
ƒ
ƒ
0
4
8
12
16
20
24
28
32
36
CDR tracks out phase error with an exponential
transition response
Jitter occuring at steady state is due to VCO and
non-idealities of phase detector
M.H. Perrott
MIT OCW
Modeling of CDR with Hogge Detector
Hogge Detector
Phase
Sampler
Φdata(t)
α
Charge
Pump
1
e(t)
π
Icp
i(t)
Loop
Filter
H(s)
VCO
v(t)
2πKv
s
Φout(t)
α = transition density
0 < α < 1, = 1/2
for PRBS input
ƒ
Similar to frequency synthesizer model except
- No divider
- Phase detector gain depends on the transition density
of the input data
ƒ
The issue of transition density
- Phase error information of the input data signal is only
-
M.H. Perrott
seen when it transitions
ƒ VCO can wander in the absence of transitions
Open loop gain (and therefore the closed loop
bandwidth) is decreased at low transition densities
MIT OCW
A Common Loop Filter Implementation
Hogge Detector
Phase
Sampler
Φdata(t)
α
Charge
Pump
e(t)
1
π
Icp
i(t)
Loop
Filter
H(s)
VCO
v(t)
2πKv
s
Φout(t)
α = transition density
0 < α < 1, = 1/2
for PRBS input
i(t)
v(t)
C1
H(s) =
ƒ
R1
C2
C|| =
C 1C 2
C1+C2
1+sR1C2
1+s/wz
1
=
s(C1+C2) 1+sR1C||
sCtot(1+s/wp)
Use a lead/lag filter to implement a type II loop
- Integrator in H(s) forces the steady-state phase error to
zero (important to minimize jitter)
M.H. Perrott
MIT OCW
Open Loop Response and Closed Loop Pole/Zeros
Evaluation of
Phase Margin
Closed Loop Pole
Locations of G(f)
Im{s}
Open loop
gain
increased
20log|A(f)|
C
B
0 dB
fz
f
fp
Non-dominant
pole
C
B
A
ƒ
o
-160
o
-180
o
BC
A
o
-140
A
Re{s}
angle(A(f))
120
Dominant
pole pair
PM = 54oo for B
PM = 53 for A
PM = 55o for C
0
A
B
C
Key issue: an undesired pole/zero pair occurs due to
stabilizing zero in the lead/lag filter
M.H. Perrott
MIT OCW
Corresponding Closed Loop Frequency Response
|G(w)|
Peaking caused by
undesired pole/zero pair
wcp wz
1
0
ƒ
ƒ
wz
wo
Frequency (rad/s)
w
Undesired pole/zero pair causes peaking in the closed
loop frequency response
SONET demands that peaking must be less than 0.1 dB
- For classical lead/lag filter approach, this must be achieved
by having a very low-valued zero
ƒ Requires a large loop filter capacitor
M.H. Perrott
MIT OCW
An Interesting Observation
X(s)
NA(s)
DA(s)
Y(s)
NB(s)
DB(s)
ƒ
Calculation of closed loop transfer function
ƒ
Key observation
- Zeros in feedback loop do not appear as zeros in the
overall closed loop transfer function!
M.H. Perrott
MIT OCW
Method of Achieving Zero Peaking
retimed
data(t)
data(t)
PD
e(t) Charge
Pump
Loop
Filter
v(t)
clk(t)
VCO
Adjustable
Delay Element
ƒ
ƒ
ƒ
We can implement a stabilizing zero in the PLL feedback
path by using a variable delay element
- Loop filter can now be implemented as a simple integrator
Issue: delay must support a large range
See T.H. Lee and J.F. Bulzacchelli, “A 155-MHz Clock
Recovery Delay- and Phase-Locked Loop”, JSSC, Dec
1992
M.H. Perrott
MIT OCW
Model of CDR with Delay Element
Hogge Detector
Phase
Sampler
Φdata(t)
α
Charge
Pump
1
e(t)
π
α = transition density
0 < α < 1, = 1/2
for PRBS input
Icp
i(t)
Loop
Filter
H(s)
VCO
v(t)
Kd
2πKv
s
Φout(t)
Note: Kv units
are Hz/V
Note: Kd units
are radians/V
ƒ
ƒ
Delay “gain”, Kd, is set by delay implementation
Note that H(s) can be implemented as a simple
capacitor
- H(s) = 1/(sC)
M.H. Perrott
MIT OCW
Derivation of Zero Produced by Delay Element
Hogge Detector
Phase
Sampler
Φdata(t)
α
Charge
Pump
1
e(t)
π
Icp
i(t)
Loop
Filter
H(s)
α = transition density
0 < α < 1, = 1/2
for PRBS input
VCO
v(t)
2πKv
s
Kd
Φout(t)
Note: Kv units
are Hz/V
Note: Kd units
are radians/V
i(t)
Loop
Filter
H(s)
VCO
v(t)
2πKv
s
Φout(t)
i(t)
Loop
Filter
H(s)
VCO
v(t)
2πKv
s
Φout(t)
s
K
2πKv d
Kd
1+ 2πK s
v
ƒ
Zero set by ratio of delay gain to VCO gain
M.H. Perrott
MIT OCW
Alternate Implementation
retimed
data(t)
data(t)
PD
e(t) Charge
Pump
Loop
Filter
Adjustable
Delay Element
v(t)
clk(t)
VCO
-1
ƒ
Can delay data rather than clk
- Same analysis as before
M.H. Perrott
MIT OCW
The Issue of Data Dependent Jitter
retimed
data(t)
Φclk(t)
data(t)
PD
e(t) Charge
Pump
Loop
Filter
v(t)
clk(t)
VCO
ƒ
For classical or Bulzacchelli CDR
- Type II PLL dynamics are employed so that steady state
phase detector error is zero
ƒ
Issue: phase detector output influences VCO phase
through a double integrator operation
- The classical Hogge detector ends up creating data
dependent jitter at the VCO output
M.H. Perrott
MIT OCW
Culprit Behind Data Dependent Jitter for Hogge PD
Hogge Detector (Linear)
data(t)
clk(t)
A(t)
e(t)
B
C
retimed data(t)
B(t)
C(t)
A
data(t)
clk(t)
ƒ
Reg
Latch retimed
data(t)
D
D
Q
e(t)
1
0
-1
e(t)
0
Q
The double integral of the e(t) pulse sequence is
nonzero (i.e., has DC content)
- Since the data transition activity is random, a low
M.H. Perrott
frequency noise source is created
ƒ Low frequency noise not attenuated by PLL dynamics
MIT OCW
One Possible Fix
Hogge Detector (Linear)
data(t)
e(t)
clk(t)
A(t)
retimed data(t)
2
B
C
B(t)
D
C(t)
D(t)
A
data(t)
clk(t)
ƒ
ƒ
Reg
Latch
Latch
D
D
D
Q
Q
retimed
data(t)
e(t)
1
0
Q
-2
e(t)
0
Modify Hogge so that the double integral of the e(t)
pulse sequence is zero
- Low frequency noise is now removed
See L. Devito et. al., “A 52 MHz and 155 MHz Clockrecovery PLL”, ISSCC, Feb, 1991
M.H. Perrott
MIT OCW
A Closer Look at the Bang-Bang Detector
Bang-Bang Detector (Nonlinear)
data(t)
Reg
D
Q
A
retimed
data(t)
Reg
D
Q
C
e(t)
clk(t)
data(t)
clk(t)
A(t)
retimed data(t)
B(t)
C(t)
clk(t)
ƒ
ƒ
Reg
Latch
D
D
Q
Q
D
B
D(t)
e(t)
1
0
-1
Error output consists of pulses of fixed area that are
either positive or negative depending on phase error
Pulses occur at data edges
- Data edges detected when sampled data sequence is
different than its previous value
ƒ
Above example illustrates the impact of having the
data edge lagging the clock edge
M.H. Perrott
MIT OCW
A Closer Look at the Bang-Bang Detector (continued)
Bang-Bang Detector (Nonlinear)
data(t)
Reg
D
Q
A
retimed
data(t)
Reg
D
Q
C
e(t)
clk(t)
data(t)
clk(t)
A(t)
retimed data(t)
B(t)
C(t)
clk(t)
ƒ
Reg
Latch
D
D
Q
Q
D
B
D(t)
e(t)
1
0
-1
Above example illustrates the impact of having the
data edge leading the clk edge
- Error pulses have opposite sign from lagging edge case
M.H. Perrott
MIT OCW
Example CDR Settling Characteristic with Bang-Bang PD
Instantaneous Phase Error (UI)
0.05
Instantaneous Phase Error vs Time for CDR 2 (Bang-Bang Detector)
(Steady-State RMS Jitter = 3.4598 mUI)
0
-0.05
-0.1
-0.15
-0.2
0
2
4
6
8
10
12
Time (Micro Seconds)
14
16
18
20
ƒ
Bang-bang CDR response is slew rate limited
ƒ
Steady-state jitter often dominated by bang-bang
behavior (jitter set by error step size and limit cycles)
- Much faster than linear CDR, in general
M.H. Perrott
MIT OCW
The Issue of Limit Cycles
Bang-Bang Style
Phase Detector
data(t)
Sense
e(t)
Φclk(t)
Drive
v(t)
clk(t)
VCO
v(t)
Φclk(t)
e(t)
ƒ
Bang-bang loops exhibit limit cycles during steadystate operation
- Above diagram shows resulting waveforms when data
transitions on every cycle
- Signal patterns more complicated for data that randomly
transitions
ƒ
For lowest jitter: want to minimize period of limit cycles
M.H. Perrott
MIT OCW
The Impact of Delays in a Bang-Bang Loop
Bang-Bang Style
Phase Detector
data(t)
Sense
e(t)
Delay
Φclk(t)
Drive
v(t)
clk(t)
VCO
v(t)
Φclk(t)
e(t)
v(t)
Φclk(t)
e(t)
ƒ
Delays increase the period of limit cycles, thereby
increasing jitter
M.H. Perrott
MIT OCW
Practical Implementation Issues for Bang-Bang Loops
ƒ
Minimize limit cycle periods
- Use phase detector with minimal delay to error output
- Implement a high bandwidth feedforward path in loop
filter
ƒ One possibility is to realize feedforward path in VCO
ƒ See B. Lai and R.C Walker, “A Monolithic 622 Mb/s Clock
Extraction Data Retiming Circuit”, ISSCC, Feb 1991
ƒ
Avoid dead zones in phase detector
- Cause VCO phase to wonder within the dead zone,
thereby increasing jitter
ƒ
Use simulation to examine system behavior
- Nonlinear dynamics can be non-intuitive
- For first order analysis, see R.C. Walter et. al., “A TwoChip 1.5-GBd Serial Link Interface”, JSSC, Dec 1992
M.H. Perrott
MIT OCW
Delay-Locked Loops
Clock and Data
arrive misaligned
in phase
data(t)
Adjustable
Delay Element
clk(t)
ƒ
PD
e(t) Charge
Pump
Clock and Data
are now re-aligned
in phase
retimed
data(t)
Loop v(t)
Filter
adjusted
clk(t)
In some applications you have a reference clock that
is perfectly matched in frequency to data sequence
- Phase mismatch is present due to different propagation
delays between clock and data on the PC board
ƒ
A delay-locked loop limits adjustment to phase (as
opposed to phase and frequency)
- Faster, and much simpler to design than PLL structure
M.H. Perrott
MIT OCW
Some References on CDR’s and Delay-Locked Loops
ƒ
ƒ
Gu-Yeon Wei will discuss DLL’s in his guest lecture
Tom Lee has a nice paper
- See T. Lee et. al., “A 2.5 V CMOS Delay-Locked Loop for an
18 Mbit, 500 Megabyte/s DRAM”, JSSC, Dec 1994
ƒ
Check out papers from Mark Horowitz’s group at Stanford
- Oversampling data recovery approach
-
M.H. Perrott
ƒ See C-K K. Yang et. al., “A 0.5-um CMOS 4.0-Gbit/s Serial
Link Transceiver with Data Recovery using Oversampling”,
JSSC, May 1998
Multi-level signaling
ƒ See Ramin Farjad-Rad et. al., “A 0.3-um CMOS 8-Gb/s 4PAM Serial Link Transceiver”, JSSC, May 2000
Bi-directional signaling
ƒ See E. Yeung, “A 2.4 Gb/s/pin simultaneous bidirectional
parallel link …”, JSSC, Nov 2000
MIT OCW