6.976
High Speed Communication Circuits and Systems
Lecture 15
Integer-N Frequency Synthesizers
Michael Perrott
Massachusetts Institute of Technology
Copyright © 2003 by Michael H. Perrott
Integer-N Frequency Synthesizers in Wireless Systems
Zin
From Antenna
and Bandpass
Filter
PC board
trace
Zo
RF in
Package
Interface
Mixer
IF out
To Filter
LNA
LO signal
VCO
Reference ref(t) Frequency v(t)
Frequency
Synthesizer
ref(t)
e(t) Charge
PFD
Pump
out(t)
Loop
Filter
v(t)
out(t)
VCO
div(t)
Divider
N
ƒ
Design Issues: low noise, fast settling time, low power
M.H. Perrott
MIT OCW
Overview of Integer-N Frequency Synthesizer
ref(t)
PFD
e(t)
Loop
Filter
v(t)
out(t)
VCO
div(t)
Divider
N
ƒ
VCO
M.H. Perrott
produces high frequency sine wave
MIT OCW
Overview of Integer-N Frequency Synthesizer
ref(t)
PFD
e(t)
Loop
Filter
v(t)
out(t)
VCO
div(t)
Divider
N
ƒ
ƒ
VCO
Divider
M.H. Perrott
produces high frequency sine wave
divides down VCO frequency
MIT OCW
Overview of Integer-N Frequency Synthesizer
ref(t)
PFD
e(t)
Loop
Filter
v(t)
out(t)
VCO
div(t)
Divider
N
ƒ
ƒ
ƒ
VCO
Divider
PFD
M.H. Perrott
produces high frequency sine wave
divides down VCO frequency
compares phase of ref and div
MIT OCW
Overview of Integer-N Frequency Synthesizer
ref(t)
PFD
e(t)
Loop
Filter
v(t)
out(t)
VCO
div(t)
Divider
N
ƒ
ƒ
ƒ
ƒ
VCO
Divider
PFD
Loop filter
M.H. Perrott
produces high frequency sine wave
divides down VCO frequency
compares phase of ref and div
smooths phase error signal
MIT OCW
Overview of Integer-N Frequency Synthesizer
Fref
ref(t)
Fout = N Fref
PFD
e(t)
Loop
Filter
v(t)
out(t)
VCO
div(t)
Divider
N
ƒ
ƒ
ƒ
ƒ
VCO
Divider
PFD
Loop filter
produces high frequency sine wave
divides down VCO frequency
compares phase of ref and div
smooths phase error signal
VCO frequency locks to ref. frequency multiplied by N
M.H. Perrott
MIT OCW
Popular VCO Structures
LC oscillator
VCO Amp
-Ramp
Vout
C
Vin
L
Rp
Ring oscillator
Vout
Vin
ƒ
ƒ
-1
LC Oscillator: low phase noise, large area
Ring Oscillator: easy to integrate, higher phase noise
M.H. Perrott
MIT OCW
Model for Voltage to Frequency Mapping of VCO
LC oscillator
VCO Amp
-Ramp
Vout
C
Vin
L
Rp
Fvco
Ring oscillator
Vout
Vin
-1
VCO
Frequency
fc
Fout
slope=Kv
v
vin
Vbias
Input Voltage
M.H. Perrott
MIT OCW
Model for Voltage to Phase Mapping of VCO
ƒ
Time-domain frequency relationship (from previous
slide)
ƒ
Time-domain phase relationship
ƒ
Intuition of integral relationship between frequency and
phase:
1/Fvco= α
out(t)
out(t)
M.H. Perrott
1/Fvco= α+ε
MIT OCW
Frequency-Domain Model for VCO
ƒ
Time-domain relationship (from previous slide)
ƒ
Corresponding frequency-domain model
Laplace-Domain
v(t)
out(t)
VCO
M.H. Perrott
v(t)
2πKv
s
VCO
Φout(t)
Frequency-Domain
v(t)
Kv
jf
Φout(t)
VCO
MIT OCW
Divider
ƒ
Implementation
N
Counter
count value
out
div(t)
out(t)
out(t)
div(t)
ƒ
Time-domain model
N=6
- Frequency:
- Phase:
M.H. Perrott
MIT OCW
Frequency-Domain Model of Divider
ƒ
Time-domain relationship between VCO phase and
divider output phase (from previous slide)
ƒ
Corresponding frequency-domain model (same as
Laplace-domain)
out(t)
Divider
div(t)
Φout(t)
1
N
Φdiv(t)
Divider
M.H. Perrott
MIT OCW
Phase Detector (PD)
ƒ
XOR structure
- Average value of error pulses corresponds to phase error
- Loop filter extracts the average value and feeds to VCO
ref(t)
e(t)
div(t)
ref(t)
div(t)
e(t)
1
-1
M.H. Perrott
MIT OCW
Modeling of XOR Phase Detector
ƒ
Average value of pulses is extracted by loop filter
- Look at detector output over one cycle:
W
1
e(t)
-1
T/2
ƒ
Equation:
M.H. Perrott
MIT OCW
Relate Pulse Width to Phase Error
ƒ
Two cases:
0 < Φref − Φdiv < π
−π < Φref − Φdiv < 0
T/2
T/2
ref(t)
ref(t)
div(t)
div(t)
e(t)
1
e(t)
-1
1
-1
W
W=-
M.H. Perrott
Φref − Φdiv
T/2
π
W
W=
Φref − Φdiv
T/2
π
MIT OCW
Overall XOR Phase Detector Characteristic
0 < Φref − Φdiv < π
−π < Φref − Φdiv < 0
T/2
T/2
ref(t)
ref(t)
div(t)
div(t)
e(t)
1
e(t)
-1
1
-1
W
W=-
W
Φref − Φdiv
T/2
π
W=
Φref − Φdiv
T/2
π
avg{e(t)}
gain = -2/π
−π
gain = 2/π
1
−π/2
0
π/2
π
Φref - Φdiv
-1
phase detector
range = π
M.H. Perrott
MIT OCW
Frequency-Domain Model of XOR Phase Detector
ƒ
Assume phase difference confined within 0 to π radians
- Phase detector characteristic looks like a constant gain
element
avg{e(t)}
gain = -2/π
−π
gain = 2/π
1
−π/2
0
π/2
Φref - Φdiv
π
-1
ƒ
Corresponding frequency-domain model
ref(t)
PD
div(t)
M.H. Perrott
e(t)
Φref(t)
Φdiv(t)
2
π
e(t)
PD gain
MIT OCW
Loop Filter
ƒ
ƒ
Consists of a lowpass filter to extract average of
phase detector error pulses
Frequency-domain model
Laplace-Domain
e(t)
Loop
Filter
v(t)
e(t)
H(s)
e(t)
H(f)
v(t)
H(s)
VCO
ƒ
v(t)
Frequency-Domain
VCO
First order example
e(t)
R1
v(t)
C1
M.H. Perrott
MIT OCW
Overall Linearized PLL Frequency-Domain Model
ƒ
Combine models of individual components
Laplace-Domain Model
XOR PD
Φref(t)
Loop Filter
2
π
e(t)
H(s)
VCO
v(t)
2πKv
s
Φout(t)
Divider
Φdiv(t)
1
N
Frequency-Domain Model
XOR PD
Φref(t)
Φdiv(t)
M.H. Perrott
Loop Filter
2
π
e(t)
H(f)
VCO
v(t)
Kv
jf
Φout(t)
Divider
1
N
MIT OCW
Open Loop versus Closed Loop Response
ƒ
Frequency-domain model
XOR PD
Φref(t)
Φdiv(t)
Loop Filter
2
π
e(t)
H(f)
VCO
v(t)
Kv
jf
Φout(t)
Divider
1
N
ƒ
Define A(f) as open loop response
ƒ
Define G(f) as a parameterizing function (related to
closed loop response)
M.H. Perrott
MIT OCW
Classical PLL Transfer Function Design Approach
1. Choose an appropriate topology for H(f)
ƒ
Usually chosen from a small set of possibilities
2. Choose pole/zero values for H(f) as appropriate for
the required filtering of the phase detector output
ƒ
Constraint: set pole/zero locations higher than
desired PLL bandwidth to allow stable dynamics to
be possible
3. Adjust the open-loop gain to achieve the required
bandwidth while maintaining stability
ƒ
ƒ
M.H. Perrott
Plot gain and phase bode plots of A(f)
Use phase (or gain) margin criterion to infer stability
MIT OCW
Example: First Order Loop Filter
ƒ
Overall PLL block diagram
XOR PD
Φref(t)
Loop Filter
2
π
H(f)
v(t)
Kv
jf
Φout(t)
Divider
Φdiv(t)
ƒ
e(t)
VCO
1
N
Loop filter
e(t)
R1
v(t)
C1
M.H. Perrott
MIT OCW
Closed Loop Poles Versus Open Loop Gain
Evaluation of
Phase Margin
Closed Loop Pole
Locations of G(f)
20log|A(f)|
Open loop
gain
increased
C
Dominant
pole pair
0 dB
B
f
fp
angle(A(f))
Im{s}
A
C
B
A
Re{s}
0
o
-90
A
-120o
PM = 59o for A
PM = 45o for B
-150o
-180o
ƒ
PM = 33o for C
B
C
Higher open loop gain leads to an increase in Q of
closed loop poles
M.H. Perrott
MIT OCW
Corresponding Closed Loop Response
Step Response of G(f)
Frequency Response of G(f)
1.4
C
5 dB
0 dB
C
B
-5 dB
B
A
A
1
0.6
fp
ƒ
f
0
t
Increase in open loop gain leads to
- Peaking in closed loop frequency response
- Ringing in closed loop step response
M.H. Perrott
MIT OCW
The Impact of Parasitic Poles
ƒ
ƒ
ƒ
Loop filter and VCO may have additional parasitic
poles and zeros due to their circuit implementation
We can model such parasitics by including them in
the loop filter transfer function
Example: add two parasitic poles to first order filter
e(t)
R1
Parasitics
v(t)
C1
M.H. Perrott
MIT OCW
Closed Loop Poles Versus Open Loop Gain
Evaluation of
Phase Margin
Closed Loop Pole
Locations of G(f)
Im{s}
20log|A(f)|
Open loop
gain
increased
C
Dominant
pole pair
0 dB
f
fp fp2fp3
angle(A(f))
-90
C
B
A
A
o
o
PM = 72 for A
PM = 51o for B
o
-165
o
-180
M.H. Perrott
-240
o
-315
o
B
Non-dominant
poles
Re{s}
0
A
B
PM = -12o for C
C
MIT OCW
Corresponding Closed Loop Response
Closed Loop Step Response
Closed Loop Frequency Response
C
0 dB
A
B
C
1
B
A
Frequency
ƒ
Time
Increase in open loop gain now eventually leads to
instability
- Large peaking in closed loop frequency response
- Increasing amplitude in closed loop step response
M.H. Perrott
MIT OCW
Response of PLL to Divide Value Changes
XOR PD
Φref(t)
Loop Filter
2
π
e(t)
Kv
jf
Φout(t)
1
N
N+1
N
ƒ
v(t)
Divider
Φdiv(t)
ƒ
H(f)
VCO
t
Change in output frequency achieved by changing the
divide value
Classical approach provides no direct model of
impact of divide value variations
- Treat divide value variation as a perturbation to a linear
system
ƒ PLL responds according to its closed loop response
M.H. Perrott
MIT OCW
Response of an Actual PLL to Divide Value Change
ƒ
Example: Change divide value by one
N (Divide Value)
Synthesizer Response To Divider Step
93
92.8
92.6
92.4
92.2
92
Output Frequency (GHz)
91.8
40
60
80
100
120
140
160
180
200
220
240
40
60
80
100
120
140
160
180
200
220
240
1.87
1.86
1.85
1.84
1.83
Time (microseconds)
PLL responds according to closed loop response!
M.H. Perrott
MIT OCW
What Happens with Large Divide Value Variations?
ƒ
PLL temporarily loses frequency lock (cycle slipping
occurs)
Synthesizer Response To Divider Step
N (Divide Value)
96
95
94
93
Output Frequency (GHz)
92
40
60
80
100
120
140
160
180
200
220
240
40
60
80
100
120
140
160
180
200
220
240
1.92
1.9
1.88
1.86
1.84
Time (microseconds)
- Why does this happen?
M.H. Perrott
MIT OCW
Recall Phase Detector Characteristic
avg{e(t)}
gain = -2/π
−π
gain = 2/π
1
−π/2
0
π/2
π
Φref - Φdiv
-1
ƒ
ƒ
To simplify modeling, we assumed that we always
operated in a confined phase range (0 to π)
- Led to a simple PD model
Large perturbations knock us out of that confined
phase range
- PD behavior varies depending on the phase range it
happens to be in
M.H. Perrott
MIT OCW
Cycle Slipping
ƒ
Consider the case where there is a frequency offset
between divider output and reference
- We know that phase difference will accumulate
ref(t)
div(t)
ƒ
Resulting ramp in phase causes PD characteristic to
be swept across its different regions (cycle slipping)
avg{e(t)}
gain = -2/π
−π
gain = 2/π
1
−π/2
0
π/2
π
Φref - Φdiv
-1
M.H. Perrott
MIT OCW
Impact of Cycle Slipping
ƒ
ƒ
Loop filter averages out phase detector output
Severe cycle slipping causes phase detector to
alternate between regions very quickly
- Average value of XOR characteristic can be close to
zero
- PLL frequency oscillates according to cycle slipping
- In severe cases, PLL will not re-lock
ƒ PLL has finite frequency lock-in range!
XOR DC characteristic
cycle slipping
1
−π
π
3π
nπ
(n+2)π
Φref - Φdiv
-1
M.H. Perrott
MIT OCW
Back to PLL Response Shown Previously
ƒ
PLL output frequency indeed oscillates
- Eventually locks when frequency difference is small enough
Synthesizer Response To Divider Step
N (Divide Value)
96
95
94
93
Output Frequency (GHz)
92
40
60
80
100
120
140
160
180
200
220
240
40
60
80
100
120
140
160
180
200
220
240
1.92
1.9
1.88
1.86
1.84
Time (microseconds)
- How do we extend the frequency lock-in range?
M.H. Perrott
MIT OCW
Phase Frequency Detectors (PFD)
ƒ
Example: Tristate PFD
1
Q
D
ref(t)
up(t)
Q
R
1
div(t)
D
R
e(t)
Q
Q
down(t)
Ref(t)
Div(t)
Up(t)
Down(t)
E(t)
1
0
-1
M.H. Perrott
MIT OCW
Tristate PFD Characteristic
ƒ
Calculate using similar approach as used for XOR
phase detector
avg{e(t)}
1
gain = 1/(2π)
−2π
2π
Φref - Φdiv
−1
phase detector
range = 4π
ƒ
Note that phase error characteristic is asymmetric
about zero phase
- Key attribute for enabling frequency detection
M.H. Perrott
MIT OCW
PFD Enables PLL to Always Regain Frequency Lock
ƒ
Asymmetric phase error characteristic allows positive
frequency differences to be distinguished from
negative frequency differences
- Average value is now positive or negative according to
sign of frequency offset
- PLL will always relock
Tristate DC characteristic
cycle slipping
1
−2π
0
2π
4π
2nπ
Φref - Φdiv
lock
-1
M.H. Perrott
MIT OCW
Another PFD Structure
ƒ
XOR-based PFD
Q
D
D
ref(t)
Q
Q
D
div(t)
Q
ref/2(t)
div/2(t)
Q
R
Q
e(t)
D SQ
Q
Divide-by-2
Phase
Detector
Frequency
Detector
ref(t)
div(t)
ref/2(t)
div/2(t)
e(t)
M.H. Perrott
1
-1
MIT OCW
XOR-based PFD Characteristic
ƒ
Calculate using similar approach as used for XOR phase
detector
avg{e(t)}
1
−3π
−2π
gain = 1/π
0
π
2π
4π
5π
Φref - Φdiv
−1
phase detector
range = 2π
ƒ
Phase errror characteristic asymmetric about zero phase
- Average value of phase error is positive or negative during
cycle slipping depending on sign of frequency error
M.H. Perrott
MIT OCW
Linearized PLL Model With PFD Structures
ƒ
Assume that when PLL in lock, phase variations are
within the linear range of PFD
- Simulate impact of cycle slipping if desired (do not
include its effect in model)
ƒ
Same frequency-domain PLL model as before, but
PFD gain depends on topology used
Tristate: α=1
PFD XOR-based: α=2
Φref(t)
Φdiv(t)
M.H. Perrott
α
2π
Loop Filter
e(t)
H(f)
VCO
v(t)
Kv
jf
Φout(t)
Divider
1
N
MIT OCW
Type I versus Type II PLL Implementations
ƒ
ƒ
Type I: one integrator in PLL open loop transfer
function
- VCO adds on integrator
- Loop filter, H(f), has no integrators
Type II: two integrators in PLL open loop transfer
function
- Loop filter, H(f), has one integrator
Tristate: α=1
PFD XOR-based: α=2
Φref(t)
Φdiv(t)
M.H. Perrott
α
2π
Loop Filter
e(t)
H(f)
VCO
v(t)
Kv
jf
Φout(t)
Divider
1
N
MIT OCW
VCO Input Range Issue for Type I PLL Implementations
ƒ
DC output range of gain block versus integrator
Gain Block
0
Integrator
0
K
s
K
ƒ
Issue: DC gain of loop filter often small and PFD
output range is limited
- Loop filter output fails to cover full input range of VCO
VDD
Output Range
of Loop Filter
No
Integrator
Gnd
ref(t)
PFD
e(t)
Loop
Filter
v(t)
out(t)
VCO
Divider
M.H. Perrott
N[k]
MIT OCW
Options for Achieving Full Range Span of VCO
ƒ
Type I
- Add a D/A converter to provide coarse tuning
ƒ Adds power and complexity
ƒ Steady-state phase error inconsistently set
ƒ
Type II
- Integrator automatically provides DC level shifting
ƒ Low power and simple implementation
ƒ Steady-state phase error always set to zero
Type I
Course
Tune
D/A
No
Integrator
e(t)
M.H. Perrott
C.P.
Loop
Filter
Type II
Output Range
of Loop Filter
Output Range
of Loop Filter
VDD
VDD
Contains
Integrator
Gnd
v(t)
e(t)
C.P.
Loop
Filter
Gnd
v(t)
MIT OCW
A Common Loop Filter for Type II PLL Implementation
ƒ
Use a charge pump to create the integrator
ƒ
Gain of loop filter can be adjusted according to the
value of the charge pump current
Example: lead/lag network
ƒ
- Current onto a capacitor forms integrator
- Add extra pole/zero using resistor and capacitor
e(t)
Charge
Pump
i(t)
v(t)
C1
M.H. Perrott
R1
C2
MIT OCW
Charge Pump Implementations
ƒ
Switch currents in and out:
Single-Ended
up(t)
Icp
Differential
Icp
Iout(t)
Iout(t)
e(t)
down(t)
Icp
M.H. Perrott
Icp
e(t)
2Icp
MIT OCW
Modeling of Loop Filter/Charge Pump
ƒ
ƒ
Charge pump is gain element
Loop filter forms transfer function
Charge
Pump
e(t)
ƒ
Icp
Loop
Filter
H(s)
v(t)
Example: lead/lag network from previous slide
M.H. Perrott
MIT OCW
PLL Design with Lead/Lag Filter
ƒ
Overall PLL block diagram
Tristate: α=1
PFD XOR-based: α=2
Φref(t)
α
2π
Charge
Pump Loop Filter
e(t)
Icp
H(f)
v(t)
VCO
Kv
jf
Φout(t)
Divider
Φdiv(t)
1
N
ƒ
Loop filter
ƒ
Set open loop gain to achieve adequate phase margin
- Set f lower than and f
z
M.H. Perrott
p
higher than desired PLL bandwidth
MIT OCW
Closed Loop Poles Versus Open Loop Gain
Evaluation of
Phase Margin
Closed Loop Pole
Locations of G(f)
Im{s}
Open loop
gain
increased
20log|A(f)|
C
B
0 dB
fz
f
fp
Non-dominant
pole
C
B
A
ƒ
o
-160
o
-180
o
BC
A
o
-140
A
Re{s}
angle(A(f))
120
Dominant
pole pair
PM = 54oo for B
PM = 53 for A
PM = 55o for C
0
A
B
C
Open loop gain cannot be too low or too high if
reasonable phase margin is desired
M.H. Perrott
MIT OCW
Impact of Parasitics When Lead/Lag Filter Used
ƒ
We can again model impact of parasitics by including
them in loop filter transfer function
e(t)
Charge
Pump
i(t)
Parasitics
C1
ƒ
v(t)
R1
C2
Example: include two parasitic poles with the lead/lag
transfer function
M.H. Perrott
MIT OCW
Closed Loop Poles Versus Open Loop Gain
Evaluation of
Phase Margin
Closed Loop Pole
Locations of G(f)
Im{s}
Open loop
gain
increased
20log|A(f)|
C
Dominant
pole pair
B
0 dB
fz
angle(A(f))
120
-140
ƒ
f
fp fp2 fp3
Non-dominant
poles
C
B
A
Re{s}
-160
o
-180
o
BC
A
o
o
A
0
A
PM = 46o for A
PM = 38o for B
PM = -7o for C
B
C
Closed loop response becomes unstable if open loop
gain is too high
M.H. Perrott
MIT OCW
Negative Issues For Type II PLL Implementations
Normalized Amplitude
|G(f)|
Peaking caused by
undesired pole/zero pair
fcp fz
1
0
ƒ
fz
fo
Frequency (Hz)
Step Responses for a Second Order
G(f) implemented as a Bessel Filter
1.4
Type II: fz/fo = 1/3
Type II: fz/fo = 1/8
1
Type I
0.6
f
0
1
2
3
Normalized time: t*fo
4
Parasitic pole/zero pair causes
- Peaking in the closed loop frequency response
ƒ A big issue for CDR systems, but not too bad for wireless
- Extended settling time due to parasitic “tail” response
ƒ Bad for wireless systems demanding fast settling time
M.H. Perrott
MIT OCW