6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers
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6.976 High Speed Communication Circuits and Systems Lecture 5 High Speed, Broadband Amplifiers Michael Perrott Massachusetts Institute of Technology Copyright © 2003 by Michael H. Perrott Broadband Communication System Example: high speed data link on a PC board package Connector Adjoining pins die Controlled Impedance PCB trace Driving Source Z1 Vin On-Chip L1 Delay = x Characteristic Impedance = Zo Transmission Line C1 C2 RL VL - We’ve now studied how to analyze the transmission line effects and package parasitics - What’s next? M.H. Perrott MIT OCW High Speed, Broadband Amplifiers The first thing that you typically do to the input signal package is amplify it Connector Adjoining pins die Controlled Impedance PCB trace Driving Source Z1 Vin On-Chip L1 Delay = x Characteristic Impedance = Zo Transmission Line Function Key performance parameters Amp C1 C2 RL Vout VL - Boosts signal levels to acceptable values - Provides reverse isolation - Gain, bandwidth, noise, linearity M.H. Perrott MIT OCW Basics of MOS Large Signal Behavior (Qualitative) Triode VGS ID G S D Cchannel = Cox(VGS-VT) Pinch-off VGS S ID D Saturation Triode ∆V ID G S Pinch-off VD=∆V Saturation M.H. Perrott ID G VGS Overall I-V Characteristic VDS=0 VDS VD>∆V D MIT OCW Basics of MOS Large Signal Behavior (Quantitative) Triode VGS ID G S VDS=0 ID = µnCox W (VGS - VT - VDS/2)VDS L for VDS << VGS - VT D ID Cchannel = Cox(VGS-VT) Pinch-off ID ∆V = VGS-VT VGS G S VD=∆V VGS 2IDL µnCoxW ID G S ∆V = D Saturation M.H. Perrott µnCox W (VGS - VT)VDS L VD>∆V D ID = 1 µ C W 2 (VGS-VT) (1+λVDS) n ox 2 L (where λ corresponds to channel length modulation) MIT OCW Analysis of Amplifier Behavior Typically focus on small signal behavior - Work with a linearized model such as hybrid-π - Thevenin modeling techniques allow fast and efficient analysis To do small signal analysis: ID Small Signal Analysis Steps RD 1) Solve for bias current Id RG vout vin Vbias M.H. Perrott RS 2) Calculate small signal parameters (such as gm, ro) 3) Solve for small signal response using transistor hybrid-π small signal model MIT OCW MOS DC Small Signal Model Assume transistor in saturation: ID RD RD RG RG vgs gmvgs ro -gmbvs RS vs RS gm = µnCox(W/L)(VGS - VT)(1 + λVDS) = 2µnCox(W/L)ID (assuming λVDS << 1) gmb = γgm 2 2|Φp| + VSB where γ = 2qεsNA Cox In practice: gmb = gm/5 to gm/3 ro = 1 λID Thevenin modeling based on the above M.H. Perrott MIT OCW Capacitors For MOS Device In Saturation Top View Side View E VGS G Cov S D LD B VD>∆V D Cjdb LD L E junction bottom wall cap (per area) L source to bulk cap: Cjsb = drain to bulk cap: Cjsd = Cj(0) ΦB 1 + VSB Cj(0) 1 + VDB ΦB overlap cap: Cov = WLDCox + WCfringe WE + WE + junction sidewall cap (per length) Cjsw(0) ΦB 1 + VSB Cjsw(0) 1 + VDB ΦB (W + 2E) (make 2W for "4 sided" perimeter in some cases) (W + 2E) gate to channel cap: Cgc = channel to bulk cap: Ccb - ignore in this class M.H. Perrott Cov Cgc Ccb S W Cjsb E ID 2 C W(L-2LD) 3 ox MIT OCW MOS AC Small Signal Model (Device in Saturation) RD RG ID RD Cgd vgs RG Cgs -gmbvs ro Cdb Csb RS vs Cgs = Cgc + Cov = Cgd = Cov M.H. Perrott gmvgs RS 2 C W(L-2LD) + Cov 3 ox Csb = Cjsb (area + perimeter junction capacitance) Cdb = Cjdb (area + perimeter junction capacitance) MIT OCW Wiring Parasitics Capacitance - Gate: cap from poly to substrate and metal layers - Drain and source: cap from metal routing path to substrate and other metal layers Resistance - Gate: poly gate has resistance (reduced by silicide) - Drain and source: some resistance in diffusion region, and from routing long metal lines Inductance - Gate: poly gate has negligible inductance - Drain and source: becoming an issue for long wires Extract these parasitics from circuit layout M.H. Perrott MIT OCW Frequency Performance of a CMOS Device Two figures of merit in common use - f : frequency for which current gain is unity - f : frequency for which power gain is unity t max Common intuition about ft - Gain, bandwidth product is conserved - We will see that MOS devices have an f that shifts with t bias This effect strongly impacts high speed amplifier topology selection We will focus on ft - Look at pages 70-72 of Tom Lee’s book for discussion on fmax M.H. Perrott MIT OCW Derivation of ft for MOS Device in Saturation id ID+id RLARGE Vbias iin Cgd iin vgs Cgs gmvgs -gmbvs ro Cdb Csb Assumption is that input is current, output of device is short circuited to a supply voltage - Note that voltage bias is required at gate The calculated value of ft is a function of this bias voltage M.H. Perrott MIT OCW Derivation of ft for MOS Device in Saturation id ID+id RLARGE Vbias M.H. Perrott iin Cgd iin vgs Cgs gmvgs -gmbvs ro Cdb Csb MIT OCW Derivation of ft for MOS Device in Saturation id iin slope = -20 dB/dec 1 M.H. Perrott ft f MIT OCW Why is ft a Function of Voltage Bias? ft is a ratio of gm to gate capacitance -g is a function of gate bias, while gate cap is not (so long as device remains biased) m First order relationship between gm and gate bias: - The larger the gate bias, the higher the value for f t Alternately, ft is a function of current density - So f maximized at max current density (and minimum L) t M.H. Perrott MIT OCW Speed of NMOS Versus PMOS Devices NMOS devices have much higher mobility than PMOS devices (in current, non-strained, bulk CMOS processes) - Intuition: NMOS devices provide approximately 2.5 x g for a given amount of capacitance and gate bias voltage - Also: NMOS devices provide approximately 2.5 x I for a m d given amount of capacitance and gate bias voltage M.H. Perrott MIT OCW Assumptions for High Speed Amplifier Analysis Assume that amplifier is loaded by an identical amplifier and by fixed wiring capacitance Ctot = Cout+Cin+Cfixed Cin Cout Cin Amp Amp Cfixed Intrinsic performance - Defined as the bandwidth achieved for a given gain is negligible when C - Amplifier approaches intrinsic performance as its device fixed sizes (and current) are increased In practice, optimal sizing (and power) of amplifier is roughly where Cin+Cout = Cfixed M.H. Perrott MIT OCW The Miller Effect Concerns impedances that connect from input to output of an amplifier Zin Vin Zf Av Amp Input impedance: Output impedance: M.H. Perrott Zout Vout ZL MIT OCW Example: The Impact of Capacitance in Feedback Consider Cgd in the MOS device as Cf - Assume gain is negative Cf Zin Vin Zout Av Amp Impact on input capacitance: Output impedance: M.H. Perrott Vout ZL MIT OCW Amplifier Example – CMOS Inverter Assume that we set Vbias such that the amplifier nominal output is such that NMOS and PMOS transistors are all in saturation - Note: this topology VERY sensitive to bias errors M2 vin Vbias M1 M4 vout Cfixed M3 Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + Cfixed (+Cov1+Cov2) M.H. Perrott Miller multiplication factor MIT OCW Transfer Function of CMOS Inverter vout vin (gm1+gm2)(ro1||ro2) Low Bandwidth! slope = -20 dB/dec 1 1 2πCtot(ro1||ro2) f gm1+gm2 2πCtot M2 vin Vbias M1 M4 vout Cfixed M3 Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + Cfixed (+Cov1+Cov2) M.H. Perrott Miller multiplication factor MIT OCW Add Resistive Feedback vout vin Bandwidth extended and less sensitivity to bias offset (gm1+gm2)(ro1||ro2) slope = -20 dB/dec (gm1+gm2)Rf 1 1 2πCtot(ro1||ro2) gm1+gm2 f 2πCtot 1 2πCtotRf M2 Rf vin Vbias M1 M4 vout Cfixed M3 Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + CRf /2 + Cfixed (+Cov1+Cov2) M.H. Perrott Miller multiplication factor MIT OCW We Can Still Do Better We are fundamentally looking for high gm to capacitance ratio to get the highest bandwidth - PMOS degrades this ratio - Gate bias voltage is constrained M2 Rf vin Vbias M1 M4 vout Cfixed M3 Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + CRf /2 + Cfixed (+Cov1+Cov2) M.H. Perrott Miller multiplication factor MIT OCW Take PMOS Out of the Signal Path Vbias2 Ibias vout Rf vin Vbias M1 CL M2 vout Rf vin M1 Vbias CL Advantages - PMOS gate no longer loads the signal - NMOS device can be biased at a higher voltage Issue - PMOS is not an efficient current provider (I /drain cap) Drain cap close in value to C - Signal path is loaded by cap of R and drain cap of d gs PMOS M.H. Perrott f MIT OCW Shunt-Series Amplifier Rin Rs vin vout Rf RL M1 Vbias Rin Rout Ibias Rs Rout Rf vin Vbias R1 RL vout M1 R1 Use resistors to control the bias, gain, and input/output impedances - Improves accuracy over process and temp variations Issues - Degeneration of M lowers slew rate for large signal applications (such as limit amps) - There are better high speed approaches – the advantage 1 of this one is simply accuracy M.H. Perrott MIT OCW Shunt-Series Amplifier – Analysis Snapshot From Chapter 8 of Tom Lee’s book (see pp 191-197): Rin - Gain Rs vin Vbias Rout RL Rf vx vout M1 R1 - Input resistance - Output resistance M.H. Perrott Same for Rs = RL! MIT OCW NMOS Load Amplifier Vdd vout vin M2 vin Vbias 1 gm2 Id M1 gm1 gm2 vout Cfixed M3 slope = -20 dB/dec 1 gm2 Ctot = Cdb1+Csb2+Cgs2 + Cgs3+KCov3 + Cfixed (+Cov1) Miller multiplication factor gm1 2πCtot f 2πCtot Gain set by the relative sizing of M1 and M2 M.H. Perrott MIT OCW Design of NMOS Load Amplifier Vdd Ctot = Cdb1+Csb2+Cgs2 + Cgs3+KCov3 + Cfixed M2 vin Vbias 1 gm2 Id M1 (+Cov1) Miller multiplication factor vout Cfixed M3 Size transistors for gain and speed - Choose minimum L for maximum speed - Choose ratio of W to W to achieve appropriate gain 1 2 Problem: VT of M2 lowers the bias voltage of the next stage (thus lowering its achievable ft) - Severely hampers performance when amplifier is cascaded - One person solved this issue by increasing V of NMOS dd M.H. Perrott load (see Sackinger et. al., “A 3-GHz 32-dB CMOS Limiting Amplifier for SONET OC-48 receivers”, JSSC, Dec 2000) MIT OCW Resistor Loaded Amplifier (Unsilicided Poly) vout vin Vdd RL Id vin Vbias M1 vout Cfixed M2 slope = -20 dB/dec gm1RL 1 gm1 2πCtot Ctot = Cdb1+CRL/2 + Cgs2+KCov2 + Cfixed (+Cov1) f 1 2πRLCtot Miller multiplication factor This is the fastest non-enhanced amplifier I’ve found - Unsilicided poly is a pretty efficient current provider (i..e, has a good current to capacitance ratio) - Output swing can go all the way up to V Allows following stage to achieve high f - Linear settling behavior (in contrast to NMOS load) dd t M.H. Perrott MIT OCW Implementation of Resistor Loaded Amplifier Typically implement using differential pairs Vdd R1 R2 Vo- αIbias Vin+ Ibias/2 M1 M2 Vo+ Vin- Cfixed Cfixed M3 M 4 Ibias M5 Benefits Negative M6 M7 - Self-biased - Common-mode rejection - More power than single-ended version M.H. Perrott MIT OCW The Issue of Velocity Saturation We classically assume that MOS current is calculated as Which is really -V corresponds to the saturation voltage at a given length, which we often refer to as ∆V dsat,l It may be shown that - If V gs-VT approaches LEsat in value, then the top equation is no longer valid We say that the device is in velocity saturation M.H. Perrott MIT OCW Analytical Device Modeling in Velocity Saturation If L small (as in modern devices), than velocity saturation will impact us for even moderate values of Vgs-VT - Current increases linearly with V gs-VT! Transconductance in velocity saturation: - No longer a function of V gs! M.H. Perrott MIT OCW Example: Current Versus Voltage for 0.18µ Device Id Vgs M1 1.8µ W = L 0.18µ Id versus Vgs 1.4 1.2 Id (milliAmps) 1 0.8 0.6 0.4 0.2 0 0.4 0.6 0.8 1 1.2 V M.H. Perrott gs 1.4 1.6 1.8 2 (Volts) MIT OCW Example: Gm Versus Voltage for 0.18µ Device Id Vgs M1 1.8µ W = L 0.18µ g versus V m gs 1 0.9 0.8 0.6 0.5 0.4 m g (milliAmps/Volts) 0.7 0.3 0.2 0.1 0 0.4 0.6 0.8 1 1.2 V M.H. Perrott gs 1.4 1.6 1.8 2 (Volts) MIT OCW Example: Gm Versus Current Density for 0.18µ Device Id M1 1.8µ W = L 0.18µ Transconductance versus Current Density Transconductance (milliAmps/Volts) Vgs 1 0.8 0.6 0.4 0.2 0 0 M.H. Perrott 100 200 300 400 500 Current Density (microAmps/micron) 600 700 MIT OCW How Do We Design the Amplifier? Highly inaccurate to assume square law behavior We will now introduce a numerical procedure based on the simulated gm curve of a transistor - A look at g m assuming square law device: - Observe that if we keep the current density (I /W) d M.H. Perrott constant, then gm scales directly with W This turns out to be true outside the square-law regime as well We can therefore relate gmof devices with different widths given that have the same current density MIT OCW A Numerical Design Procedure for Resistor Amp – Step 1 Vdd R R Vo- αIbias Vin+ Ibias M1 M2 2Ibias M5 Vo+ Two key equations - Set gain and swing (singleended) Vin- Equate (1) and (2) through R M6 Can we relate this formula to a gm curve taken from a device of width Wo? M.H. Perrott MIT OCW A Numerical Design Procedure for Resistor Amp – Step 2 We now know: Substitute (2) into (1) The above expression allows us to design the resistor loaded amp based on the gm curve of a representative transistor of width Wo! M.H. Perrott MIT OCW Example: Design for Swing of 1 V, Gain of 1 and 2 Assume L=0.18µ, use previous gm plot (Wo=1.8µ) Transconductance versus Current Density A=2 Transconductance (milliAmps/Volts) 1 A=1 gm(wo=1.8µ,Iden) 0.8 0.6 0.4 For gain of 1, current density = 250 µA/µm For gain of 2, current density = 115 µA/µm Note that current density reduced as gain increases! - f effectively 0.2 t 0 0 M.H. Perrott 100 200 300 400 500 Current Density - Iden (microAmps/micron) 600 700 decreased MIT OCW Example (Continued) Knowledge of the current density allows us to design the amplifier - Recall - Free parameters are W, I bias, and R (L assumed to be fixed) Given Iden = 115 µA/µm (Swing = 1V, Gain = 2) - If we choose I bias = 300 µA Note that we could instead choose W or R, and then calculate the other parameters M.H. Perrott MIT OCW How Do We Choose Ibias For High Bandwidth? Ctot = Cout+Cin+Cfixed Cin Cout Cin Amp Amp Cfixed As you increase Ibias, the size of transistors also increases to keep a constant current density - The size of C in and Cout increases relative to Cfixed To achieve high bandwidth, want to size the devices (i.e., choose the value for Ibias), such that - C +C in M.H. Perrott out roughly equal to Cfixed MIT OCW
