6.976 High Speed Communication Circuits and Systems Lecture 4
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6.976
High Speed Communication Circuits and Systems
Lecture 4
Generalized Reflection Coefficient, Smith Chart,
Integrated Passive Components
Michael Perrott
Massachusetts Institute of Technology
Copyright © 2003 by Michael H. Perrott
Determine Voltage and Current At Different Positions
ZL
Incident Wave
Ex
jwt jkz
V+e e
x
y
I+ejwtejkz
Hy
ZL
z
Reflected Wave
Hy
Ex
V-ejwtejkz
I-ejwtejkz
z
L
0
Incident and reflected waves must be added together
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Determine Voltage and Current At Different Positions
ZL
Incident Wave
Ex
jwt jkz
V+e e
x
y
I+ejwtejkz
Hy
ZL
z
Reflected Wave
Hy
Ex
V-ejwtejkz
I-ejwtejkz
z
L
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0
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Define Generalized Reflection Coefficient
Similarly:
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A Closer Look at Γ(z)
Recall ΓL is
Im{Γ(z)}
Note:
|ΓL|
∆
ΓL
We can view Γ(z)
as a complex
number that
rotates clockwise
as z (distance
from the load)
increases
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Γ(z)
0
|ΓL|
= 2kz
ΓL
Re{Γ(z)}
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Calculate |Vmax| and |Vmin| Across The Transmission Line
We found that
So that the max and min of V(z,t) are calculated as
We can calculate this geometrically!
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A Geometric View of |1 + Γ(z)|
Im{1+Γ(z)}
Γ(z)
|1+Γ(z)|
|ΓL|
0
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1
Re{1+Γ(z)}
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Reflections Cause Amplitude to Vary Across Line
Equation:
Graphical representation:
direction
of travel
jwt jkz
V+e e
t
z
λ
|1 + Γ(z)|
max|1+Γ(z)|
|1+Γ(0)|
z
min|1+Γ(z)|
0
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Voltage Standing Wave Ratio (VSWR)
Definition
For passive load (and line)
We can infer the magnitude of the reflection
coefficient based on VSWR
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Reflections Influence Impedance Across The Line
From Slide 4
- Note: not a function of time! (only of distance from load)
Alternatively
- From Lecture 2:
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Example: Z(λ/4) with Shorted Load
λ/4
x
Z(λ/4)
y
z
ZL
z
L
0
Calculate reflection coefficient
Calculate generalized reflection coefficient
Calculate impedance
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Generalize Relationship Between Z(λ/4) and Z(0)
General formulation
At load (z=0)
At quarter wavelength away (z = λ/4)
- Impedance is inverted!
Shorts turn into opens
Capacitors turn into inductors
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Now Look At Z(∆) (Impedance Close to Load)
Impedance formula (∆ very small)
- A useful approximation:
- Recall from Lecture 2:
Overall approximation:
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Example: Look At Z(∆) With Load Shorted
ZL
x
Z(∆)
y
z
z
∆ 0
Reflection coefficient:
Resulting impedance looks inductive!
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Example: Look At Z(∆) With Load Open
ZL
x
Z(∆)
y
z
z
∆ 0
Reflection coefficient:
Resulting impedance looks capacitive!
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Consider an Ideal LC Tank Circuit
Zin
L
C
Calculate input impedance about resonance
=0
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negligible
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Transmission Line Version: Z(λ0 /4) with Shorted Load
λ0/4
Z(λ0/4)
x
y
z
z
L
As previously calculated
Impedance calculation
Relate λ to frequency
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ZL
0
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Calculate Z(∆ f) – Step 1
λ0/4
Z(λ0/4)
x
y
z
z
L
Wavelength as a function of ∆ f
Generalized reflection coefficient
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ZL
0
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Calculate Z(∆ f) – Step 2
λ0/4
Z(λ0/4)
x
y
z
z
L
Impedance calculation
Recall
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ZL
0
- Looks like LC tank circuit about frequency w !
o
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Smith Chart
Define normalized impedance
Mapping from normalized impedance to Γ
is one-to-one
- Consider working in coordinate system based on Γ
Key relationship between Zn and Γ
- Equate real and imaginary parts to get Smith Chart
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Real Impedance in Γ Coordinates (Equate Real Parts)
Im{ΓL}
ΓL=j
ΓL=-1
0.2
ΓL=1
ΓL=0
0.5
1
2
5
Re{ΓL}
Zn=0.5
ΓL=-j
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Imag. Impedance in Γ Coordinates (Equate Imag. Parts)
j1 Im{ΓL}
j0.5
j0.2
ΓL=j
j2
j5
Zn=j0.5
ΓL=-1
ΓL=1
ΓL=0
Re{ΓL}
0
-j0.2
Zn=-j0.5
-j0.5
-j5
ΓL=-j
-j2
-j1
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What Happens When We Invert the Impedance?
Fundamental formulas
Impact of inverting the impedance
- Derivation:
We can invert complex impedances in Γ plane by
simply changing the sign of Γ !
How can we best exploit this?
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The Smith Chart as a Calculator for Matching Networks
Consider constructing both impedance and
admittance curves on Smith chart
- Conductance curves derived from resistance curves
- Susceptance curves derived from reactance curves
For series circuits, work with impedance
For parallel circuits, work with admittance
- Impedances add for series circuits
- Admittances add for parallel circuits
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Resistance and Conductance on the Smith Chart
Im{ΓL}
ΓL=j
Yn=0.5
Zn=0.5
ΓL=-1
Yn=2
0.2
ΓL=1
ΓL=0
Zn=2
0.5
1
2
5
Re{ΓL}
ΓL=-j
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Reactance and Susceptance on the Smith Chart
j1 Im{ΓL}
j0.5
j0.2
ΓL=j
j2
Yn=-j2
Zn=j2
j5
ΓL=0
ΓL=-1
ΓL=1
Re{ΓL}
0
-j0.2
Yn=j2
-j0.5
Zn=-j2
ΓL=-j
-j5
-j2
-j1
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Overall Smith Chart
j1
j0.5
j2
j0.2
0
j5
0.2
0.5
1
2
5
−j0.2
−j5
−j0.5
−j2
−j1
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Example – Match RC Network to 50 Ohms at 2.5 GHz
Circuit
Zin
Matching
Network
ZL
Cp=1pF
Rp=200
Step 1: Calculate ZLn
Step 2: Plot ZLn on Smith Chart (use admittance, YLn)
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Plot Starting Impedance (Admittance) on Smith Chart
j1
j0.5
j2
j0.2
0
j5
0.2
0.5
1
2
5
-j0.2
-j5
-j0.5
YLn=0.25+j0.7854
-j2
-j1
(Note: ZLn=0.37-j1.16)
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Develop Matching “Game Plan” Based on Smith Chart
By inspection, we see that the following matching
network can bring us to Zin = 50 Ohms (center of
Smith chart)
Matching Network
Lm
Zin
Cm
ZL
Cp=1pF
Rp=200
Use the Smith chart to come up with component
values
- Inductance L shifts impedance up along reactance
curve
- Capacitance C shifts impedance down along
m
m
susceptance curve
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Add Reactance of Inductor Lm
j1
j0.5
j2
Z2n=0.37+j0.48
j0.2
0
-j0.2
j5
0.2
normalized
inductor
reactance
= j1.64
-j0.5
0.5
1
2
5
-j5
ZLn=0.37-j1.16
-j2
-j1
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Inductor Value Calculation Using Smith Chart
From Smith chart, we found that the desired
normalized inductor reactance is
Required inductor value is therefore
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Add Susceptance of Capacitor Cm (Achieves Match!)
j1
j0.5
Z2n=0.37+j0.48
(note: Y2n=1.00-j1.31)
normalized
capacitor
susceptance
= j1.31
j0.2
0
j2
0.2
0.5
1.0+j0.0
1
2
j5
5
-j0.2
-j5
-j0.5
ZLn=0.37-j1.16
-j2
-j1
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Capacitor Value Calculation Using Smith Chart
From Smith chart, we found that the desired
normalized capacitor susceptance is
Required capacitor value is therefore
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Just For Fun
Play the “matching game” at
http://contact.tm.agilent.com/Agilent/tmo/an-95-1/classes/imatch.html
- Allows you to graphically tune several matching
networks
- Note: game is set up to match source to load impedance
rather than match the load to the source impedance
Same results, just different viewpoint
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Passives
Polysilicon Resistors
Use unsilicided polysilicon to create resistor
A
Rpoly
A
B
B
Key parameters
- Resistance (usually 100- 200 Ohms per square)
- Parasitic capacitance (usually small)
Appropriate for high speed amplifiers
- Linearity (quite linear compared to other options)
- Accuracy (usually can be set within ± 15%)
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MOS Resistors
Bias a MOS device in its triode region
Rds
A
W/L
B
A
B
High resistance values can be achieved in a small
area (MegaOhms within tens of square microns)
Resistance is quite nonlinear
- Appropriate for small swing circuits
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High Density Capacitors (Biasing, Decoupling)
MOS devices offer the highest capacitance per unit area
- Limited to a one terminal device
- Voltage must be high enough to invert the channel
A
A
C1=CoxWL
Key parameters
- Capacitance value
-
W/L
Raw cap value from MOS device is 6.1 fF/µ m2 for 0.24u
CMOS
Q (i.e., amount of series resistance)
Maximized with minimum L (tradeoff with area efficiency)
See pages 39-40 of Tom Lee’s book
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High Q Capacitors (Signal Path)
Lateral metal capacitors offer high Q and reasonably
large capacitance per unit area
- Stack many levels of metal on top of each other (best
layers are the top ones), via them at maximum density
A
A
C1
B
- Accuracy often better than ±10%
- Parasitic side cap is symmetric, less than 10% of cap value
B
Example: CT = 1.5 fF/µm2 for 0.24µm process with 7
metals, Lmin = Wmin = 0.24µm, tmetal = 0.53µm
- See “Capacity Limits and Matching Properties of Integrated
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Capacitors”, Aparicio et. al., JSSC, Mar 2002
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Spiral Inductors
Create integrated inductor using spiral shape on top level
metals (may also want a patterned ground shield)
A
A
Lm
B
B
- Key parameters are Q (< 10), L (1-10 nH), self resonant freq.
- Usually implemented in top metal layers to minimize series
resistance, coupling to substrate
- Design using Mohan et. al, “Simple, Accurate Expressions
for Planar Spiral Inductances, JSSC, Oct, 1999, pp 1419-1424
- Verify inductor parameters (L, Q, etc.) using ASITIC
http://formosa.eecs.berkeley.edu/~niknejad/asitic.html
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Bondwire Inductors
Used to bond from the package to die
- Can be used to advantage
package
Adjoining pins
From board
die
Lbondwire
Cpin
To chip circuits
Cbonding_pad
Key parameters
- Inductance ( ≈ 1 nH/mm – usually achieve 1-5 nH)
- Q (much higher than spiral inductors – typically > 40)
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Integrated Transformers
Utilize magnetic coupling between adjoining wires
A
B
Cpar1
k
C
L1
D
L2
C
Cpar2
D
Key parameters
Design – ASITIC, other CAD packages
- L (self inductance for primary and secondary windings)
- k (coupling coefficient between primary and secondary)
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A
B
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High Speed Transformer Example – A T-Coil Network
A T-coil consists of a center-tapped inductor with
mutual coupling between each inductor half
B
L2
CB
X
k
L1
X
A
A
B
Used for bandwidth enhancement
- See S. Galal, B. Ravazi, “10 Gb/s Limiting Amplifier and
Laser/Modulator Driver in 0.18u CMOS”, ISSCC 2003, pp
188-189 and “Broadband ESD Protection …”, pp. 182-183
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