6.976 High Speed Communication Circuits and Systems Lecture 1 Overview of Course
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6.976 High Speed Communication Circuits and Systems Lecture 1 Overview of Course Michael Perrott Massachusetts Institute of Technology Copyright © 2003 by Michael H. Perrott Wireless Systems Direct conversion architecture A/D D/A Digital Processing Block LNA sin(wot) 90o Power Amp sin(wot) 90o A/D D/A Transmit IC Digital Processing Block Receive IC Transmitter issues - Meeting the spectral mask (LO phase noise & feedthrough, quadrature accuracy), D/A accuracy, power amp linearity Receiver Issues - Meeting SNR (Noise figure, blocking performance, channel selectivity, LO phase noise, A/D nonlinearity and noise), selectivity (filtering), and emission requirements M.H. Perrott MIT OCW Future Goals Low cost, low power, and small area solutions Increased spectral efficiency - New architectures and circuits! - Example: GSM cellphones (GMSK) to 8-PSK (Edge) Requires a linear power amplifier! Increased data rates - Example: 802.11b (11 Mb/s) to 802.11a (> 50 Mb/s) GFSK modulation changes to OFDM modulation Higher carrier frequencies New modulation formats New application areas - 802.11b (2.5 GHz) to 802.11a (5 GHz) to ? (60 GHz) - GMSK, CDMA, OFDM, pulse position modulation M.H. Perrott MIT OCW High Speed Data Links A common architecture Digital Processing Block MUX Driver 10 Gb/s Data Link Clock Generation Transmit IC Amp Clock and Data Recovery DEMUX Clock Distribution Digital Processing Block Receive IC Transmitter Issues - Intersymbol interference (limited bandwidth of IC amplifiers, packaging), clock jitter, power, area Receiver Issue - Intersymbol interference (same as above), jitter from clock and data recovery, power, area M.H. Perrott MIT OCW Future Goals Low cost, low power, small area solutions Increased data rates - New architectures and circuits! - 40 Gb/s for optical (moving to 120 Gb/s!) Electronics is a limitation (optical issues getting significant) - > 5 Gb/s for backplane applications The channel (i.e., the PC board trace) is the limitation High frequency compensation/equalization Multi-level modulation - Higher data rates, lower bit error rates (BER), improved robustness in the face of varying conditions - How do you do this at GHz speeds? - Better spectral efficiency (more bits in given bandwidth) M.H. Perrott MIT OCW This Class Circuit AND system focus Circuit stuff System stuff - Knowing circuit design is not enough - Knowing system theory is not enough - RF issues: transmission lines and impedance transformers - High speed design techniques - Basic building blocks: amplifiers, mixers, VCO’s, digital components - Nonidealities: noise and nonlinearity - Macromodeling and simulation - Wireless and high speed data link principles - System level blocks: PLL’s, CDR’s, transceivers M.H. Perrott MIT OCW The Goal – Design at Circuit/System Level 1. Design architecture with analytical models 2. Verify architectural ideas by simulating with ideal macro-models of circuit blocks 3. Go back to 1. if the architecture breaks! Design circuit blocks and get better macro-models 5. 6. Guess macro-models for new circuits Add known non-idealities of circuit blocks (nonlinearity, noise, offsets, etc.) 4. May require new circuits – guess what they look like Go back to 1. if you can’t build the circuit! Go back to 1. if the architecture breaks! Verify as much of system as possible with SPICE Layout, extract, verify M.H. Perrott Do this soon for high speed systems - iteration likely! MIT OCW Key System Level Simulation Needs You need a fast simulator You need to be able to add non-idealities in a controlled manner - To design new things well, you must be able to iterate - The faster the simulation, the faster you can iterate - Fundamental issues with architectures need to be separated from implementation issues An architecture that is fundamentally flawed should be quickly abandoned You need flexibility - Capable of implementing circuit blocks such as filters, VCO’s, etc. - Capable of implementing algorithms - Arbitrary level of detail M.H. Perrott MIT OCW A Custom C++ Simulator Will Be Used - CppSim Blocks are implemented with C/C++ code Users enter designs in graphical form using Cadence schematic capture - High computation speed - Complex block descriptions - System analysis and transistor level analysis in the same CAD framework Resulting signals are viewed in Matlab Note: Hspice used for circuit level simulations - Powerful post-processing and viewing capability CppSim is on Athena and freely downloadable at http://www-mtl.mit.edu/~perrott M.H. Perrott MIT OCW A Quick Preview of Homeworks and Projects HW1 – Transmission Lines and Transformers High speed data link application: High Speed Trace (RF Connector to Chip Die) package Connector Adjoining pins die Controlled Impedance PCB trace Two-Port Model Driving Source On-Chip Ro Ei1 Vin M.H. Perrott Er1 L1 Delay = x Characteristic Impedance = Ro Ideal Transmission Line C1 C2 Ei2 Er2 RL Vout MIT OCW HW2 – High Speed Amplifiers Broadband R1 R2 Vo+ VoVin+ Ibias M3 M1 M2 Vin- Narrowband Ld Ibias = 1mA M4 Vout 5 kΩ M3 Vin M2 CL=1pF Lg 50 Ω Cbig x M1 Ls Zin M.H. Perrott MIT OCW HW3 – Amplifier Noise and Nonlinearity Amplifier circuit RL Ibias Vout RT 2 0.18 M2 50 Ω Cbig2 10 0.18 Cbig1 Model Noise 50 Ω Vin Vin M.H. Perrott M1 Nonlinearity Vout 50 Ω Vout = co + c1x + c2x2 + c3x3 MIT OCW HW4 – Low Noise Amplifiers and Mixers Narrowband LNA Ld Ibias = 1mA Rpd 5 kΩ M2 Cbig M3 Lg 50 Ω Rps Vin Cbig Zin Vout CL=1pF Rpg M1 Rps RS/2 Passive Mixer Cbig Vdd Ls 0 LO Vin Vout LO LO CL RL/2 RL/2 Vout 0V LO Vdd M.H. Perrott RS/2 Cbig 0 MIT OCW HW5 – Voltage Controlled Oscillators Differential CMOS 1.8 V 100/0.18 M3 M4 100/0.18 Ctune Vout Vin Vout 0V M2 M1 Vout 50/0.18 M1 Vbias=1.2V M.H. Perrott Rd=10kΩ Ld=4nH 3 nH 50/0.18 Colpitts Ibias=100 µA C1=2pF C2=8pF MIT OCW Project 1 - High Speed Frequency Dividers High speed latches/registers High speed dual-modulus divider 2/3 IN Φ Load Load OUT IN OUT 2/3 Core A 2 B 2 OUT CON* CON Control Qualifier IN Φ 8 + CON Cycles IN A B OUT CON* CON M.H. Perrott MIT OCW HW6 – Phase Locked Loop Design T Integer-N synthesizer ref(t) PFD e(t) Icp vin(t) Loop Filter out(t) VCO T Divider div(t) N[k] = Nnom Phase noise simulation SΦout(f) s 1 + s/(2πfp) vin out t out(t) = cos(2π (fo+Kvvin(τ))dτ) 2 vph K2 dBc -20 dBc/Hz/dec K1 dBc/Hz vspur = Asin(2πfst) 0 M.H. Perrott fs fp foffset MIT OCW Project 2 – GMSK Transmitter for Wireless Apps Reference Frequency (100 MHz) Loop Filter vin(t) H(s) Icp PFD out(t) T Power Amp Kv = 30 MHz/V fo = 900 MHz Limit Amp 90 RF Transmit Spectrum Trans. Noise o 0 fRF f Q N I Digital I/Q Generation Td T T t t Instantaneous Frequency Data Generator Gaussian f inst LPF 1-z cos(Φ) D/A sin(Φ) D/A Φ -1 Data Eye t Td = M.H. Perrott K ph 1 1 MHz Peak-to-Peak Frequency Deviation Includes Zero-Order Hold MIT OCW Project 2 – Accompanying Receiver Receiver Noise Received Spectrum fRF NR Trans. Noise fRF f Channel Select Filter f Band Select Filter Baseband Spectrum S( IR+jQR) IR LNA Modulation Signal cos(2πfRFt) Receiver Noise sin(2πfRFt) Transmitter Noise 0 f QR M.H. Perrott MIT OCW Basics of Digital Communication Example: A High Speed Backplane Data Link Suppose we consider packaging issues at the receiver side (ignore transmitter packaging now for simplicity) Transmitter Receiver package 100 Ω 100 Ω Adjoining pins die Vo+ Ibias Vin+ M3 Controlled Impedance PCB trace On-Chip Ideal Transmission Line Ei1 M.H. Perrott Vin- Two-Port Model 100 Ω Er1 intentional mismatch M2 M4 Driving Source Vin M1 Delay = 110 ps Characteristic Impedance = 50 Ω 0.5 pF 1 nH Ei2 0.5 pF Er2 55 Ω Vout unintentional mismatch MIT OCW Modulation Format Binary, Non-Return to Zero (NRZ), Pulse Amplitude Modulation (PAM) - Send either a zero or one in a given time interval T - Time interval set by a low jitter clock - Ideal signal from transmitter: d 0.4 0.35 0.3 0.25 in 0.2 0.15 0.1 0.05 0 −0.05 0 0.5 1 1.5 TIME M.H. Perrott 2 2.5 −8 x 10 MIT OCW Receiver Function Two operations - Recover clock and use it to sample data - Evaluate data to be 0 or 1 based on a slicer Detector Data Out Clock Recovery Recovered Clock Sampling Instant Slice Level Data Recovered Clock 0 1 1 1 0 0 0 1 0 1 0 0 1 M.H. Perrott Out MIT OCW Issue: PC Board Trace is Not an Ideal Channel Chip capacitance and inductance limits bandwidth Transmission line effects cause reflections in the presence of impedance mismatch Example: transmit at 1 Gb/s across link in previous slide (assume bondwire inductance is zero) - Signal at receiver termination resistor 0.4 0.35 0.3 0.25 out 0.2 0.15 0.1 0.05 0 −0.05 0 0.5 1 1.5 TIME M.H. Perrott 2 2.5 −8 x 10 MIT OCW Eye Diagram for 1 Gb/s Data Rate Wrap signal back onto itself every 2*Td seconds Allows immediate assessment of the quality of the signal at the receiver (look at eye opening) - Same as an oscilloscope would do Eye Diagram 0.4 0.35 0.3 0.25 out 0.2 0.15 0.1 0.05 0 −0.05 M.H. Perrott 0 0.2 0.4 0.6 0.8 1 1.2 Time (seconds) 1.4 1.6 1.8 2 −9 x 10 MIT OCW Relationship of Eye to Sampling Time and Slice Level Horizontal portion of eye indicates sensitivity to timing jitter Vertical portion of eye indicates sensitivity to additional noise and ISI Sampling Instant Eye Diagram 0.4 0.35 0.3 0.25 Slice Level out 0.2 0.15 0.1 0.05 0 0.05 M.H. Perrott 0 0.2 0.4 0.6 0.8 1 1.2 Time (seconds) 1.4 1.6 1.8 2 9 x 10 MIT OCW What Happens if We Increase the Data Rate? Limited bandwidth and reflections cause intersymbol interference (ISI) Eye diagram at 10 Gb/s for same data link Eye Diagram 0.6 0.5 0.4 out 0.3 0.2 0.1 0 −0.1 M.H. Perrott 0 1 Time (seconds) 2 −10 x 10 MIT OCW What is the Impact of the Bondwire Inductance? Rule of thumb: 1 nH/mm for bondwire Impact of inductance here increases bandwidth - Assume 1 nH - less ISI occurs Eye Diagram 0.6 0.5 0.4 out 0.3 0.2 0.1 0 −0.1 M.H. Perrott 0 1 Time (seconds) 2 −10 x 10 MIT OCW How High of a Data Rate Can The Channel Support? Raise it to 25 Gb/s Eye Diagram 0.6 0.5 0.4 out 0.3 0.2 0.1 0 −0.1 0 2 4 Time (seconds) 6 8 −11 x 10 However, we haven’t considered other issues - PC board trace attenuates severely at high frequencies Bandwidth is < 5 GHz for 48 inch PC board trace (FR4) M.H. Perrott MIT OCW Multi-Level Signaling Increase spectral efficiency by sending more than one bit during a symbol interval - Example: 4-Level PAM at 12.5 Gb/s on same channel Effective data rate: 25 Gb/s Eye Diagram 0.5 0.4 0.3 out 0.2 0.1 0 −0.1 −0.2 M.H. Perrott 0 0.2 0.4 0.6 0.8 Time (seconds) 1 1.2 1.4 1.6 −10 x 10 MIT OCW How Else Can We Reduce ISI? Consider a system level view of the link - Channel can be viewed as having an equivalent frequency response Assumes linearity and time-invariance (accurate for most transmission line systems) Transmitter Receiver Channel Transmitter Driver M.H. Perrott Receiver Detector MIT OCW Equalization Undo channel frequency response with an inverse filter at the receiver - Removes ISI! - Can make it adaptive to learn channel Transmitter Receiver Channel Transmitter Driver M.H. Perrott Equalization Receiver Detector MIT OCW The Catch Equalization enhances noise Optimal approach is to make ISI and noise degradation about equal - Overall SNR may be reduced Transmitter Receiver Channel Transmitter Driver M.H. Perrott Noise Equalization Receiver Detector MIT OCW Alternative – Pre-emphasize at Transmitter Put inverse filter at transmitter instead of receiver - No enhancement of noise, but … - Need feedback from receiver to learn channel - Requires higher dynamic range/power from transmitter Trransmitter Compensation (Pre-emphasis) Transmitter Driver M.H. Perrott Receiver Channel Noise Receiver Detector MIT OCW Best Overall Performance Combine compensation and equalization - Starting to see this for high speed links Trransmitter Compensation (Pre-emphasis) Transmitter Driver M.H. Perrott Receiver Channel Noise Equalization Receiver Detector MIT OCW What are the Issues with Wireless Systems? Noise Selectivity (filtering, processing gain) Nonlinearity Multi-path (channel response) - Need to extract the radio signal with sufficient SNR - Need to remove interferers (which are often much larger!) - Degrades transmit spectral mask - Degrades selectivity for receiver - Degrades signal – nulls rather than ISI usually the issue - Can actually be used to advantage! We will look at BOTH broadband data links and wireless systems in this class M.H. Perrott MIT OCW
