Viterbi Algorithm - Implementation
Lecture 14
Vladimir Stojanović
6.973 Communication System Design – Spring 2006
Massachusetts Institute of Technology
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Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
Convolutional Codes
‰
Adding redundancy
1+D2
di
D
+
0111
di-1
D
Channel
di-2
(00, 11, 10, 10)
0110
1+D+D2
0100
+
Generators:
G1 = 101
G2 = 111
‰
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Decisions at Each Step
i
i+1
i+2
‰
00
01
‰
10
11
State (path)
metrics
Branch
metrics
In Gaussian channel:
bm = (yk – sk)2
In BSC:
bm = dH(yk, sk) = |yk –
sk|
dH is Hamming distance
‰ If received yk = 10
dH(10, 00) = 1
dH(10, 01) = 2
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Trellis Diagram
‰
Time-indexed state diagram
i
00
01
10
i+1
i+2
0/00
0/00
1/11
1/11
i+3
i+4
0/11
1/00
11
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The Viterbi Algorithm
‰
Illustrated by 2-state trellis
sm1n−1
sm1n
bm1
bm2
sm2 n−1
bm3
bm4
tn−1
sm2 n
tn
time
sm1n = min ( sm1n−1 + bm1, sm2 n−1 + bm3)
sm2 n = min ( sm1n−1 + bm2, sm2 n−1 + bm4 )
Add
Select
Add
Compare
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Viterbi Decoder
‰
‰
Implements Viterbi algorithm
Three main components
„
„
„
Branch metric calculation
Path metric accumulation (add-compare
select recursion)
Survivor path decode
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Viterbi Decoder
D
Inputs
‰
Survivor
path
decode
Decoded bits
Calculates the distances between the received signal
and the ideal signals
Add-Compare-Select unit
„
‰
AddCompareSelect
Branch metrics unit
„
‰
Branch
metrics
unit
Accumulates path metrics
Survivor path decode
„
Keeps track of the path through the trellis
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Calculating Branch Metrics
‰
‰
‰
Assume G1 and G2 both output a 0
Soft decoder inputs are 0.1 and 0.25 instead
Branch metrics:
„
„
„
„
bm00 = |0 – 0.1| + |0 – 0.25| = 0.35
bm01 = |0 – 0.1| + |1 – 0.25| = 0.85
bm10 = |1 – 0.1| + |0 – 0.25| = 1.15
bm11 = |1 – 0.1| + |1 – 0.25| = 1.65
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Calculating Branch Metrics
Euclidean distances (AWGN channel)
‰ bmi = (yk – sk)2
‰ sk are usually integers
bmi = yk2 -2Ciyk + Ci2
‰ Since yk terms are common to all branch
metrics they drop out in ACS comparison,
and can be eliminated.
‰ Ci2 are precomputed and 2Ciyk are shifts and
adds.
‰
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Add-Compare-Select Recursion
Eight state trellis
Conventional
add-compare-select unit
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Add-Compare-Select Recursion
sm1
sm2
8
8
bm1
Adder
5
bm2
Adder
5
8
8
Subtractor
MSB
2:1 Multiplexer
Register
Decision
New State Metric
8
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Add-Compare-Select Recursion
sm2
sm2
sm1
7
sm1
6
−
+
5
bm2
sm2
bm1
sm1
−
+
6
sm2
−
+
7
sm1
bm2
sm2
bm1
3
bm2
sm2
bm1
−
+
3
bm2
sm2
bm1
sm1
0
0
0
+
4
−
+
2
1
1
5
3
2
1
6
sm
2
bm2
sm2
bm1
sm
sm
4
3
7
−
+
4
sm
sm
5
4
4
diff
−
+
sm
2
sm
1
−
sm
0
0
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Add-Compare-Select Recursion
Time
Register
Select
C
C
C
C
C
C
Add
C
C
Register
0
1
2
3
4
Bit
5
6
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Add-Compare-Select Recursion
One step lookahead
applied to an eight-state trellis
Radix-4
add-compare-select unit
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Add-Compare-Select Recursion
sm1
bm1
sm3
sm2
8
8
sm4
8
8
Adder
5
bm2
Adder
5
bm3
Adder
5
bm4
Adder
8
8
8
Inhibit sm4
8
Inhibit sm3
5
MSB
Subtractor
MSB
Subtractor
MSB
Subtractor
MSB
Subtractor
Select
4-way ACS:
2 additions +
6 comparisons
MSB
Subtractor
MSB
Subtractor
4:1 Multiplexer
Register
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State Metric 8
Decision
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Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
2-state example
Figure from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture."
IEEE Communications Magazine 29 (1991): 46-55. Copyright 1991 IEEE. Used with permission.
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Figure from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture."
IEEE Communications Magazine 29 (1991): 46-55. Copyright 1991 IEEE. Used with permission.
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Bit-level view
MSB
LSB
Figure from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture."
IEEE Communications Magazine 29 (1991): 46-55. Copyright 1991 IEEE. Used with permission.
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Turn into forward path and pipeline
Figures from Fettweis, G., and H. Meyr. "High-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecture."
IEEE Communications Magazine 29 (1991): 46-55. Copyright 1991 IEEE. Used with permission.
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Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].
Add-Compare-Select Recursion
Parallel compare-select-add unit
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References
Slides from Borivoje Nikolic and Bob Brodersen
‰ G. Fettweis and H. Meyr "High-speed parallel Viterbi decoding: algorithm and VLSI-
architecture," Communications Magazine, IEEE
vol. 29, no. 5, pp. 46-55, 1991.
‰
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