L10: Analog Building Blocks
(OpAmps, A/D, D/A)
Acknowledgement:
Materials in this lecture are courtesy of the following sources and are used with permission.
Dave Wentzloff
L10: 6.111 Spring 2006
Introductory Digital Systems Laboratory
1
Introduction to Operational Amplifiers
DC Model
+
vid
Rin
a ⋅ vid
Rout
vout
„
Typically very high input
resistance ~ 300KΩ
„
High DC gain (~105)
„
Output resistance ~75Ω
−
Vout = a ( f ) ⋅ Vin
LM741 Pinout
a(f)
+10 to +15V
10 5
-20dB/
decade
Reprinted with
permission of
National
Semiconductor
Corporation.
-10 to -15V
Reprinted with permission of National Semiconductor Corporation.
L10: 6.111 Spring 2006
10Hz
Introductory Digital Systems Laboratory
f
2
The Inside of a 741 OpAmp
Reprinted with
permission of
National
Semiconductor
Corporation.
Differential
Input Stage
Current Source Additional
for biasing
Gain Stage
Output Stage
Output devices
provides large
drive current
Bipolar version
has small input
Bias current
MOS OpAmps
have ~ 0 input
current
Gain is Sensitive to Operating Condition
(e.g., Device, Temperature, Power supply voltage, etc.)
Reprinted with permission of National Semiconductor Corporation.
L10: 6.111 Spring 2006
Introductory Digital Systems Laboratory
3
Simple Model for an OpAmp
VCC
i+ ~ 0
+
vid +
i- ~ 0
+
vout
-VCC
Linear Mode
vid
-
ε = 100μV
Negative Saturation
+
+
-
-100μV
vid
-VCC = -10V
Reasonable
approximation
+
VCC = 10V
vout
avid vout
-
If -VCC < vout < VCC
vid
+
+
-
-
Positive Saturation
+
-VCC vout
-
vid
vid < - ε
+
-
+
-
+
+VCC vout
-
vid > ε
Small input range for “Open” loop Configuration
L10: 6.111 Spring 2006
Introductory Digital Systems Laboratory
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The Power of (Negative) Feedback
R1
vin
+
-
+
R1
R2
vout
vin
vin + vid vout + vid
+
=0
R1
R2
R2
-
+
-
v
vid = out
a
R2 a
vout
R2
=−
≈ − (if
(1 + a )R1 + R2
vin
R1
vid
+
vin
vout
=−
R1
a
+
-
+
avid vout
-
⎡1
a
1⎤
+ ⎥
⎢ +
⎣ R1 R2 R2 ⎦
a >> 1)
ƒ Overall (closed loop) gain does not depend on open loop gain
ƒ Trade gain for robustness
ƒ Easier analysis approach: “virtual short circuit approach”
ƒ v+ = v- = 0 if OpAmp is linear
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Introductory Digital Systems Laboratory
5
Basic OpAmp Circuits
Non-inverting
Voltage Follower (buffer)
+
vin +
−
vout
-
R + R2
vout ≈ 1
vin
R1
vout ≈ vin
Differential Input
Integrator
t
vout ≈
L10: 6.111 Spring 2006
(
R2
v − vin1
R1 in 2
)
Introductory Digital Systems Laboratory
vout ≈ − 1
RC
∫v
in dt
−∞
6
Use With Open Loop
Analog Comparator:
Is V+ > V- ?
The Output is a DIGITAL signal
LM311 is a single supply
comparator
L10: 6.111 Spring 2006
Introductory Digital Systems Laboratory
7
Data Conversion: Quantization Noise
D/A Conversion
11
Analog Output
Binary Output
A/D Conversion
10
01
00
0
Vref
4
Vref
2
3Vref
4
Vref
Analog Input
3Vref
4
Vref
2
Vref
4
0
00 01 10 11
Binary code
digital
code
vin
A/D
D/A
+
−
„
Quantization
noise
vnoise
LSB
Quantization noise exists even with
ideal A/D and D/A converters
L10: 6.111 Spring 2006
Introductory Digital Systems Laboratory
Vref
4
Vref
2
3Vref
4
Vref
v in
8
Non-idealities in Data Conversion
Offset
error
Ideal
Gain error – deviation of slope from ideal value
of 1
Analog
Analog
Offset – a constant voltage offset that appears
at the output when the digital input is 0
Binary code
Gain
error
Ideal
Binary code
Integral Nonlinearity – maximum deviation from Differential nonlinearity – the largest increment
the ideal analog output voltage
in analog output for a 1-bit change
Ideal
Analog
Analog
Integral
nonlinearity
Ideal
Nonmonoticity
Binary code
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Binary code
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R-2R Ladder DAC Architecture
-1
ƒ Note that the driving point impedance (resistance) is the same
for each cell.
„
R-2R Ladder achieves large current division ratios with only
two resistor values
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DAC (AD 558) Specs
„
8-bit DAC
„
Single Supply Operation: 5V to 15V
„
Integrates required references
(bandgap voltage reference)
„
Uses a R-2R resistor ladder
„
Settling time 1μs
„
Programmable output range from
0V to 2.56V or 0V to 10V
„
Simple Latch based interface
Image courtesy of Analog Devices. Used with permission.
L10: 6.111 Spring 2006
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Chip Architecture and Interface
D[7:0]
LATCH
CE
CS
Outputs are noisy
when input bits settles,
so it is best to have inputs
stable before latching
the input data
Image courtesy of Analog Devices. Used with permission.
L10: 6.111 Spring 2006
Introductory Digital Systems Laboratory
12
Setting the Voltage Range
Very similar to a
non-inverting amp
Strap output for
different voltage
ranges
Image courtesy of Analog Devices. Used with permission.
Convert data to
Offset binary
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Introductory Digital Systems Laboratory
13
Another Approach: Binary-Weighted DAC
R
b3
I
I
2
b2
I
4
b1
I
8
b0
+
vout
„
Switch binary-weighted
currents
„
MSB to LSB current ratio is 2N
vout = − IR(b3 + 12 b2 + 14 b1 + 18 b0 )
„
Analog Devices AD9768
uses two banks of
ratioed currents
„
Additional current
division performed by
750 Ω resistor between
the two banks
AD9768
Image courtesy of Analog Devices. Used with permission.
Reference current source
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Glitching and Thermometer D/A
„
Glitching is caused when
switching times in a D/A are not
synchronized
Binary
Thermometer
Example: Output changes from
011 to 100 – MSB switch is
delayed
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
„
Filtering reduces glitch but
increases the D/A settling time
1
1
1
1
1
„
One solution is a thermometer
code D/A – requires 2N – 1
switches but no ratioed
currents
„
vout
011→ 100
I
t
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R
T0
I
T1
T2
vout
I
vout = − IR(T0 + T1 + T2 )
Introductory Digital Systems Laboratory
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Successive-Approximation A/D
ƒ D/A converters are typically compact and easier to design. Why not A/D convert
using a D/A converter and a comparator?
ƒ D to A generates analog voltage which is compared to the input voltage
ƒ If D to A voltage > input voltage then set that bit; otherwise, reset that bit
ƒ This type of A to D takes a fixed amount of time proportional to the bit length
Vin
code
D/A
+ −
C
Comparator
out
L10: 6.111 Spring 2006
Example: 3-bit A/D conversion, 2 LSB < Vin < 3 LSB
Introductory Digital Systems Laboratory
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Successive-Approximation A/D
Data
D/A
Converter
N
Successive
Approximation
Generator
Done
vin
„
Sample/
Hold
+
Control
Go
Serial conversion takes a time equal to N(tD/A + tcomp)
L10: 6.111 Spring 2006
Introductory Digital Systems Laboratory
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Successive-Approximation A/D
(AD670)
Unipolar (BPO =0)
„
~10μs conversion time
Bipolar (BPO =1)
Image courtesy of Analog Devices. Used with permission.
L10: 6.111 Spring 2006
Introductory Digital Systems Laboratory
18
Single Write, Single Read Operation
(see data sheet for other modes)
tw
R/W
Write
CE, CS
Read
tDC
Status
Data
tc
Valid
tDT
tTD
Data Valid
tw (write/start pulse width) = 300ns (min)
tDC (delay to start conversion) = 700ns (max)
tc (conversion time) = 10μs (max)
tTD (Bus Access Time) = 250 (max)
tDT (Output Float Delay) = 150 (max)
ƒ Control bits CE and CS can be wired to ground if A/D is the only chip driving the bus
ƒ Suggestion: tie CE and CS pins together and hardwire BPO and Format
L10: 6.111 Spring 2006
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Simple A/D Interface FSM
cs_b
clk
CS
CE
r_w_b
reset
sample
FSM
status
R/W
AD670
STATUS
Data[7:0]
dataavail
Q D
Status should be
synchronized: why?
Courtesy of James Oey and
Cemal Akcaba
L10: 6.111 Spring 2006
Introductory Digital Systems Laboratory
Figure by MIT OpenCourseWare.
20
Example A/D Verilog Interface
module AD670 (clk, reset, sample, dataavail,
r_wbar, cs_bar, status, state);
// System Clk
input clk;
// Global Reset signal, assume it is synchronized
input reset;
// User Interface
input sample;
output dataavail;
always @ (posedge clk or negedge reset)
begin
if (!reset) state <=IDLE;
else state <=nextstate;
// A-D Interface
input status;
reg status_d1, status_d2;
output r_wbar, cs_bar;
output [3:0] state;
// internal state
reg [3:0] state;
reg [3:0] nextstate;
reg r_wbar_int, r_wbar;
reg cs_bar_int, cs_bar;
reg dataavail;
L10: 6.111 Spring 2006
// State declarations.
parameter IDLE = 0;
parameter CONV0 = 1;
parameter CONV1 = 2;
parameter CONV2 = 3;
parameter WAITSTATUSHIGH = 4;
parameter WAITSTATUSLOW = 5;
parameter READDELAY0 = 6;
parameter READDELAY1 = 7;
parameter READCYCLE = 8;
status_d1 <= status;
status_d2 <= status_d1;
r_wbar <= r_wbar_int;
cs_bar <=cs_bar_int;
end
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Example A/D Verilog Interface (cont.)
CONV2:
begin
r_wbar_int = 0;
cs_bar_int = 0;
nextstate = WAITSTATUSHIGH;
end
WAITSTATUSHIGH:
begin
cs_bar_int = 0;
if (status_d2) nextstate = WAITSTATUSLOW;
always @ (state or status_d2 or sample) begin
// defaults
r_wbar_int = 1; cs_bar_int = 1; dataavail = 0;
case (state)
IDLE: begin
if(sample) nextstate = CONV0;
else nextstate = IDLE;
end
else nextstate = WAITSTATUSHIGH;
end
CONV0:
begin
r_wbar_int = 0;
cs_bar_int = 0;
nextstate = CONV1;
end
WAITSTATUSLOW:
begin
cs_bar_int = 0;
if (!status_d2) nextstate = READDELAY0;
else nextstate = WAITSTATUSLOW;
end
CONV1:
begin
r_wbar_int = 0;
cs_bar_int = 0;
nextstate = CONV2;
end
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Example A/D Verilog Interface(cont.)
READDELAY0:
begin
cs_bar_int = 0;
nextstate = READDELAY1;
end
READDELAY1:
begin
cs_bar_int = 0;
nextstate = READCYCLE;
end
READCYCLE:
begin
cs_bar_int = 0;
dataavail = 1;
nextstate = IDLE;
end
default: nextstate = IDLE;
endcase // case(state)
end // always @ (state or status_d2 or sample)
endmodule // adcInterface
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Simulation
On reset, present state goes to 0
r_w_b must stay low for at least 3 cycles (@ 100ns period)
Enable read flip-flop
Status is synchronized – two register delays
Wait for ~10μs for status to go low
Sample pulse initiates
data conversion
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Notice a one cycle delay since A/D
control signal delayed through a register
Introductory Digital Systems Laboratory
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Flash A/D Converter
R
+
−
R
+
−
R
+
−
R
C
C
C
The rmom eter to binary
Vref vin
b0
b1
„
Brute-force A/D conversion
„
Simultaneously compare the
analog value with every
possible reference value
„
Fastest method of A/D
conversion
„
Size scales exponentially
with precision
(requires 2N comparators)
Comparators
Can be implemented as OpAmp in open loop
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Introductory Digital Systems Laboratory
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AD 775 – Flash Data Converter
Image courtesy of Analog Devices. Used with permission.
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High Performance Converters:
Use Pipelining and Parallelism!
Pipelining (used in video rate, RF basestations, etc.)
1-bit
Sample/
Hold
A/D
Converter
D/A
Converter
−
1-bit
Amplifier
2
+
Sample/
Hold
A/D
Converter
D/A
Converter
−
Amplifier
2
…
+
Parallelism (use many slower A/D’s in parallel to build very
high speed A/D converters)
1 GHz
Clock
[ISSCC 2003],
Poulton et. al.
DLL
1MByte SRAM
8 Mem Controllers
80 Slice Decimator
80 Radix Converters
CMOS
Buffer Chip
80 ADC Slices
Gen
80 T/Hs and V/Is
Clock
2 muxes
0.18-
CMOS ADC Chip
20Gsample/sec,
8-bit ADC
from Agilent Labs
Figure by MIT OpenCourseWare. Adapted from Poulten, Ken, et al. "A 20 GS/s 8b ADC with a 1MB Memory in 0.18um CMOS."
IEEE International Solid-State Circuits Conference Paper 18.1, 2003.
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New Trend: Eliminate OpAmps!
(Use Comparators, more digital…)
„
Op amps must achieve high
open-loop gain and fast
settling time under
feedback.
„
High gain becomes
increasingly difficult
achieve due to low device
gain.
„
Solution: Comparator
based analog Design
„
Dramatic power savings
possible
Courtesy of Prof. Harry Lee, ISSCC 2006. Used with permission.
L10: 6.111 Spring 2006
Introductory Digital Systems Laboratory
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Summary of Analog Blocks
„
Analog blocks are integral components of any
system. Need data converters (analog to digital
and digital to analog), analog processing
(OpAmps circuits, switched capacitors filters,
etc.), power converters (e.g., DC-DC
conversion), etc.
„
We looked at example interfaces for A/D and
D/A converters
† Make
etc.)
„
sure you register critical signals (enables, R/W,
Analog design incorporate digital principles
† Glitch
free operation using coding
† Parallelism and Pipelining!
† More advanced concepts such as calibration
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Introductory Digital Systems Laboratory
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