Stepper Motors
• DC motors with permanent motors and multiple
coils around the body.
• Coils are turned on and off in sequence to cause
the motor to turn.
• Because the coils are turned on and off they are
easy to control with microcomputer and digital
circuits. At any given time, the position of the
shaft is known.
• Holding torque requires power.
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1
Servos
• Servos are motors with electronic circuitry
that controls the angular position of the
shaft based on a control signal. If the
angle is incorrect the motor is turned on
until the correct position is reach.
• Angular position controlled by a 0 – 2.0 ms
pulse width.
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2
Schematic Drawing Convention
No connection
connection
connection
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3
Lab Exercise - Review
Ramp Generator
R
R
R
R
Vo
R
2R
2R
2R
2R
B0
+5
QA
7
10
+5
2
T
QA
QB
LD
4
2
14
13
B1
QB
12
9
1
1.8432
Mhz
crystal
osc.
P
74HC08
QC
11
QD
CLR
74LS163
counter
B2
QC
B3
QD
3
triangle is symbol
for clock input
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4
RAMP Generator Output
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5
DA Summary
• Output from digital to analog conversion
are discrete levels.
• More bits means better resolution.
• An example of DA conversion
– Current audio CD’s have 16 bit resolution or
65,536 possible output levels
– New DVD audio samples at 192 khz with 24
bit resolution or 224 = 16,777,216
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6
Analog to Digital Conversion (ADC)
• Successive approximate conversion steps
– Scale the input to 0-3 volts (example)
– Sample and hold the input
– Internally generate and star case ramp and compare
• Flash Compare
– Compare voltage to one of 2n possible voltage levels.
8 bit ADC would have 255 comparators.
• Note that by definition, ADC have quantizing
errors (number of bits resolution)
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Successive Approximation AD
6.091 Jan 2008
(6.111 L14, Fall ’05)
8
Binary Adder – mth bit
Cin
A
0
0
0
0
1
1
1
1
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0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
A
Sum Cout
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
B
Cin
Cout
ADDER
Sum
Sum =
Cout =
9
Switch Bounce
• All mechanical switches
have “switch bounce”
+5V
Vout
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10
Debounce Circuit
T
+5v
B
1K
Q
T
Qbar
Q
+5v
1K
SPDT
switch
B
Requires SPDT switch
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Qbar
T
Qbar
Q
0
0
1
0
1
1
1
0
1
Q
1
1
0
Qbar
T
0
B
1
11
Lab 5
• Design, build and keep
the electronics for a
digital lock.
• Unlock key based on
sequence of 0, 1.
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12
Digital Lock
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13
Pushbutton Clocking
+5v
1K
T
Q "1"
+5v
1K
SPDT
switch
B
Q "1"
Composite
clock
Q "0"
+5v
1K
T
Q "0"
composite
clock
+5v
.
1K
SPDT
switch
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B
14
Digital Lock
+5v
1K
“1” button will
clock in “1”
"1"
Button
T
+5v
1K
SPDT
switch
Either button
generates clk
B
QD
DATA
D
SET
CLR
+5v
Q
Q
QC
D
SET
CLR
Q
Q
QB
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
pin 1 +5
1K
+5V
"0"
button
T
470
+5v
1K
SPDT
switch
B
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Use 4 input NAND
gate to decode
74LS20
15
Design guidelines
• Apply power and ground to each
chip
• Add 10 uf or greater to power bus
• Select and wire up desired code
• For control inputs on all IC’s or
inputs that matter, tie to a “1” or a
“0”. Floating inputs are in an
indeterminate state.
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Construction Techniques
• Consider placement of IC’s
• Wire up power and ground to all IC’s
– Use all four power rails
• Build and debug in stages
– Debounce circuits
– Composite clock
– Shift registers
– Neat wiring helps!
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17
Enhancements
• Increase lock code to 8 bits
• Add power up reset
+5v
1K
power up
reset
1uf
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18
Lab 5
• Use last three aisle on the left at the
end of the 6.111 lab
• Pick up IC’s and tools from LA’s.
• You may keep the completed circuit
you build (pushbuttons, IC’s,
everything!)
• Return tools.
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Odds and Ends
• FPGA: Field Programmable Gate Array
– Use high level hardware description language (HDL)
to describe behavior
– Can be re-programmed thousands of times.
– very inexpensive kits
– free software tools on web
• Please complete your evaluation of this course
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