6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-1
Lecture 32 - The ”Short”
Metal-Oxide-Semiconductor Field-Effect
Transistor (cont.)
April 27, 2007
Contents:
1. MOSFET scaling
Reading assignment:
P. K. Ko, ”Approaches to Scaling.”
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-2
Key questions
• What happens if a MOSFET gate length is simply shrunk in size
without changing anything else?
• How should the MOSFET design change as it shrinks down in
size?
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-3
1. MOSFET scaling
Several driving forces for scaling down size of MOSFET:
• higher density circuits: SSI, MSI, LSI, VLSI, ULSI, RLSI, ...
• higher performance: L ↓⇒ ID ↑⇒ τswitch ↓
• lower power consumption: L ↓⇒ VDD ↓
Simple L scaling compromises electrostatic integrity and produces
punchthrough (extreme case of short-channel effects):
n+
n+
n+
n+
p
n+
n+
p
deep �
uncontrolled�
current
To avoid punchthrough:
• NA ↑⇒ VT ↑⇒ ID ↓
• VDD ↓⇒ ID ↓
• xox ↓⇒ VT ↓⇒ ID ↑
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-4
Image by MIT OpenCourseWare.
Adapted from Sze, S. M. Physics of Semiconductor Devices. 2nd ed.
New York, NY: John Wiley & Sons, 1981, p. 470. ISBN: 9780471056614.
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-5
Image by MIT OpenCourseWare.
Adapted from Sze, S. M. Physics of Semiconductor Devices. 2nd ed.
New York, NY: John Wiley & Sons, 1981, p. 481. ISBN: 9780471056614.
Need smart way of scaling:
• constant field scaling
• constant voltage scaling
• generalized scaling
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-6
� Constant field scaling
Scale keeping vertical and horizontal electric fields constant.
Define: scaling factor S > 1
parameter
scaling factor
device dimensions (L, W , xox )
1/S
doping level (NA )
S
supply voltage (VDD )
1/S
Consequences (use simple long-channel theory):
• gate capacitance:
�
�
Cgs
= Cox
L� W � = SCox
LW
Cgs
=
↓
S S
S
• threshold voltage:
VT�
1 �
VT
= VF B + φsth + γ φsth � � 2�sqNA� φsth ∼ √ ↓
Cox
S
�
• drive current:
ID�
W
W�
VDD VT 2 ID
�
�
� 2
= � µe Cox (VDD − VT ) = SL µe SCox (
−√ ) =
↓
2L
S
S
2S
S
• gate delay:
�
�
Cgs
VDD
τ =
=
ID�
�
Cgs VDD
S S
ID
S
=
τ
↓
S
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-7
• power-delay product or switching energy:
�
� 2
Cgs
VDD
2
Cgs VDD 2 Cgs VDD
=
(
) =
↓↓↓
S S
S3
• switching energy density:
�
� 2
Cgs
VDD
L� W �
=
2
Cgs VDD
S3
LW
S S
• inverse subthreshold slope:
n� = 1 +
�
Csth
�
Cox
= 1+
2
1 CgsVDD
=
↓
S LW
√
SCsth
Csth
= 1+ √
↓
SCox
SCox
but since VT ↓, Iof f ↑↑.
log ID
V'th
Vth
I'off
S-1
S'-1
Ioff
0
VGS
Two key problems with constant field scaling:
• system designers don’t want to scale VDD
• Ioff ↑↑⇒ more static power
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-8
� More rigorous study of constant field scaling using 2D simulations
[P. Vande Voorde, HP Journal, 1997]
-0.4
-0.4
-0.2
Lg
Distance (µm)
Distance (µm)
-0.2
Tox
0
Leff
0.2
-0.4
Xi
0
Distance (µm)
0
0.2
0.4
-0.4
-0.4
-0.2
-0.2
0
0
0.2
0.2
-0.4
0
Distance (µm)
0.4
-0.4
0
Distance (µm)
0.4
D
C
-0.4
-0.4
-0.2
-0.2
Distance (µm)
Distance (µm)
0.4
B
-0.4
Distance (µm)
Distance (µm)
A
0
Distance (µm)
0
0.2
0
0.2
-0.4
0
Distance (µm)
E
0.4
-0.4
0
Distance (µm)
0.4
F
Simulated device structures. Dark shading is Oxide. Lighter shading is Silicide. Dashed line are doping contours.
(a) Lg = 0.35 µm, Tox = 8.0 nm. (b) Lg = 0.25 µm, Tox = 6.0 nm. (c) Lg = 0.18 µm, Tox = 4.5 nm. (d) Lg = 0.13 µm,
Tox = 3.4 nm. (e) Lg = 0.10 µm, Tox = 2.5 nm. (f) Lg = 0.07 µm, Tox = 1.9 nm.
Image by MIT OpenCourseWare. Adapted from Figure 1 on p. 97 in Vande Voorde, Paul. "MOSFET
Scaling into the Future." Hewlett-Packard Journal (August 1997): 96-100.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-9
Scaling of power supply voltage Vdd and Oxide thickness Tox
8
3.5
Eox = 4 MV/cm
7
Tox
6
Power Supply (V)
2.5
Vdd
2.0
5
4
1.5
3
1.0
2
0.5
0
Gate Oxide Thickness (nm)
3.0
1
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0
0.40
Gate Length (µm)
Image by MIT OpenCourseWare. Adapted from Figure 2 on p. 98 in Vande Voorde, Paul.
"MOSFET Scaling into the Future." Hewlett-Packard Journal (August 1997): 96-100.
3.0
0.30
2.5
0.25
2.0
0.20
Leff
1.5
0.15
Xj
1.0
0.10
0.5
0
Extension Junction Depth (µm)
Effective Channel Length (µm)
Scaling of effective channel length Leff and extension junction depth Xj
0.25
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0
0.40
Gate Length (µm)
Image by MIT OpenCourseWare. Adapted from Figure 3 on p. 98 in Vande Voorde, Paul.
"MOSFET Scaling into the Future." Hewlett-Packard Journal (August 1997): 96-100.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-10
Scaling of maximum drain current and total gate capacitance
700
2.0
Drain current
1.8
600
500
1.4
Gate capacitance
400
1.2
1.0
300
0.8
0.6
200
0.4
100
0
Gate capacitance (fF/µm)
Drain current (µA/µm)
1.6
0.2
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0
0.40
Gate length (µm)
Image by MIT OpenCourseWare. Adapted from Figure 5 on p. 98 in Vande Voorde, Paul.
"MOSFET Scaling into the Future." Hewlett-Packard Journal (August 1997): 96-100.
0.7
1µ
0.6
100n
10n
0.5
1n
0.4
100p
Vt
0.3
Ioff
10p
0.2
1p
0.1
0
Off-state leakage current (A/µm)
Threshold voltage (V)
Scaling of threshold voltage Vt and off-state leakage current Ioff
100f
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
10f
0.40
Gate length (µm)
Image by MIT OpenCourseWare. Adapted from Figure 4 on p. 98 in Vande Voorde, Paul.
"MOSFET Scaling into the Future." Hewlett-Packard Journal (August 1997): 96-100.
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Inverter chain
Inverter delay versus gate length
Vdd
Vin
Lecture 32-11
200
2
1
Fanout = 7
Wn = 5 µm
Wp = 10 µm
100
Fanout = 3
Inverter delay (ps)
80
GND
Image by MIT OpenCourseWare. Adapted from Figure 8 on p. 99 in
Vande Voorde, Paul. "MOSFET Scaling into the Future."
Hewlett-Packard Journal (August 1997): 96-100.
Cload
150 pF
60
40
Fanout = 1
50 pF
20
0 pF
10
30% Improvement per generation
0.07 0.08 0.09 0.1
0.2
0.3
0.4
Gate length (µm)
Image by MIT OpenCourseWare. Adapted from Figure 10 on p. 99 in Vande Voorde, Paul.
"MOSFET Scaling into the Future." Hewlett-Packard Journal (August 1997): 96-100.
30
Fanout = 1
Wn = 5 µm
Wp = 10 µm
Inverter delay (ps)
25
Lg
0.18 µm
20
15
0.13 µm
0.10 µm
10
0.07 µm
5
0.4
0.5 0.6 0.7 0.8 0.9 1
2
3
Power supply (V)
Inverter delay versus power supply voltage. The stars show
the expected operating points. Wn and Wp are the widths of
the n-channel and p-channel transistors.
Image by MIT OpenCourseWare. Adapted from Figure 11 on p. 99 in Vande Voorde, Paul.
"MOSFET Scaling into the Future." Hewlett-Packard Journal (August 1997): 96-100.
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-12
� Constant voltage scaling
Scale all device dimensions but do not scale VDD .
parameter
scaling factor
device dimensions (L, W , xox )
1/S
doping level (NA )
S
1
supply voltage (VDD )
Consequences (using long-channel theory):
figure of merit scaling factor
Cgs
1/S
√
Vth
1/ S
ID
S
τ
1/S 2
2
Cgs VDD
1/S
2
CgsVDD
/LW
S
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-13
Features of constant voltage scaling:
• Performance ↑↑
• But:
– It does not address Ioff problem.
– Electric field across oxide ↑:
Eox =
VDD
∝S↑
xox
Reliability problems when Eox � 4 MV /cm.
– Electric field in semiconductor (at drain end of channel) ↑:
�
�
�
�
�
(VDS − VDSsat )2
2 ∝ S ↑
Em =
+ Esat
2
l
with
l2 =
�s
xox xj ∝ S −2
�ox
Reliability problems when Em � 0.5 MV /cm.
– Power density ↑ ⇒ system power ↑
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-14
� Generalized scaling
• scale oxide thickness more slowly than other device dimensions
• scale VDD keeping Eox constant
parameter scaling factor
L, W
1/S
1/R
xox
S
NA
1/R
VDD
with 1 < R < S.
In generalized scaling:
• Ioff problem alleviated by not scaling VT so aggresively;
trade-off: performance
• VDD scales;
trade-off: performance
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-15
100n
600
Vdd = 1V
500
Ioff
450
Drain
current
20n
10n
5n
2n
400
1n
500p
350
Off-state leakage current (A/µm)
550
Drain current (µA/µm)
50n
Lg = 0.1 µm
200p
300
0.15
0.20
0.25
0.30
0.35
100p
0.45
0.40
Threshold voltage (V)
Drain current and off-state leakage current Ioff versus
threshold voltage Vt for the 0.1-µm generation.
Image by MIT OpenCourseWare. Adapted from Figure 12 on p. 100 in Vande Voorde, Paul.
"MOSFET Scaling into the Future." Hewlett-Packard Journal (August 1997): 96-100.
Inverter delay versus threshold voltage Vt for the 0.1-µm generation
Inverter delay (ps)
100
90
80
70
60
Fanout = 7
CI
150 fF
Fanout = 3
50
40
30
50 fF
Fanout = 1
20
0 fF
10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
Threshold voltage (V)
Lg = 0.1 µm Vdd = 1V
Wn = 5 µm Wp = 10 µm
Image by MIT OpenCourseWare. Adapted from Figure 13 on p. 100 in Vande Voorde, Paul.
"MOSFET Scaling into the Future." Hewlett-Packard Journal (August 1997): 96-100.
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-16
Image by MIT OpenCourseWare. Adapted from Bohr, M. Semiconductor International (July 1995): 75.
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-17
� Modern generalized scaling
• Concept of generation: every 2 years, new technology is de­
ployed with 30% reduced transistor delay and twice as high
transistor density (microprocessor performance doubling every
2 years).
• Everything scales: L (↓), W (↓), xox (↓), NA (↑), xj (↓), and
VDD (↓).
• Scaling goal: extract maximum performance from each gen­
eration (maximize Ion ), for a given amount of:
– short-channel effects (DIBL), and
– off-current
• Currently two technology flavors:
– high-performance: high VDD (high ID , low τ ), low VT (high
Iof f );
– low-power: low VDD (low ID , high τ ), high VT (low Ioff ).
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-18
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6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007
Lecture 32-19
Key conclusions
• Constant field scaling: scale all device dimensions keeping ver­
tical and horizontal electric fields constant.
Consequences:
– Iof f ↑
– system designers don’t want to scale VDD
• Constant voltage scaling: scale all device dimensions keeping
voltage constant.
Consequences:
– Iof f ↑
– fields everywhere ↑ ⇒ reliability compromised
• For a long time scaling proceeded through constant VDD path
with abrupt drops in VDD .
• Scaling goal: extract maximum performance from each gen­
eration (maximize Ion ), for a given amount of:
– short-channel effects (DIBL), and
– off-current
• Generalized scaling demands simultaneous scaling of Lg , xox , xj , NA ,
and VDD .
Cite as: Jesús del Alamo, course materials for 6.720J Integrated Microelectronic Devices, Spring 2007.
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