6.776
High Speed Communication Circuits
Lecture 23
Design of Fractional-N Frequency Synthesizers and
Bandwidth Extension Techniques
Michael Perrott
Massachusetts Institute of Technology
May 4, 2005
Copyright © 2005 by Michael H. Perrott
Outline of PLL Lectures
ƒ
Integer-N Synthesizers
ƒ
Noise in Integer-N and Fractional-N Synthesizers
ƒ
Design of Fractional-N Frequency Synthesizers and
Bandwidth Extension Techniques
- Basic blocks, modeling, and design
- Frequency detection, PLL Type
- Noise analysis of integer-N structure
- Sigma-Delta modulators applied to fractional-N
structures
- Noise analysis of fractional-N structure
- PLL Design Assistant Software
- Quantization noise reduction for improved bandwidth
and noise
M.H. Perrott
MIT OCW 2
Design of Frequency Synthesizers
ƒ
Focus on fractional-N architecture since it is
essentially a “super set” of other PLL synthesizers
- If we can design this structure, we can also design
classical integer-N systems
ref(t)
PFD
e(t) Charge
Pump
Loop
Filter
out(t)
v(t)
VCO
div(t)
Nsd[m]
M.H. Perrott
Divider
Σ−∆
Modulator
N[m]
MIT OCW 3
Frequency-domain Model
PFD
Φref [k]
Tristate: α=1
XOR: α =2
α
T
e(t)
2π
Icp
H(f)
VCO
v(t)
KV
Φout(t)
jf
Divider
Φdiv[k]
1
Nnom
n[k]
ƒ
C.P.
Loop
Filter
1
T
Φd [k]
-1
z
2π
1 - z-1
j2πfT
z=e
Perrott et. al. JSSC, Aug. 2002
Closed loop dynamics parameterized by
M.H. Perrott
MIT OCW 4
Review of Classical Design Approach
Given the desired closed-loop bandwidth, order, and
system type:
1. Choose an appropriate topology for H(f)
ƒ Depends on order, type
2. Choose pole/zero values for H(f) as appropriate for the
required bandwidth
3. Adjust the open-loop gain to achieve the required
bandwidth while maintaining stability
ƒ Plot gain and phase bode plots of A(f)
ƒ Use phase (or gain) margin criterion to infer
stability
M.H. Perrott
MIT OCW 5
Example: First Order, Type I with Parasitic Poles
Evaluation of
Phase Margin
Closed Loop Pole
Locations of G(f)
Im(s)
20log|A(f)|
Open loop
gain
increased
C
Dominant
pole pair
0 dB
f
fp fp2fp3
B
Non-dominant
poles
\A(f)
-90
C
B
A
Re(s)
A
o
o
0
A
PM = 72 for A
PM = 51o for B
B
o
-165
o
-180
-240
o
-315
o
M.H. Perrott
PM = -12o for C
C
MIT OCW 6
First Order, Type I: Frequency and Step Responses
Closed Loop Step Response
Closed Loop Frequency Response
C
C
2
0 dB
B
B
A
1
A
0
Frequency
M.H. Perrott
Time
MIT OCW 7
Limitations of Open Loop Design Approach
ƒ
ƒ
ƒ
ƒ
Constrained for applications which require precise
filter response
Complicated once parasitic poles are taken into
account
Poor control over filter shape
Inadequate for systems with third order rolloff
- Phase margin criterion based on second order systems
Closed loop design approach:
Directly design G(f) by specifying dominant pole and
zero locations on the s-plane (pole-zero diagram)
M.H. Perrott
MIT OCW 8
Closed Loop Design Approach: Overview
ƒ
G(f) completely describes the closed loop dynamics
- Design of this function is the ultimate goal
Performance
Specifications
{type, fo, ...}
Open Loop
Design
Approach
G(f) =
|A(f)|
\A(f)
{K, fzA, fpA, ...}
A(f)) =
A(f)
1+A(f)
G(f)
G(f)
{fz , fp , ...}
11-G(f)
Closed Loop Design Approach
ƒ
ƒ
ƒ
Instead of indirectly designing G(f) using plots of A(f),
solve for G(f) directly as a function of specification
parameters
Solve for A(f) that will achieve desired G(f)
Account for the impact of parasitic poles/zeros
M.H. Perrott
MIT OCW 9
Closed Loop Design Approach: Implementation
ƒ
ƒ
ƒ
Download PLL Design Assistant Software at
http://www-mtl.mit.edu/research/perrottgroup/tools.html
Read accompanying manual
Algorithm described by C.Y. Lau et. al. in “Fractional-N
Frequency Synthesizer Design at the Transfer Function
Level Using a Direct Closed Loop Realization
Algorithm”, Design Automation Conference, 2003
M.H. Perrott
MIT OCW 10
PLL Design Assistant
M.H. Perrott
MIT OCW 11
Definition of Bandwidth, Order, and Shape for G(f)
0
G(f)
(dB)
ƒ
Bandwidth – fo
ƒ
Order – n
ƒ
Shape
fo
f
rolloff =
-20n
dB/decade
- Defined in asymptotic manner as shown
- Defined according to the rolloff characteristic of G(f)
- Defined according to standard filter design
methodologies
ƒ Butterworth, Bessel, Chebyshev, etc.
M.H. Perrott
MIT OCW 12
Definition of Type
ƒ
ƒ
Type I: one integrator in PLL open loop transfer
function
- VCO adds on integrator
- Loop filter, H(f), has no integrators
Type II: two integrators in PLL open loop transfer
function
- Loop filter, H(f), has one integrator
Tristate: α=1
PFD XOR-based: α=2
Φref(t)
Φdiv(t)
M.H. Perrott
α
2π
Loop Filter
e(t)
H(f)
VCO
v(t)
Kv
jf
Φout(t)
Divider
1
N
MIT OCW 13
Loop Filter Transfer Function Vs Type and Order of G(f)
H(s) Topology For Different Type and Orders of G(f)
Type I
Order 1
Order 2
Order 3
Type II
KLP
KLP
KLP
KLP
1+s/wp
1+s/wz
s(1+s/wp)
KLP(1+s/wz)
KLP
1+s/(wpQp)+(s/wp)
1+s/wz
s
2
where KLP = K
s(1+s/(wpQp)+(s/wp)2)
Nnom
KvIcpα
Calculated from software
ƒ
Practical PLL implementations limited to above
ƒ
Open loop gain, K, will be calculated by algorithm
- Prohibitive analog complexity for higher order, type
Loop filter gain related to open loop gain as shown above
M.H. Perrott
MIT OCW
14
Passive Topologies to Realize a Second Order PLL
Type I, Order 2
DAC
Idac
Vout
Iin
Vout
Iin
C1
Vout
Iin
ƒ
Type II, Order 2
=
C1
R1
R1
1+sR1C1
Vout
Iin
=
1
R1
C2
1+sR1C2
s(C1+C2) 1+sR1C||
DAC is used for Type I implementation to coarsely
tune VCO
- Allows full range of VCO to be achieved
M.H. Perrott
MIT OCW 15
Passive Topologies to Realize a Third Order PLL
Type I, Order 3
Idac
DAC
L1
Iin
C1
Vout
Iin
Type II, Order 3
=
L1
Iin
Vout
C1
Vout
R1
C2
R1
R1
2
1+sR1C1+s L1C1
Vout
Iin
=
1
1+sR1C2
s(C1+C2) 1+sR1C||+s2L1C||
where C||= C1C2/(C1+C2)
ƒ
Inductor is necessary to create a complex pole pair
- Must be implemented off-chip due to its large value
M.H. Perrott
MIT OCW 16
Problem with Passive Loop Filter Implementations
ƒ
Large voltage swing required at charge pump output
ƒ
Non-ideal behavior of inductors (for third order G(f)
implementations)
- Must support full range of VCO input
- Hard to realize large inductor values
- Self resonance of inductor reduces high frequency
attenuation
Cp
L1
L1
Alternative: active loop filter implementation
M.H. Perrott
MIT OCW 17
Guidelines for Active Loop Filter Design
ƒ
Use topologies with unity
gain feedback in the
opamp
- Minimizes influence of
opamp noise
R1
ƒ
Perform level shifting in
feedback of opamp
- Fixes voltage at charge
pump output
Use current
to achieve
level shift
R2
Level
Shift
Element
2
Vnoise,in
Vout
Set nominal
voltage to Vref
Vout
Vref
ƒ
Prevent fast edges from directly reaching opamp inputs
- Will otherwise cause opamp to be driven into nonlinear
region of operation
M.H. Perrott
MIT OCW 18
Active Topologies To Realize a Second Order PLL
Type I, Order 2
DAC
Idac
Type II, Order 2
R2
C2
Iin
C3
Vout
Iin
C1
R1
Vref
Iin
R1
C1
Vref
Vref
Vout
Iin
ƒ
ƒ
=
Vout
R1
1+sR1C1
Vout
Iin
=
1+sR1(C1+C2+C3)
sC2(1+sR1C1)
Follows guidelines from previous slide
Charge pump output is terminated directly with a high
Q capacitor
- Smooths fast edges from charge pump before they
reach the opamp input(s)
M.H. Perrott
MIT OCW 19
Active Topologies To Realize a Third Order PLL
Type I, Order 3
Type II, Order 3
C2
DAC
C2
R1
Idac
R2
R1
C1
Iin
Vout
Vref
Iin
=
R2
C1
Iin
Vout
Vout
C3
Vref
-R2
Vout
1+s(R1+R2)C2+s2R1R2C1C2
Iin
=
-1
1+sR2C3
s(C1+C2) 1+sC||(R1(1+C1/C3)+R2)+s2R1R2C1C||
where C||= C2C3/(C2+C3)
ƒ
Follows active implementation guidelines from a few
slides ago
M.H. Perrott
MIT OCW 20
Example Design
ƒ
Type II, 3rd order, Butterworth, fo = 300kHz, fz/fo = 0.125
ƒ
Required loop filter transfer function can be found from
table:
- No parasitic poles
M.H. Perrott
MIT OCW 21
Use PLL Design Assistant to Calculate Parameters
M.H. Perrott
MIT OCW 22
Resulting Step Response and Pole/Zero Diagram
M.H. Perrott
MIT OCW 23
Impact of Open Loop Parameter Variations
ƒ
Open loop parameter variations can be directly entered
into tool
M.H. Perrott
MIT OCW 24
Resulting Step Responses and Pole/Zero Diagrams
ƒ
Impact of variations on the loop dynamics can be
visualized instantly and taken into account at early
stage of design
M.H. Perrott
MIT OCW 25
Design with Parasitic Pole
ƒ
Include a parasitic pole at nominal value fp1 = 1.2MHz
Ö K, fp and
Qp are adjusted to obtain the same dominant
pole locations
M.H. Perrott
MIT OCW 26
Noise Estimation
ƒ
Phase noise plots can be easily obtained
Jitter calculated by integrating over frequency
range
-
M.H. Perrott
MIT OCW 27
Calculated Versus Simulated Phase Noise Spectrum
Without parasitic pole:
60
Output Phase Noise of Synthesizer
SD Noise
Detector Noise
VCO Noise
Total Noise
Simulated Noise
80
100
120
100
120
140
140
160
160
180 4
10
105
106
Frequency Offset (Hz)
107
Simulated Phase Noise of SD Freq. Synth.
80
L(f) (dBc/Hz)
L(f) (dBc/Hz)
60
108
180 4
10
105
106
Frequency Offset (Hz)
107
108
RMS jitter = 13.791ps
M.H. Perrott
MIT OCW 28
Calculated Versus Simulated Phase Noise Spectrum
With parasitic pole at 1.2 MHz:
Output Phase Noise of Synthesizer
60
SD Noise
Detector Noise
VCO Noise
Total Noise
Simulated Noise
80
100
120
100
120
140
140
160
160
180
104
105
106
Frequency Offset (Hz)
107
Simulated Phase Noise of SD Freq. Synth.
80
L(f) (dBc/Hz)
L(f) (dBc/Hz)
60
108
180 4
10
105
106
107
108
Frequency Offset from Carrier (Hz)
RMS jitter = 14.057ps
M.H. Perrott
MIT OCW 29
Noise under Open Loop Parameter Variations
60
Output Phase Noise of Synthesizer
SD Noise
Detector Noise
VCO Noise
Total Noise
L(f) (dBc/Hz)
80
100
120
140
160
180 4
10
105
106
107
108
Frequency Offset (Hz)
RMS jitter = 11.678ps (min), 18.211ps (max)
ƒ
Impact of open loop parameter variations on phase
noise and jitter can be visualized immediately
M.H. Perrott
MIT OCW 30
Conclusion
ƒ
New closed loop design approach facilitates:
ƒ
Techniques implemented in a GUI-based CAD tool
ƒ
Beginners can quickly come up to speed in designing
PLL’s
Experienced designers can quickly evaluate the
performance of different PLL configurations
ƒ
- Accurate control of closed loop dynamics
ƒ Bandwidth, Order, Shape, Type
- Straightforward design of higher order PLL’s
- Direct assessment of impact of parasitic poles/zeros
M.H. Perrott
MIT OCW 31
Bandwidth Extension of Fractional-N Frequency
Synthesizers
M.H. Perrott
MIT OCW
Impact of Σ−∆ Quantization Noise on Synth. Output
Ref
PFD
Loop
Filter
Div
Frequency
Selection
M-bit
Out
N/N+1
Σ−∆
Modulator
1-bit
Quantization
Noise Spectrum
Output
Spectrum
Frequency
Selection
Fout
Σ−∆
ƒ
Noise
PLL dynamics
Lowpass action of PLL dynamics suppresses the
shaped Σ-∆ quantization noise
M.H. Perrott
MIT OCW 33
Impact of Increasing the PLL Bandwidth
Ref
PFD
Loop
Filter
Div
Frequency M-bit
Selection
Out
N/N+1
Σ−∆
Modulator
1-bit
Quantization
Noise Spectrum
Output
Spectrum
Frequency
Selection
ƒ
Noise
Fout
Σ−∆
PLL dynamics
Higher PLL bandwidth leads to less quantization noise suppression
Tradeoff: Noise performance vs PLL bandwidth
M.H. Perrott
MIT OCW 34
Recent Approaches to Bandwidth Extension
ƒ
ƒ
ƒ
ƒ
[1] C. Park, O. Kim, and B. Kim, “A 1.8GHz SelfCalibrated Phase-Locked Loop with Precise I/Q
Matching,” IEEE JSSC, May 2001.
[2] K. Lee, et. al., “A Single Chip 2.4GHz DirectConversion CMOS Receiver for Wireless Local Loop
Using Multiphase Reduced Frequency Conversion
Technique ,” IEEE JSSC, May 2001.
[3] S. Pamarti, L. Jansson, and I. Galton, “A Wideband
2.4GHz Delta-Sigma Fractional-N PLL With 1Mb/s InLoop Modulation”, IEEE JSSC, Jan 2004
[4] E. Temporiti, et. al., “A 700kHz Bandwidth Σ−∆
Fractional-N Frequency Synthesizer with Spurs
Compensation and Linearization Techniques for
WCDMA Applications”, IEEE JSSC, Sept 2004
We will focus on our own approach in this talk
M.H. Perrott
MIT OCW 35
Examine Classical Fractional-N Signals
ref(t)
div(t)
e(t)
1
4
2
4
3
4
0
4
1
4
Se(f)
2
4
3
4
Fractional
Spurs
f
0
ƒ
Fref
Goal: eliminate the fractional spurs
M.H. Perrott
MIT OCW 36
Method 1: Vertical Compensation
ref(t)
div(t)
e(t)
1
4
2
4
3
4
0
4
1
4
2
4
3
4
e(t)
3
4
1
4
2
4
2
4
1
4
3
4
4
4
0
4
3
4
1
4
2
4
2
4
1
4
3
4
Se(f)
f
0
ƒ
Fref
“Fill in” pulses so that they are constant area
- Fractional spurs are eliminated!
M.H. Perrott
MIT OCW 37
Method 2: Horizontal Compensation
ref(t)
div(t)
e(t)
1
4
2
4
3
4
0
4
1
4
2
4
3
4
e(t)
3
4
1
4
2
4
2
4
1
4
3
4
4
4
0
4
3
4
1
4
2
4
2
4
1
4
3
4
3
4
1
4
2
4
2
4
1
4
3
4
4
4
0
4
3
4
1
4
2
4
2
4
1
4
3
4
e(t)
ƒ
Use constant width pulses of
varying height to achieve constant
area pulses
- Largely eliminates fractional spurs
M.H. Perrott
Se(f)
f
0
Fref
MIT OCW 38
Implementation of Horizontal Cancellation
ƒ
We begin with the basic fractional-N structure
ref(t)
Loop
Filter
PFD
out(t)
e2(t)
div(t)
ref(t)
div(t)
e2(t)
Reg
M.H. Perrott
Divider
N[k]
MIT OCW 39
Add a Second PFD with Delayed Divider Signal
ref(t)
delayed
div(t)
e1(t)
ref(t)
PFD
e1(t)
delayed
div(t)
Loop
Filter
PFD
out(t)
e2(t)
div(t)
ref(t)
div(t)
e2(t)
Reg
M.H. Perrott
Reg
Divider
N[k]
MIT OCW 40
Scale Error Pulses According to Accumulator Residue
ref(t)
delayed
div(t)
ε[k]e1(t)
ref(t)
ε[k]e1(t)
ε[k]
PFD
delayed
div(t)
Loop
Filter
PFD
1-ε[k]
out(t)
(1-ε[k])e2(t)
div(t)
ref(t)
div(t)
(1-ε[k])e2(t)
Reg
frac[k]
Accum
M.H. Perrott
Reg
Divider
residue[k] = ε[k]
MIT OCW 41
A Closer Look at Adding the Scaled Error Pulses
ref(t)
PFD
ε[k]
delayed
div(t)
ε[k]e1(t)
e(t)
PFD
1-ε[k]
(1-ε[k])e2(t)
div(t)
(1-ε[k])e2(t)
ε[k]e1(t)
e(t)
ƒ
Goal – keep area constant for each pulse
- It’s easier to see this from a slightly different viewpoint
M.H. Perrott
MIT OCW 42
Alternate Viewpoint
ƒ
The sum of scaled pulses can now be viewed as
horizontal cancellation
ref(t)
ε[k]
PFD
ε[k]e1(t)
delayed
div(t)
e(t)
1-ε[k]
PFD
(1-ε[k])e2(t)
div(t)
(1-ε[k])e2(t)
ε[k]e1(t)
e(t)
e(t)
M.H. Perrott
3
4
1
4
2
4
2
4
1
4
3
4
4
4
0
4
3
4
1
4
2
4
2
4
1
4
3
4
MIT OCW 43
Implementation of Pulse Scaling Operation
ƒ
Direct output of a differential current DAC into two
charge pumps
ref(t)
PFD
delayed
div(t)
div(t)
Charge
Pump
ε[k]
PFD
Charge
Pump
ε[k]e1(t)
Loop
Filter
(1-ε[k])e2(t)
1-ε[k]
Residue[k]
2n
ƒ
Y. Dufour
US Patent 6,130,561
1998 (filing date)
Issue: practical non-idealities kill performance
M.H. Perrott
MIT OCW 44
Primary Non-idealities of Concern
Incomplete Fractional
Spur Suppression
Delay mismatch
ref(t)
Tvco+∆
PFD
delayed
div(t)
div(t)
Charge
Pump
ε[k]
PFD
Charge
Pump
1-ε[k]
Residue[k]
e(t)
Se(f)
0
Fref
f
2n
DAC current
element mismatch
Proposed approach: dramatically reduce impact of these
non-idealities using mixed-signal processing techniques
M.H. Perrott
MIT OCW 45
Eliminate Impact of DAC Current Element Mismatch
ƒ
Apply standard DAC noise shaping techniques to
shape mismatch noise to high frequencies
- See Baird and Fiez, TCAS II, Dec 1995
ref(t)
PFD
delayed
div(t)
div(t)
ε[k]
Residue[k]
n+1
ƒ
DAC
Mismatch
Shaping
Charge
Pump
ε[k]
PFD
Charge
Pump
ε[k]e1(t)
Loop
Filter
(1-ε[k])e2(t)
1-ε[k]
2n
Allows up to 5% mismatch between unit elements
without degrading our desired performance targets
M.H. Perrott
MIT OCW 46
Eliminate Impact of Timing Mismatch
ƒ
Swap paths between divider outputs in a pseudorandom fashion
Need to also swap ε[k] and 1-ε[k] sequence
-
ref(t)
vco_out(t)
PFD
Tvco+∆
delayed
div(t)
div(t)
Timing Mismatch
Compensation and
Re-synchronization
ε[k]
Residue[k]
n+1
ƒ
DAC
Mismatch
Shaping
Charge
Pump
ε[k]
PFD
Charge
Pump
ε[k]e1(t)
Loop
Filter
(1-ε[k])e2(t)
1-ε[k]
2n
Allows up to 5 ps mismatch without degrading our
desired performance targets
M.H. Perrott
MIT OCW 47
Improve Horizontal Cancellation Performance
ƒ
Sampling circuit accumulates error pulses before
passing their information to the loop filter
- A common analog trick used for decades
ref(t)
vco_out(t)
PFD
delayed
div(t)
div(t)
Timing Mismatch
Compensation and
Re-synchronization
ε[k]
Residue[k]
n+1
ƒ
DAC
Mismatch
Shaping
2n
Charge
Pump
ε[k]
PFD
Sampler
Charge
Pump
1-ε[k]
Se(f)
0
Eliminates issue of having non-square error pulse
shapes
M.H. Perrott
Loop
Filter
Fref
f
MIT OCW 48
For More Details on This Approach
ƒ
Theory and simulations presented in TCAS II paper
- Meninger and Perrott, TCASII, Nov 2003
ref(t)
vco_out(t)
PFD
delayed
div(t)
div(t)
Timing Mismatch
Compensation and
Re-synchronization
ε[k]
Residue[k]
n+1
DAC
Mismatch
Shaping
M.H. Perrott
2n
Charge
Pump
ε[k]
PFD
Sampler
Loop
Filter
Charge
Pump
1-ε[k]
Se(f)
0
Fref
f
MIT OCW 49
Design and Simulation of ‘PFD/DAC’ Synthesizer
ref(t)
div(t)
Reg
frac[k]
PFD/DAC
Reg
Loop
Filter
out(t)
Divider
Accum
residue[k] = ε[k]
ƒ
ƒ
ƒ
ƒ
Step 1:
Step 2:
Step 3:
Step 4:
Derive analytical model
Design at system level
Simulate at system level (CppSim)
Simulate at transistor level (SPICE)
Iterate between all of these steps in practice
M.H. Perrott
MIT OCW 50
Analytical Model of ‘PFD/DAC’ Fractional-N PLL
VCO-referred
Noise
S Φvn(f)
-20 dB/dec
PFD-referred
Noise
S En(f)
1/T
0
PFD Tristate: α=1
Φref [k]
α
0
C.P.
e(t)
T
2π
Icp
Loop
Filter
H(f)
VCO
v(t)
KV
f
Φvn(t)
Φout(t)
jf
Divider
Φdiv[k]
S q(e
en(t)
f
1
Nnom
j2πfT
)
Φd [k]
∆
Σ−∆
Quantization
Noise
n[k]
0
∆: 1
1
T
f
2π
z-1
1 - z-1
j2πfT
z=e
Based on:
Perrott et. al.,
JSSC, Aug. 2002
(1/2) n
n-bit PFD/DAC → ∆ is reduced from 1 to (1/2)n
M.H. Perrott
MIT OCW 51
Parameterized PLL Model
VCO-referred
Noise
S Φvn(f)
PFD-referred
Noise
S En(f)
Σ−∆
Quantization
Noise
1/T
0
∆
fo
f
0
Φvn(t)
2π
α NnomG(f)
fo
1-G(f)
f
0
(1/2)
n[k]
M.H. Perrott
f
En(t)
S q(ej2πfT)
∆: 1
-20 dB/dec
n
Φ [k]
-1
n
2π z -1
1-z
z=ej2πfT
T G(f)
Φdiv(t)
Φtn,pll(t)
Φout(t)
fo
MIT OCW 52
Application:
A 1 MHz Bandwidth Fractional-N Frequency
Synthesizer Implementation
M.H. Perrott
MIT OCW
Design Goals
ƒ
Output frequency: 3.6 GHz
ƒ
Reference frequency: 50 MHz
ƒ
Bandwidth: 1 MHz
ƒ
Noise: < -150 dBc/Hz at 20 MHz offset (3.6 GHz carrier)
- Allows dual-band output (1.8 GHz and 900 MHz)
- Allows low cost crystal reference
- Allows fast settling time and ~1 Mbit/s modulation rate
- Phase noise at the 20 MHz frequency offset is very
challenging for GSM and DCS transmitters
ƒ GSM: -162 dBc/Hz at 20 MHz offset (900 MHz carrier)
ƒ DCS: -151 dBc/Hz at 20 MHz offset (1.8 GHz carrier)
Simultaneous achievement of the above bandwidth
and noise targets is very challenging
M.H. Perrott
MIT OCW 54
Evaluate Noise Performance with 1 MHz PLL BW
ƒ
G(f) parameters
- 1 MHz BW, Type II, 2
nd
ƒ
order rolloff, extra pole at 2.5 MHz
Required PLL noise parameters (with a few dB of margin)
- Output-referred charge pump noise: -105 dBc/Hz
- VCO noise: -155 dBc/Hz at 20 MHz offset (3.6 GHz carrier)
M.H. Perrott
MIT OCW 55
Calculated Phase Noise for Classical Fractional-N
2nd Order Σ−∆
-132 dBc/Hz at 20 MHz
3rd Order Σ−∆
These do NOT meet
our target of
-150 dBc/Hz at 20 MHz
(3.6 GHz carrier freq.)
M.H. Perrott
-126 dBc/Hz at 20 MHz
MIT OCW 56
Calculated Phase Noise for 7-bit PFD/DAC Synth
7-bit PFD/DAC
-155 dBc/Hz at 20 MHz !
M.H. Perrott
MIT OCW 57
Simulation of PFD/DAC Synthesizer using CppSim
ƒ
Phase noise plots to follow: 40e6 time steps in 10 min
M.H. Perrott
MIT OCW 58
Intrinsic PLL Noise Performance
ref(t)
div(t)
Reg
PFD/DAC
Reg
Loop
Filter
out(t)
Divider
frac[k] = 0
Accum
ƒ
ƒ
residue[k] = 0
Set fractional portion of divide value to zero
- Leads to residue variation of zero
ƒ No quantization noise!
Need to calculate and simulate impact of detector and VCO
noise
In essence, operate as integer-N synthesizer
M.H. Perrott
MIT OCW 59
Calculate Intrinsic PLL Noise Sources
ƒ
Estimate detector noise (dominated by charge pump)
- From SPICE Simulation, S (f) = Duty*3e-22 A /Hz
- Output-referred PLL noise due to above noise:
Icp
ƒ
2
Estimate VCO noise
- For off-chip VCO, examine data sheet:
ƒ In this case, S
= -155 dBc/Hz at 20 MHz offset
- For on-chip VCO, use Spectre RF or other CAD tool
Φvco
M.H. Perrott
MIT OCW 60
Calculate PLL Noise Due to Intrinsic Noise Sources
ƒ
We will see that we
will need to include:
- Reference noise
- 1/f noise
M.H. Perrott
MIT OCW 61
Simulated Phase Noise due to Intrinsic Noise Sources
CppSim Simulated Phase Noise for Cell: wb_synth, Lib: WBSynth_Example, Sim: test_int_n.par
freqfilt
-49
Reference Spur
≈ -50 dBc at 50 MHz
-100
L(f) (dBc/Hz)
-110
-69
-120
-79
-130
-89
-140
-99
Detector Noise
VCO Noise
Total Noise
-150
-109
-160
-119
-170
-129
-180
-139
0.1
ƒ
-59
Spurs (dBc)
-90
1
10
Frequency Offset from Carrier (MHz)
PLL Design Assistant accurately models simulated noise!
M.H. Perrott
MIT OCW 62
2nd Order Σ−∆ Fractional-N Performance
ref(t)
div(t)
Reg
frac[k]
ƒ
ƒ
2nd order
Σ−∆
PFD/DAC
Reg
Loop
Filter
out(t)
Divider
residue[k] = 0
Replace accumulator with second order Σ−∆ modulator
Set residue into PFD/DAC equal to zero
M.H. Perrott
MIT OCW 63
Calculate PLL Noise for 2nd Order Σ−∆ Synthesizer
ƒ
2nd order Σ−∆
- Click on 2
order
S-D quantization
noise in tool
nd
M.H. Perrott
MIT OCW 64
Simulated Phase Noise of 2nd Order Σ−∆ Synthesizer
CppSim Simulated Phase Noise for Cell: wb_synth_sd2, Lib: WBSynth_Example, Sim: test.par
-80
-39
-100
-59
-120
-79
-140
-99
Spurs (dBc)
L(f) (dBc/Hz)
freqfilt
SD Noise
Detector Noise
VCO Noise
Total Noise
-160
-119
-180
-139
0.1
ƒ
1
10
Frequency Offset from Carrier (MHz)
PLL Design Assistant accurately models simulated noise!
M.H. Perrott
MIT OCW 65
7-bit PFD/DAC Synthesizer Performance
Delay mismatch
ref(t)
vco_out(t)
PFD
Tvco+∆
delayed
div(t)
div(t)
Timing Mismatch
Compensation and
Re-synchronization
ε[k]
Residue[k]
n+1
DAC
Mismatch
Shaping
2n
Charge
Pump
ε[k]
PFD
Sampler
Loop
Filter
Charge
Pump
1-ε[k]
DAC
current
element
mismatch
Application of proposed noise scrambling/shaping
techniques leads to broadband noise from delay and
DAC current mismatch
M.H. Perrott
MIT OCW 66
Impact on PLL Noise due to Non-idealities of PFD/DAC
ƒ
Impact of DAC mismatch
ƒ
Impact of delay mismatch
- Lowers achievable quantization noise suppression
- Negligible in this case
- Model as white reference noise uniformly distributed from
0 to ∆t
ƒ Calculation for ∆t = 5 ps:
M.H. Perrott
MIT OCW 67
Calculate PLL Noise for 7-bit PFD/DAC Synthesizer
ƒ
ƒ
M.H. Perrott
PFD/DAC
- Adjust S-D Quant.
Noise
Delay mismatch
- Adjust Detector noise
MIT OCW 68
Simulated PLL Phase Noise of 7-bit PFD/DAC
ƒ
PLL Design Assistant accurately models simulated noise!
M.H. Perrott
MIT OCW 69
Summary of Design/Simulation Results
ƒ
The PLL Design Assistant can be used to model the
impact of
- Intrinsic PLL noise sources
- Quantization noise due to Σ−∆ dithering of divide value
- Suppression of quantization noise by n-bit PFD/DAC
- Impact of delay and current mismatch on PLL phase
ƒ
noise
CppSim simulations confirm the accuracy of the
above analysis
How do PLL Design Assistant calculations
compare to measured results?
M.H. Perrott
MIT OCW 70
A 1 MHz BW Fractional-N Frequency Synthesizer IC
Scott Meninger
ƒ
Implements
proposed 7-bit
PFD/DAC
structure
- 0.18u CMOS
- Circuit details
to be published
in the future
Funded by
MARCO C2S2
Fabricated by
National
Semiconductor
M.H. Perrott
MIT OCW
Measured vs Calculated Phase Noise (Integer-N)
ƒ
Calculated noise is way off!
Issue:
M.H. Perrott
we did not consider reference jitter and 1/f noise
MIT OCW 72
Adjustment of Calculations to Fit Measured Result
ƒ
Calculated noise now assumes:
-
Detector noise is -107 dBc/Hz with 1/f corner of 130 kHz
M.H. Perrott
MIT OCW 73
Back Extraction of Reference Jitter
Accounts for PFD structure
with reduced iup
ƒ
Assuming G(f) = 1:
ƒ
Assuming Nnom = 73, T = 1/50MHz, iup/idown = 1/5
⇒ ∆tjitt = 3.08ps
M.H. Perrott
MIT OCW 74
7-bit PFD/DAC Synthesizer Vs Integer-N Configuration
ƒ
Left: Phase swapping enabled
ƒ
Right: Phase swapping disabled
- Timing mismatch converted into broadband noise
More fractional spurs, lower broadband noise
M.H. Perrott
MIT OCW 75
Adjustment of Calculations to fit Measured Results
ƒ
Calculated noise now assumes:
- Detector noise is -100 dBc/Hz with 1/f corner of 20 kHz
M.H. Perrott
MIT OCW 76
Back Extraction of Timing Mismatch Using the Model
ƒ
Assuming G(f) = 1:
ƒ
Assuming Nnom = 73, T = 1/50MHz ⇒ ∆t2 = 10.7 ps
M.H. Perrott
MIT OCW 77
Measured Noise Suppression
ƒ
ƒ
ƒ
Comparison of 7-bit PFD/DAC synthesizer with 2nd order Σ∆
Synthesizer
Low freq noise ~2dB worse because of phase swapping
29dB quantization noise suppression measured at 10MHz !
M.H. Perrott
MIT OCW 78
Measured Noise Suppression: No Swapping
ƒ
ƒ
Demonstrates that timing mismatch is degrading our
maximum suppression by 2 dB (when swapping)
Spurs occur due to gain error from timing mismatch
M.H. Perrott
MIT OCW 79
Summary of Calculation/Measured Results Comparison
ƒ
Comparison of PLL Design Assistant results to
measured data allow back extraction of key
parameters:
- Intrinsic noise
ƒ Detector and VCO noise
- PFD/DAC nonidealities
ƒ
ƒ Delay mismatch value
Future work: better low frequency noise accuracy
M.H. Perrott
MIT OCW 80
Conclusions
ƒ
Fractional-N frequency synthesizers are about to
undergo dramatic improvement in achieving high PLL
bandwidth with excellent noise performance
- The PFD/DAC approach presented here is only one of
ƒ
many possibilities to achieve this goal
Design and simulation methodologies are starting to
emerge
- Analytical modeling of noise can be quite accurate
ƒ The PLL Design Assistant can be useful in this area
- Behavioral simulation can be used to verify analytical
models
ƒ CppSim offers a convenient and fast framework for this
Research into High Bandwidth PLL
Architectures is at an Exciting Crossroads
M.H. Perrott
MIT OCW 81