6.776
High Speed Communication Circuits
Lecture 21
Overview of Phase-Locked Loops and Integer-N
Frequency Synthesizers
Michael Perrott
Massachusetts Institute of Technology
April 28, 2005
Copyright © 2005 by Michael H. Perrott
What Is A Phase-Locked Loop?
ref(t)
e(t) Charge
PFD
Pump
Loop
Filter
v(t)
out(t)
VCO
ƒ
ƒ
ƒ
ƒ
ƒ
VCO
Reference
PFD
Charge pump
Loop filter
de Bellescize
Onde Electr, Vol. 11
1932
produces variable frequency output
provides input frequency/phase
compares phase of ref and VCO output
simplifies loop filter implementation
smooths PFD signal
Objective: “Lock” VCO phase to reference phase
M.H. Perrott
MIT OCW 2
Method of Phase Detection
ref(t)
e(t) Charge
PFD
Pump
Loop
Filter
v(t)
out(t)
VCO
ref(t)
out(t)
e(t)
ƒ
ƒ
v(t)
average{e(t)}
PFD output consists of pulses whose width is
proportional to the phase error
- Phase is only observable at edges
Smooth PFD output to produce input voltage to VCO
M.H. Perrott
MIT OCW 3
Impact of Changes in Phase Error
ref(t)
e(t) Charge
PFD
Pump
Loop
Filter
v(t)
out(t)
VCO
ref(t)
out(t)
e(t)
ƒ
ƒ
v(t)
average{e(t)}
Pulse width varies according to phase difference
VCO input voltage changes accordingly
- Adjusts VCO frequency and phase
M.H. Perrott
MIT OCW 4
Phase Lock Implies Frequency Lock
Fout = Fref
ref(t)
e(t) Charge
PFD
Pump
Loop
Filter
v(t)
out(t)
VCO
ref(t)
out(t)
e(t)
ƒ
v(t)
average{e(t)}
Any error in frequency leads to a steady accumulation
of phase error
M.H. Perrott
MIT OCW 5
Integer-N Frequency Synthesizer
Fref
ref(t)
Fout = N Fref
e(t) Charge
PFD
Pump
div(t)
Loop
Filter
v(t)
out(t)
VCO
Divider
N
ƒ
Sepe and Johnston
US Patent 3,551,826
1968 (filing date)
Leverages frequency divider to create “indirect”
frequency multiplication
- Allows digital adjustment of output frequency in
increments of the reference frequency
M.H. Perrott
MIT OCW 6
Integer-N Frequency Synthesizers in Wireless Systems
From Antenna
and Bandpass
Filter
PC board
trace
Zo
Zin
Package
Interface
Reference ref(t) Frequency v(t)
Frequency
Synthesizer
ref(t)
e(t) Charge
PFD
Pump
RF in
LNA
VCO
Mixer
IF out
To Filter
LO signal
out(t)
Loop
Filter
v(t)
out(t)
VCO
div(t)
Divider
N
ƒ
Design Issues: settling time, frequency resolution, noise, power
M.H. Perrott
MIT OCW 7
A Key Limitation of Integer-N Synthesizers
Fref
ref(t)
Fout = N Fref
e(t) Charge
PFD
Pump
div(t)
Loop
Filter
v(t)
out(t)
VCO
Divider
N
ƒ
Key constraint: Divider value, N, must be integer
- High frequency resolution requires low F
- High PLL bandwidth requires high F
ref
ref
Tradeoff: Frequency resolution vs PLL bandwidth
M.H. Perrott
MIT OCW 8
Fractional-N Frequency Synthesis
Fref
Fout = M.F Fref
ref(t)
e(t) Charge
PFD
Pump
Loop
Filter
v(t)
out(t)
VCO
div(t)
Nsd[k]
ƒ
ƒ
Divider
Dithering N[k]
Modulator
Kingsford-Smith
US Patent 3,928,813
1974 (filing date)
M+1
M
M.F
Divide value is dithered between integer values
Fractional divide values can be realized!
Very high frequency resolution
M.H. Perrott
MIT OCW 9
Classical Fractional-N Synthesizer Architecture
Fref
Fout = M.F Fref
ref(t)
e(t) Charge
PFD
Pump
Loop
Filter
v(t)
out(t)
VCO
Divider
div(t)
Frac
N[k]
ƒ
M+1
M
Carry
Out
Accumulator
Kingsford-Smith
US Patent 3,928,813
1974 (filing date)
M.F
M
Use an accumulator to perform dithering operation
- Fractional input value fed into accumulator
- Carry out bit of accumulator fed into divider
M.H. Perrott
MIT OCW 10
Integer-N Synthesizer Signals with Fout = 4.25Fref
N[k]
5
4
out(t)
div(t)
ref(t)
e(t)
ƒ
Constant divide value of N = 4 leads to frequency
error
- Error pulse widths increase as phase error accumulates
M.H. Perrott
MIT OCW 11
Fractional-N Synthesizer Signals with Fout = 4.25Fref
N[k]
5
4
out(t)
div(t)
ref(t)
e(t)
ƒ
Dithering allows average divide value of N = 4.25
- Reset phase error by periodically “swallowing” a VCO
cycle
ƒ Achieved by dividing by 5 every 4 reference cycles
M.H. Perrott
MIT OCW 12
Key Observations for Classical Fractional-N Dithering
N[k]
5
4
out(t)
div(t)
ref(t)
e(t)
phase
error
ƒ
ƒ
1 VCO
Period
The instantaneous phase error always remains less
than one VCO cycle
We can directly relate the phase error to the residue
of the accumulator that is providing the dithering
M.H. Perrott
MIT OCW 13
Accumulator Operation
clk(t)
frac[k]
M-bit
M-bit
Accumulator
1-bit
residue[k]
carry_out[k]
residue[k]
frac[k] =.25
carry_out[k]
ƒ
ƒ
Carry out bit is asserted when accumulator residue reaches
or surpasses its full scale value
Accumulator residue corresponds to instantaneous phase
error
- Increments by the fractional value input into the accumulator
M.H. Perrott
MIT OCW 14
The Issue of Spurious Tones
ref(t)
e(t) Charge
PFD
Pump
v(t)
Loop
Filter
out(t)
VCO
Se(f) Fractional
Spurs
0
f
Divider
div(t)
Nsd[m]
Fref
Accumulator
Carry Out
ƒ
PFD error waveform is periodic
- Creates spurious tones in synthesizer output at lower
frequencies than the reference
Ruins noise performance of the synthesizer
M.H. Perrott
MIT OCW 15
The Phase Interpolation Technique
ref(t)
e(t) Charge
PFD
Pump
v(t)
Loop
Filter
out(t)
VCO
D/A
Divider
div(t)
Nsd[m]
Accumulator
Residue
Carry Out
ƒ
Kingsbury
US Patent 4,179,670
1978 (filing date)
Leverage the fact that the phase error due to
fractional technique is predicted by the instantaneous
residue of the accumulator
- Cancel out phase error based on accumulator residue
M.H. Perrott
MIT OCW 16
The Problem With Phase Interpolation
ref(t)
e(t) Charge
PFD
Pump
v(t)
Loop
Filter
out(t)
VCO
D/A
Divider
div(t)
Nsd[m]
Accumulator
Residue
Carry Out
ƒ
Gain matching between PFD error and scaled D/A
output must be extremely precise
- Any mismatch will lead to spurious tones at PLL output
Matching issue prevented this technique from catching on
M.H. Perrott
MIT OCW 17
Σ−∆ Fractional-N Frequency Synthesis
Fref
Fout = M.F Fref
ref(t)
e(t) Charge
PFD
Pump
Loop
Filter
v(t)
out(t)
VCO
div(t)
Nsd[k]
Divider
N[k]
Σ−∆
Modulator
M+1
M
MASH Σ−∆
Wells
US Patent 4,609,881
1984 (filing date)
M.F
General Σ−∆
Riley
US Patent 4,965,531
f
1989 (filing date)
Dither using a Σ−∆ modulator
JSSC ‘93
Quantization noise is shaped to high frequencies
Spur content of the quantization noise can be reduced to
negligible levels
Σ−∆
Quantization
Noise
ƒ
-
M.H. Perrott
MIT OCW 18
Impact of Σ−∆ Quantization Noise on Synth. Output
Ref
PFD
Loop
Filter
Div
Frequency
Selection
M-bit
Out
N/N+1
Σ−∆
Modulator
1-bit
Quantization
Noise Spectrum
Output
Spectrum
Frequency
Selection
Fout
Σ−∆
ƒ
Noise
PLL dynamics
Lowpass action of PLL dynamics suppresses the
shaped Σ-∆ quantization noise
M.H. Perrott
MIT OCW 19
Impact of Increasing the PLL Bandwidth
Ref
PFD
Loop
Filter
Div
Frequency M-bit
Selection
Out
N/N+1
Σ−∆
Modulator
1-bit
Quantization
Noise Spectrum
Output
Spectrum
Frequency
Selection
ƒ
Noise
Fout
Σ−∆
PLL dynamics
Higher PLL bandwidth leads to less quantization noise
suppression
Tradeoff: Noise performance vs PLL bandwidth
M.H. Perrott
MIT OCW 20
Outline of PLL Lectures
ƒ
Integer-N Synthesizers
ƒ
Noise in Integer-N and Fractional-N Synthesizers
ƒ
Design of Fractional-N Frequency Synthesizers and
Bandwidth Extension Techniques
- Basic blocks, modeling, and design
- Frequency detection, PLL Type
- Noise analysis of integer-N structure
- Sigma-Delta modulators applied to fractional-N
structures
- Noise analysis of fractional-N structure
- PLL Design Assistant Software
- Quantization noise reduction for improved bandwidth
and noise
M.H. Perrott
MIT OCW 21
PLL Building Blocks
M.H. Perrott
MIT OCW
Voltage-Controlled Oscillators
M.H. Perrott
MIT OCW
Popular VCO Structures
LC oscillator
VCO Amp
-Ramp
Vout
C
Vin
L
Rp
Ring oscillator
Vout
Vin
ƒ
ƒ
-1
LC Oscillator: low phase noise, large area
Ring Oscillator: easy to integrate, higher phase noise
M.H. Perrott
MIT OCW 24
Model for Voltage to Frequency Mapping of VCO
LC oscillator
VCO Amp
-Ramp
Vout
C
Vin
L
Rp
Fvco
Ring oscillator
Vout
Vin
-1
VCO
Frequency
fc
Fout
slope=Kv
v
vin
Vbias
Input Voltage
M.H. Perrott
MIT OCW 25
Model for Voltage to Phase Mapping of VCO
ƒ
Time-domain frequency relationship (from previous
slide)
ƒ
Time-domain phase relationship
ƒ
Intuition of integral relationship between frequency and
phase:
1/Fvco= α
out(t)
out(t)
M.H. Perrott
1/Fvco= α+ε
MIT OCW 26
Frequency-Domain Model for VCO
ƒ
Time-domain relationship (from previous slide)
ƒ
Corresponding frequency-domain model
Laplace-Domain
v(t)
out(t)
VCO
M.H. Perrott
v(t)
2πKv
s
VCO
Φout(t)
Frequency-Domain
v(t)
Kv
jf
Φout(t)
VCO
MIT OCW 27
Frequency Dividers
M.H. Perrott
MIT OCW
Divide-by-2 Circuit (Johnson Counter)
Register
LATCH 1
LATCH 2
D
D
Q
clk
IN
IN
ƒ
ƒ
Q
clk
Q
OUT
Q
OUT
TIN
IN
OUT
Achieves frequency division by clocking two latches
(i.e., a register) in negative feedback
Latches may be implemented in various ways
according to speed/power requirements
M.H. Perrott
MIT OCW 29
Divide-by-2 Using a TSPC register
OUT
IN
OUT
IN
ƒ
ƒ
Advantages
- Reasonably fast, compact size
- No static power dissipation, differential clock not required
Disadvantages
- Slowed down by stacked PMOS, signals goes through
three gates per cycle
- Requires full swing input clock signal
M.H. Perrott
MIT OCW 30
Divide-by-2 Using SCL (also called CML) Latches
Φ1
Φ3
Φ2
Φ4
IN
ƒ
ƒ
Φ2
Φ3
IN
Φ4
Φ1
IN
IN
Advantage
- Very fast due to small swing and absence of PMOS devices
ƒ Additional speedup can be obtained by using inductors
Disadvantages
- High power, large area relative to TSPC
- Differential signals required
Biasing sources required
M.H. Perrott
MIT OCW 31
Creating Higher Divide Values (Synchronous Approach)
Register
1
T
Q
clk
Q
A
Register
T
Q
clk
Q
B
Register
T
Q
clk
IN
OUT
Q
Toggle Register
IN
A
T
B
OUT
Register
D
clk
Q
Q
Q
Q
clk
ƒ
Cascades toggle registers and logic to perform division
- Advantage: low jitter
- Problems: high power (all registers run at high frequency),
high loading on clock (IN signal drives all registers)
M.H. Perrott
MIT OCW 32
Creating Higher Divide Values (Asynchronous Approach)
IN
2
A
2
B
2
OUT
IN
A
B
OUT
ƒ
ƒ
Higher division achieved by simply cascading
divide-by-2 stages
Advantages over synchronous approach
ƒ
Disadvantage: jitter is larger
- Lower power: each stage runs at a lower frequency,
allowing power to be correspondingly reduced
- Less loading of input: IN signal only drives first stage
M.H. Perrott
MIT OCW 33
Variable Frequency Division
Prescaler
IN
Asynchronous
Divider
Synchronous
Divider
OUT
Control Logic
Divide Value (N)
ƒ
Classical design partitions variable divider into two sections
- Asynchronous section (called a prescaler) is fast
ƒ Often supports a limited range of divide values
- Synchronous section has no jitter accumulation and a wide
range of divide values
- Control logic coordinates sections to produce a wide range of
divide values
M.H. Perrott
MIT OCW 34
Dual Modulus Prescalers
IN
2/3
A
2
B
2
OUT
CON*
CON
Control
Qualifier
8 + CON Cycles
IN
A
B
OUT
CON
CON*
ƒ
ƒ
Dual modulus design supports two divide values
-
In this case, divide-by-8 or 9 according to CON signal
One cycle resolution achieved with front-end “2/3” divider
M.H. Perrott
MIT OCW 35
Divide-by-2/3 Design (Classical Approach)
Reg B
Reg A
D
IN
Q
Y
D
Q
OUT
Q
Q
2/3
ƒ
ƒ
CON *
Normal mode of operation: CON* = 0 ⇒ Y = 0
- Register B acts as divide-by-2 circuit
Divide-by-3 operation: CON = 1 ⇒ Y = 1
- Reg
B remains high for an extra cycle
ƒ Causes Y to be set back to 0 ⇒ Reg B toggles again
*
ƒ CON* must be set back to 0 before Reg B toggles to
prevent extra pulses from being swallowed
M.H. Perrott
MIT OCW 36
Control Qualifier Design (Classical Approach)
IN
2/3
A
2
B
2
OUT
CON*
CON
Control
Qualifier
IN
A
B
OUT
CON
CON*
ƒ
ƒ
Must align CON signal to first “2/3” divider stage
- CON signal is based on logic clocked by divider output
ƒ There will be skew between “2/3” divider timing and CON
Classical approach cleverly utilizes outputs from each
section to “gate” the CON signal to “2/3” divider
M.H. Perrott
MIT OCW 37
Multi-Modulus Prescalers
CON0
IN
2/3
CON1
A
2/3
CON2
B
2/3
OUT
8 + CON0 *20 + CON1 *21 + CON2 *22
IN
A
B
OUT
ƒ
Cascaded 2/3 sections achieves a range of 2n to 2n+1-1
ƒ
Asynchronous design allows high speed and low
power operation to be achieved
- Above example is 8/ " /15 divider
Only negative is jitter accumulation
M.H. Perrott
MIT OCW 38
A More Modular Design
IN
IN
2/3
OUT
modout modin
CON
CON0
IN
A
IN
2/3
OUT
B
modout modin
CON
CON1
IN
2/3
OUT
modout modin
CON
OUT
Vdd
CON2
8 + CON0 *20 + CON1 *21 + CON2 *22
A
B
OUT
ƒ
Perform control qualification by synchronizing within
each stage before passing to previous one
- Compare to previous slide in which all outputs required
ƒ
for qualification of first 2/3 stage
See Vaucher et. al., “A Family of Low-Power Truly
Modular Programmable Dividers …”, JSSC, July 2000
M.H. Perrott
MIT OCW 39
Implementation of 2/3 Sections in Modular Approach
2/3 Circuits
LATCH
CON *
D
LATCH
Q
clk
D
Q
Q
clk
Q
OUT
IN
modout
LATCH
Q
Q
LATCH
D
Q
Q
clk
D
clk
modin
Control
Qualifier
Circuits
CON
ƒ
Approach has similar complexity to classical design
ƒ
Cleverly utilizes “gating” register to pass synchronized
control qualifying signal to the previous stage
- Consists of two registers with accompanying logic gates
M.H. Perrott
MIT OCW 40
Divider Modeling
ƒ
Conceptual implementation
Counter
N
count value
out(t)
out
div(t)
out(t)
div(t)
ƒ
Time-domain model
- Frequency:
N=6
- Phase:
M.H. Perrott
MIT OCW 41
Frequency-Domain Model of Divider
ƒ
Time-domain relationship between VCO phase and
divider output phase (from previous slide)
ƒ
Corresponding frequency-domain model (same as
Laplace-domain)
out(t)
Divider
div(t)
Φout(t)
1
N
Φdiv(t)
Divider
M.H. Perrott
MIT OCW 42
Phase Detection
M.H. Perrott
MIT OCW
Phase Detector (PD)
ƒ
XOR structure
- Average value of error pulses corresponds to phase error
- Loop filter extracts the average value and feeds to VCO
ref(t)
e(t)
div(t)
ref(t)
div(t)
e(t)
1
-1
M.H. Perrott
MIT OCW 44
Modeling of XOR Phase Detector
ƒ
Average value of pulses is extracted by loop filter
- Look at detector output over one cycle:
W
e(t)
1
-1
T/2
ƒ
Equation:
M.H. Perrott
MIT OCW 45
Relate Pulse Width to Phase Error
ƒ
Two cases:
0 < Φref − Φdiv < π
−π < Φref − Φdiv < 0
T/2
T/2
ref(t)
ref(t)
div(t)
div(t)
e(t)
1
e(t)
-1
1
-1
W
W=-
M.H. Perrott
Φref − Φdiv
T/2
π
W
W=
Φref − Φdiv
T/2
π
MIT OCW 46
Overall XOR Phase Detector Characteristic
0 < Φref − Φdiv < π
−π < Φref − Φdiv < 0
T/2
T/2
ref(t)
ref(t)
div(t)
div(t)
e(t)
1
e(t)
-1
1
-1
W
W=-
W
Φref − Φdiv
T/2
π
W=
Φref − Φdiv
T/2
π
avg{e(t)}
gain = -2/π
−π
gain = 2/π
1
−π/2
0
π/2
π
Φref - Φdiv
-1
phase detector
range = π
M.H. Perrott
MIT OCW 47
Frequency-Domain Model of XOR Phase Detector
ƒ
Assume phase difference confined within 0 to π radians
- Phase detector characteristic looks like a constant gain
element
avg{e(t)}
gain = -2/π
−π
gain = 2/π
1
−π/2
0
π/2
Φref - Φdiv
π
-1
ƒ
Corresponding frequency-domain model
ref(t)
M.H. Perrott
PD
div(t)
e(t)
Φref(t)
Φdiv(t)
2
π
e(t)
PD gain
MIT OCW 48
Loop Filter
M.H. Perrott
MIT OCW
Loop Filter
ƒ
ƒ
Consists of a lowpass filter to extract average of
phase detector error pulses
Frequency-domain model
Laplace-Domain
e(t)
Loop
Filter
v(t)
e(t)
H(s)
VCO
ƒ
v(t)
Frequency-Domain
e(t)
H(s)
H(f)
v(t)
VCO
First order example
e(t)
R1
v(t)
C1
M.H. Perrott
MIT OCW 50
Integer-N Frequency Synthesizers
M.H. Perrott
MIT OCW
Overall Linearized PLL Frequency-Domain Model
ƒ
Combine models of individual components
Laplace-Domain Model
XOR PD
Φref(t)
Loop Filter
2
π
e(t)
H(s)
VCO
v(t)
2πKv
s
Φout(t)
Divider
Φdiv(t)
1
N
Frequency-Domain Model
XOR PD
Φref(t)
Φdiv(t)
M.H. Perrott
Loop Filter
2
π
e(t)
H(f)
VCO
v(t)
Kv
jf
Φout(t)
Divider
1
N
MIT OCW 52
Open Loop versus Closed Loop Response
ƒ
Frequency-domain model
XOR PD
Φref(t)
Φdiv(t)
Loop Filter
2
π
e(t)
H(f)
VCO
v(t)
Kv
jf
Φout(t)
Divider
1
N
ƒ
Define A(f) as open loop response
ƒ
Define G(f) as a parameterizing function (related to
closed loop response)
M.H. Perrott
MIT OCW 53
Classical PLL Transfer Function Design Approach
1. Choose an appropriate topology for H(f)
ƒ
Usually chosen from a small set of possibilities
2. Choose pole/zero values for H(f) as appropriate for
the required filtering of the phase detector output
ƒ
Constraint: set pole/zero locations higher than
desired PLL bandwidth to allow stable dynamics to
be possible
3. Adjust the open-loop gain to achieve the required
bandwidth while maintaining stability
ƒ
ƒ
Plot gain and phase bode plots of A(f)
Use phase (or gain) margin criterion to infer stability
M.H. Perrott
MIT OCW 54
Example: First Order Loop Filter
ƒ
Overall PLL block diagram
XOR PD
Φref(t)
Loop Filter
2
π
H(f)
v(t)
Kv
jf
Φout(t)
Divider
Φdiv(t)
ƒ
e(t)
VCO
1
N
Loop filter
e(t)
R1
v(t)
C1
M.H. Perrott
MIT OCW 55
Closed Loop Poles Versus Open Loop Gain
Evaluation of
Phase Margin
Open loop
gain
increased
Closed Loop Pole
Locations of G(f)
20log|A(f)|
C
Dominant
pole pair
0 dB
B
f
fp
angle(A(f))
Im{s}
A
C
B
A
Re{s}
0
o
-90
A
-120o
PM = 59o for A
PM = 45o for B
-150o
-180o
ƒ
PM = 33o for C
B
C
Higher open loop gain leads to an increase in Q of closed loop
poles
M.H. Perrott
MIT OCW 56
Corresponding Closed Loop Response
Step Response of G(f)
Frequency Response of G(f)
1.4
C
5 dB
0 dB
C
B
-5 dB
B
A
A
1
0.6
fp
ƒ
f
0
t
Increase in open loop gain leads to
- Peaking in closed loop frequency response
- Ringing in closed loop step response
M.H. Perrott
MIT OCW 57
The Impact of Parasitic Poles
ƒ
ƒ
ƒ
Loop filter and VCO may have additional parasitic
poles and zeros due to their circuit implementation
We can model such parasitics by including them in
the loop filter transfer function
Example: add two parasitic poles to first order filter
e(t)
R1
Parasitics
v(t)
C1
M.H. Perrott
MIT OCW 58
Closed Loop Poles Versus Open Loop Gain
Evaluation of
Phase Margin
Closed Loop Pole
Locations of G(f)
Im{s}
20log|A(f)|
Open loop
gain
increased
C
Dominant
pole pair
0 dB
f
fp fp2fp3
angle(A(f))
-90
o
o
-165
o
-180
-240
o
-315
o
M.H. Perrott
B
Non-dominant
poles
C
B
A
A
o
PM = 72 for A
PM = 51o for B
Re{s}
0
A
B
PM = -12o for C
C
MIT OCW 59
Corresponding Closed Loop Response
Closed Loop Step Response
Closed Loop Frequency Response
C
0 dB
A
B
C
1
B
A
Frequency
ƒ
Time
Increase in open loop gain now eventually leads to
instability
- Large peaking in closed loop frequency response
- Increasing amplitude in closed loop step response
M.H. Perrott
MIT OCW 60
Response of PLL to Divide Value Changes
XOR PD
Φref(t)
Loop Filter
2
π
e(t)
Kv
jf
Φout(t)
1
N
N+1
N
ƒ
v(t)
Divider
Φdiv(t)
ƒ
H(f)
VCO
t
Change in output frequency achieved by changing the
divide value
Classical approach provides no direct model of
impact of divide value variations
- Treat divide value variation as a perturbation to a linear
system
ƒ PLL responds according to its closed loop response
M.H. Perrott
MIT OCW 61
Response of an Actual PLL to Divide Value Change
ƒ
Example: Change divide value by one
N (Divide Value)
Synthesizer Response To Divider Step
93
92.8
92.6
92.4
92.2
92
Output Frequency (GHz)
91.8
40
60
80
100
120
140
160
180
200
220
240
40
60
80
100
120
140
160
180
200
220
240
1.87
1.86
1.85
1.84
1.83
Time (microseconds)
- PLL responds according to closed loop response!
M.H. Perrott
MIT OCW 62
What Happens with Large Divide Value Variations?
PLL temporarily loses frequency lock (cycle slipping
occurs)
Synthesizer Response To Divider Step
N (Divide Value)
96
95
94
93
92
Output Frequency (GHz)
ƒ
40
60
80
100
120
140
160
180
200
220
240
40
60
80
100
120
140
160
180
200
220
240
1.92
1.9
1.88
1.86
1.84
Time (microseconds)
- Why does this happen?
M.H. Perrott
MIT OCW 63
Recall Phase Detector Characteristic
avg{e(t)}
gain = -2/π
−π
gain = 2/π
1
−π/2
0
π/2
π
Φref - Φdiv
-1
ƒ
ƒ
To simplify modeling, we assumed that we always
operated in a confined phase range (0 to π)
- Led to a simple PD model
Large perturbations knock us out of that confined
phase range
- PD behavior varies depending on the phase range it
happens to be in
M.H. Perrott
MIT OCW 64
Cycle Slipping
ƒ
Consider the case where there is a frequency offset
between divider output and reference
- We know that phase difference will accumulate
ref(t)
div(t)
ƒ
Resulting ramp in phase causes PD characteristic to
be swept across its different regions (cycle slipping)
avg{e(t)}
gain = -2/π
−π
gain = 2/π
1
−π/2
0
π/2
π
Φref - Φdiv
-1
M.H. Perrott
MIT OCW 65
Impact of Cycle Slipping
ƒ
ƒ
Loop filter averages out phase detector output
Severe cycle slipping causes phase detector to
alternate between regions very quickly
- Average value of XOR characteristic can be close to
zero
- PLL frequency oscillates according to cycle slipping
- In severe cases, PLL will not re-lock
ƒ PLL has finite frequency lock-in range!
XOR DC characteristic
cycle slipping
1
−π
π
3π
nπ
(n+2)π
Φref - Φdiv
-1
M.H. Perrott
MIT OCW 66
Back to PLL Response Shown Previously
PLL output frequency indeed oscillates
- Eventually locks when frequency difference is small enough
Synthesizer Response To Divider Step
N (Divide Value)
96
95
94
93
92
Output Frequency (GHz)
ƒ
40
60
80
100
120
140
160
180
200
220
240
40
60
80
100
120
140
160
180
200
220
240
1.92
1.9
1.88
1.86
1.84
How do we extend the frequency lock-in range?
M.H. Perrott
Time (microseconds)
MIT OCW67
Phase Frequency Detectors (PFD)
ƒ
Example: Tristate PFD
1
D
ref(t)
R
1
div(t)
Q
D
R
up(t)
Q
e(t)
Q
Q
down(t)
Ref(t)
Div(t)
Up(t)
Down(t)
E(t)
M.H. Perrott
1
0
-1
MIT OCW 68
Tristate PFD Characteristic
ƒ
Calculate using similar approach as used for XOR
phase detector
avg{e(t)}
1
gain = 1/(2π)
−2π
2π
Φref - Φdiv
−1
phase detector
range = 4π
ƒ
Note that phase error characteristic is asymmetric
about zero phase
- Key attribute for enabling frequency detection
M.H. Perrott
MIT OCW 69
PFD Enables PLL to Always Regain Frequency Lock
ƒ
Asymmetric phase error characteristic allows positive
frequency differences to be distinguished from
negative frequency differences
- Average value is now positive or negative according to
sign of frequency offset
- PLL will always relock
Tristate DC characteristic
cycle slipping
1
−2π
0
2π
4π
2nπ
Φref - Φdiv
lock
-1
M.H. Perrott
MIT OCW 70
Another PFD Structure
ƒ
XOR-based PFD
D
ref(t)
D
div(t)
D
Q
Q
Q
ref/2(t)
div/2(t)
Q
Q
R
Q
e(t)
D SQ
Q
Divide-by-2
Phase
Detector
Frequency
Detector
ref(t)
div(t)
ref/2(t)
div/2(t)
e(t)
M.H. Perrott
1
-1
MIT OCW 71
XOR-based PFD Characteristic
ƒ
Calculate using similar approach as used for XOR phase
detector
avg{e(t)}
1
−3π
−2π
gain = 1/π
0
π
2π
4π
5π
Φref - Φdiv
−1
phase detector
range = 2π
ƒ
Phase errror characteristic asymmetric about zero phase
- Average value of phase error is positive or negative during
cycle slipping depending on sign of frequency error
M.H. Perrott
MIT OCW 72
Linearized PLL Model With PFD Structures
ƒ
Assume that when PLL in lock, phase variations are
within the linear range of PFD
- Simulate impact of cycle slipping if desired (do not
ƒ
include its effect in model)
Same frequency-domain PLL model as before, but
PFD gain depends on topology used
Tristate: α=1
PFD XOR-based: α=2
Φref(t)
Φdiv(t)
M.H. Perrott
α
2π
Loop Filter
e(t)
H(f)
VCO
v(t)
Kv
jf
Φout(t)
Divider
1
N
MIT OCW 73
Type I versus Type II PLL Implementations
ƒ
ƒ
Type I: one integrator in PLL open loop transfer
function
- VCO adds on integrator
- Loop filter, H(f), has no integrators
Type II: two integrators in PLL open loop transfer
function
- Loop filter, H(f), has one integrator
Tristate: α=1
PFD XOR-based: α=2
Φref(t)
Φdiv(t)
M.H. Perrott
α
2π
Loop Filter
e(t)
H(f)
VCO
v(t)
Kv
jf
Φout(t)
Divider
1
N
MIT OCW 74
VCO Input Range Issue for Type I PLL Implementations
ƒ
DC output range of gain block versus integrator
Gain Block
0
ƒ
Integrator
0
K
K
s
Issue: DC gain of loop filter often small and PFD
output range is limited
- Loop filter output fails to cover full input range of VCO
VDD
No
Integrator
ref(t)
PFD
e(t)
Loop
Filter
Gnd
Output Range
of Loop Filter
v(t)
out(t)
VCO
Divider
M.H. Perrott
N[k]
MIT OCW 75
Options for Achieving Full Range Span of VCO
ƒ
ƒ
Type I
- Add a D/A converter to provide coarse tuning
ƒ Adds complexity
ƒ Steady-state phase error inconsistently set
Type II
- Integrator automatically provides DC level shifting
ƒ Low power and simple implementation
ƒ Steady-state phase error always set to zero
Type I
Course
Tune
D/A
No
Integrator
e(t)
M.H. Perrott
C.P.
Loop
Filter
Type II
Output Range
of Loop Filter
Output Range
of Loop Filter
VDD
VDD
Contains
Integrator
Gnd
v(t)
e(t)
C.P.
Loop
Filter
Gnd
v(t)
MIT OCW 76
A Common Loop Filter for Type II PLL Implementation
ƒ
Use a charge pump to create the integrator
ƒ
Gain of loop filter can be adjusted according to the
value of the charge pump current
Example: lead/lag network
ƒ
- Current onto a capacitor forms integrator
- Add extra pole/zero using resistor and capacitor
e(t)
Charge
Pump
i(t)
v(t)
C1
M.H. Perrott
R1
C2
MIT OCW 77
Charge Pump Implementations
ƒ
Switch currents in and out:
Single-Ended
up(t)
Icp
Differential
Icp
Iout(t)
Iout(t)
e(t)
down(t)
Icp
M.H. Perrott
Icp
e(t)
2Icp
MIT OCW 78
Modeling of Loop Filter/Charge Pump
ƒ
ƒ
Charge pump is gain element
Loop filter forms transfer function
Charge
Pump
e(t)
ƒ
Icp
Loop
Filter
H(s)
v(t)
Example: lead/lag network from previous slide
M.H. Perrott
MIT OCW 79
PLL Design with Lead/Lag Filter
ƒ
Overall PLL block diagram
Tristate: α=1
PFD XOR-based: α=2
Φref(t)
α
2π
Charge
Pump Loop Filter
e(t)
Icp
H(f)
v(t)
VCO
Kv
jf
Φout(t)
Divider
Φdiv(t)
1
N
ƒ
Loop filter
ƒ
Set open loop gain to achieve adequate phase margin
- Set f lower than and f
z
M.H. Perrott
p
higher than desired PLL bandwidth
MIT OCW 80
Closed Loop Poles Versus Open Loop Gain
Evaluation of
Phase Margin
Open loop
gain
increased
Closed Loop Pole
Locations of G(f)
Im{s}
20log|A(f)|
C
B
0 dB
fz
fp
f
Non-dominant
pole
C
B
A
120
ƒ
-140
o
-160
o
-180
o
A
Re{s}
angle(A(f))
o
Dominant
pole pair
BC
A
PM = 54oo for B
PM = 53 for A
PM = 55o for C
A
B
C
Open loop gain cannot be too low or too high if
reasonable phase margin is desired
M.H. Perrott
0
MIT OCW 81
Impact of Parasitics When Lead/Lag Filter Used
ƒ
We can again model impact of parasitics by including
them in loop filter transfer function
e(t)
Charge
Pump
i(t)
Parasitics
C1
ƒ
v(t)
R1
C2
Example: include two parasitic poles with the lead/lag
transfer function
M.H. Perrott
MIT OCW 82
Closed Loop Poles Versus Open Loop Gain
Evaluation of
Phase Margin
Open loop
gain
increased
Closed Loop Pole
Locations of G(f)
20log|A(f)|
0 dB
120
C
Dominant
pole pair
fz
angle(A(f))
Im{s}
B
f
fp fp2 fp3
Non-dominant
poles
C
B
A
A
Re{s}
BC
A
o
0
A
o
-140
ƒ
o
-160
o
-180
o
PM = 46 for A
PM = 38o for B
PM = -7o for C
B
C
Closed loop response becomes unstable if open loop
gain is too high
M.H. Perrott
MIT OCW 83
Negative Issues For Type II PLL Implementations
Normalized Amplitude
|G(f)|
Peaking caused by
undesired pole/zero pair
fcp fz
1
0
ƒ
fz
fo
Frequency (Hz)
Step Responses for a Second Order
G(f) implemented as a Bessel Filter
1.4
Type II: fz/fo = 1/3
Type II: fz/fo = 1/8
1
Type I
0.6
f
0
1
2
3
Normalized time: t*fo
4
Parasitic pole/zero pair causes
- Peaking in the closed loop frequency response
ƒ A big issue for CDR systems, but not too bad for wireless
- Extended settling time due to parasitic “tail” response
ƒ Bad for wireless systems demanding fast settling time
M.H. Perrott
MIT OCW 84