6.776 High Speed Communication Circuits and Systems Lecture 13
advertisement
6.776 High Speed Communication Circuits and Systems Lecture 13 LNA Design Examples and Recent Techniques Massachusetts Institute of Technology March 17, 2005 Copyright © 2005 by Hae-Seung Lee and Michael H. Perrott LNA Design Example In our previous design example, we picked the Q for the minimum possible noise factor: Q=1.4 We (arbitrarily) chose Vgs=1V 7 6 5.5 5 4.5 c = -j0 4 3.5 3 The design yields Achievable values as a function of Q under the constraints that 1 = wo (Lg+Ldeg)Cgs gm L = Rs Cgs deg 6.5 Noise Factor Scaling Coefficient Noise Factor Scaling Coefficient Versus Q for 0.18 µ NMOS Device 2.5 1 Note: 1 Q= 2RswoCgs c = -j0.55 c = -j1 1.5 2 2.5 3 Q 3.5 4 4.5 5 And requires H.-S. Lee & M.H. Perrott MIT OCW Id Vgs M1 1.8µ W = L 0.18µ gm and gdo (milliAmps/Volts) and Vgs (Volts) Bias Point (Vgs = 1V) 4.5 Vgs , gm , and gdo versus Current Density for 0.18µ NMOS Chosen bias point is Vgs = 1 V 4 3.5 3 2.5 Lower power Higher power Higher ft Lower ft Lower IIP3 Higher IIP3 gdo gdo Lower g Higher g m m gdo 2 Vgs 1.5 gm 1 0.5 0 0 100 200 300 400 500 600 700 Current Density (microAmps/micron) Problem: the device is in velocity saturation H.-S. Lee & M.H. Perrott MIT OCW We Have Two “Handles” to Lower Power Dissipation Key formulas Lower current density, Iden Lower W - Benefits - Negatives - Benefit: lower power - Negatives H.-S. Lee & M.H. Perrott MIT OCW Id Vgs M1 1.8µ W = L 0.18µ gm and gdo (milliAmps/Volts) and Vgs (Volts) First Step in Redesign – Lower Current Density, Iden 4.5 Vgs , gm , and gdo versus Current Density for 0.18µ NMOS New bias point is Vgs = 0.8 V 4 3.5 gdo 3 2.5 2 Vgs 1.5 gm 1 0.5 0 0 100 200 300 400 500 600 700 Current Density (microAmps/micron) Need to verify that IIP3 still OK (once we know Q) H.-S. Lee & M.H. Perrott MIT OCW Recalculate Process Parameters Assume that the only thing that changes is gm/gdo and ft - From previous graph (I den = 100 µ A/µ m) We now need to replot the Noise Factor scaling coefficient - Also plot over a wider range of Q Noise Factor scaling coefficient H.-S. Lee & M.H. Perrott MIT OCW Update Plot of Noise Factor Scaling Coefficient Noise Factor Scaling Coefficient Versus Q for 0.18 µ NMOS Device 18 Noise Factor Scaling Coefficient 16 14 12 10 Achievable values as a function of Q under the constraints that 1 = wo (Lg+Ldeg)Cgs gm L = Rs Cgs deg 8 c = -j0.55 6 c = -j0 Note: 1 Q= 2RswoCgs 4 c = -j1 2 1 2 H.-S. Lee & M.H. Perrott 3 4 5 6 Q 7 8 9 10 MIT OCW Second Step in Redesign – Lower W (or Raise Q) Recall Ibias can be related to Q as We previously chose Q = 1.4, let’s now choose Q = 6 - This alone cuts power dissipation by more than a factor - of 4. Combined with lower Iden, almost a factor of 8 reduction in power New value of W : H.-S. Lee & M.H. Perrott MIT OCW Power Dissipation and Noise Figure of New Design Power dissipation - At 1.8 V supply Noise Figure - f previously calculated, get scaling coeff. from plot t H.-S. Lee & M.H. Perrott MIT OCW Updated Component Values Assume Rs = 50 Ohms, Q = 6, fo = 1.8 GHz, ft = 42.8 GHz -C -L -L gs calculated as deg g calculated as calculated as H.-S. Lee & M.H. Perrott MIT OCW Inclusion of Load (Resonant Tank) Add output load to achieve voltage gain - Note: in practice, use cascode device LL vin Rs RL Iout inout iout Lg Zin LL Lg ens CL vout We’re ignoring Cgd in this analysis Rs RL CL Zgs vgs Cgs gmvgs indg Ldeg Vout M1 vin Ldeg Vbias H.-S. Lee & M.H. Perrott MIT OCW Calculation of Gain Assume load tank resonates at frequency ωo LL RL CL vout inout Rs vin Assume Zin = Rs H.-S. Lee & M.H. Perrott ens iout Lg Zin Zgs vgs Cgs gmvgs indg Ldeg MIT OCW Setting of Gain Parameters gm and Q were set by Noise Figure and IIP3 considerations - Note that Q is of the input matching network, not the amplifier load RL is the free parameter – use it to set the desired gain - Note that higher R for a given resonant frequency and capacitive load will increase QL (i.e., Q of the amplifier load) There is a tradeoff between amplifier bandwidth and gain Generally set RL according to overall receiver noise and IIP3 requirements (higher gain is better for noise) Very large gain (i.e., high QL) is generally avoided to minimize sensitivity to process/temp variations that will shift the center frequency and to avoid parasitic oscillation L - H.-S. Lee & M.H. Perrott MIT OCW The Issue of Package Parasitics Noise Voltage LL Equivalent Source Rs RL Lbondwire2 CL Vout Lext Lbondwire3 Noise Current Mixer and Other Circuits M1 vin Ldeg Vbias Noise Voltage Noise Current Lbondwire1 Bondwire (and package) inductance causes two issues - Value of degeneration inductor is altered - Noise from other circuits couples into LNA H.-S. Lee & M.H. Perrott MIT OCW Differential LNA LL Rs RL CL Vout Lg M1 vin Ldeg CL RL LL Vout Ldeg Lg M2 2 -vin 2 Vbias Rs Ibias Advantages - Value of L is now much better controlled - Much less sensitivity to noise from other circuits deg Disadvantages - Twice the power as the single-ended version - Requires differential input at the chip H.-S. Lee & M.H. Perrott MIT OCW Note: Be Generous with Substrate Contact Placement To Ldeg To Lg GND To amplifer load GND G D S Substrate Contact N+ enRsub enRsub Rsub Hot electrons and other noise Substrate Contact N+ P- Rsub Hot electrons and other noise Having an abundance of nearby substrate contacts helps in three ways - Reduces possibility of latch up issues - Lowers R and its associated noise Impacts LNA through backgate effect (g ) - Absorbs stray electrons from other circuits that will sub mb otherwise inject noise into the LNA Negative: takes up a bit extra area H.-S. Lee & M.H. Perrott MIT OCW Broadband LNA Design Zin High Speed Broadband Signal PC board trace Zo Package Interface LNA Most broadband systems are not as stringent on their noise requirements as wireless counterparts Equivalent input voltage is often specified rather than a Noise Figure Typically use a resistor to achieve a broadband match to input source - We know from Lecture 12 that this will limit the noise figure to be higher than 3 dB For those cases where low Noise Figure is important, are there alternative ways to achieve a broadband match? H.-S. Lee & M.H. Perrott MIT OCW Recall Noise Factor Calculation for Resistor Load Source Source Rs Rs enRs enRL vin RL vout RL Total output noise Total output noise due to source Noise Factor H.-S. Lee & M.H. Perrott vnout MIT OCW Noise Figure For Amp with Resistor in Feedback Rf Source Source Rs Rs A Vin Vref Vout Rf enRf enRs incremental ground A Vnout Total output noise (assume A is large and noiseless) Total output noise due to source (assume A is large) Noise Factor H.-S. Lee & M.H. Perrott MIT OCW Input Impedance For Amp with Resistor in Feedback Source Rf enRf enRs Rs A Vnout Zin Recall from Miller effect discussion that If we choose Zin to match Rs, then Therefore, Noise Figure lowered by being able to choose a large value for Rf since H.-S. Lee & M.H. Perrott MIT OCW Resistor Termination vs. Resistor in Feedback For Termination Source Rf enRf For Termination enRs Rs A Vnout Zin H.-S. Lee & M.H. Perrott MIT OCW Example – Series-Shunt Amplifier Rin Rs vin Rout RL Rf vx vout M1 Vbias R1 Recall that the above amplifier was analyzed in Lecture 7 Tom Lee’s book points out that this amplifier topology is actually used in noise figure measurement systems such as the Hewlett-Packard 8970A - It is likely to be a much higher performance transistor than a CMOS device, though H.-S. Lee & M.H. Perrott MIT OCW Recent CMOS LNA Techniques Consider increasing gm for a given current by using both PMOS and NMOS devices - Key idea: re-use of current (1/2)W/L Id gm1+gm2 gm Id M1 Id/2 M1 Id/2 gm1+gm2 M2 (1/2)W/L Id/2 Id/2 W/L (1/2)W/L M2 (1/2)W/L M1 See A. Karanicolas, “A 2.7 V 900-MHz CMOS LNA and Mixer”, JSSC, Dec 1996 H.-S. Lee & M.H. Perrott MIT OCW Biasing for LNA Employing Current Re-Use Stage 1 Stage 2 Rbig1 M4 M2 Vout1 Vout2 Ibias Vrf Rbig2 Cbig1 M1 Matching Network Cbig2 M3 Cbig3 opamp Vref PMOS is biased using a current mirror NMOS current adjusted to match the PMOS current H.-S. Lee & M.H. Perrott MIT OCW Another Recent Approach Feedback from output to base of transistor provides another degree of freedom. Negative feedback improves IIP3 LL RL CL Vout Q1 α Rs Vin Cbypass α<1 Ldeg Figure by MIT OCW. For details, check out: - Rossi, P. et. Al., “A 2.5 dB NF Direct-Conversion Receiver Front-End for HiperLan2/IEEE802.11a”, ISSCC 2004, pp. 102-103 H.-S. Lee & M.H. Perrott MIT OCW Recent Broadband LNA Approaches Can create broadband matching networks using LC-ladder filter design techniques CMOS example: RL LL Vbias2 Rs L1 C1 M3 M2 Vout Lg M1 Cp vin L2 Vbias Ibias C2 Ldeg See Bevilacqua et. al, “An Ultra-Wideband CMOS LNA for 3.1 to 10.6 GHz Wireless Receivers”, ISSC 2004, pp. 382-383 H.-S. Lee & M.H. Perrott MIT OCW Recent Broadband LNA Approaches (Continued) Bipolar example: RL LL Vbias2 Rs C3 M3 C2 Vbias3 Q1 C1 vin Vout R1 Q2 C4 Ldeg2 L1 Ldeg Vbias See Ismail et. al., “A 3 to 10 GHz LNA Using a Wideband LC-ladder Matching Network”, ISSCC 2004, pp. 384-385 H.-S. Lee & M.H. Perrott MIT OCW Gm Boosting for Noise Figure Improvement Gm Boosted CG Amp ino ino ind ind -A ins Rs Rs ins Figure by MIT OCW. But, the amplifier adds noise and power. How do we boost the Gm without an amplifier? See Xiaoyong Li et. al., “Low-Power gm-boosted LNA and VCO Circuits in 0.18µm CMOS” 2005 ISSCC Digest of Technical Papers pp. 534-353 H.-S. Lee & M.H. Perrott MIT OCW Gm Boosting by a Transformer Vdd Ld C1 Out M2 C2 M1 In k LP T1 Ls VB Figure by MIT OCW. Gm is boosted without adding noise by the step-up transformer Transformer provides gate and source with voltages 180o out of phase: effective increase in Vgs H.-S. Lee & M.H. Perrott MIT OCW Revisit Neutralizaton CN RL RL Cgd vin Rs Vbias CN Cgd M1 Rs M2 -vin 2Ibias Issues: Power Consumption Output swing (additional drop for the tail current) Differential output Matching between Cgd and CN - H.-S. Lee & M.H. Perrott MIT OCW Can We Tune Out Cgd Instead? VDD ZLOAD L VOUT CBIG VIN M1 Figure by MIT OCW. Conceptually, one can tune out Cgd by a series inductor L. CBIG is necessary to block DC between input and output. Inductor value too large Bottom plate parasitic capacitance of CBIG - Source: David J. Cassan , et. al., “A 1-V Transformer-Feedback Low-Noise Amplifier for 5-GHz Wireless LAN in 0.18 m CMOS” IEEE J. Solid-State Circuits, vol. SC-23 pp 427-435, Mar. 2003 H.-S. Lee & M.H. Perrott MIT OCW Neutralization by Transformer Feedback VDD Neutraliztion of Cgd by Cgs if L22 VOUT VIN M1 L11 Figure by MIT OCW. Advantages No DC drop: can operate at low supply voltages Power match by inductor degeneration No additional power consumption Cgd to Cgs matching is better than Cgd to CN - H.-S. Lee & M.H. Perrott MIT OCW Differential Implementation LM1 VIN+ Q1 CM1 L11 VOUT+ M L22 CTUNE VDD CM1 VIN- LM1 M L11 Q1 L22 CTUNE VOUT- Figure by MIT OCW. See David J. Cassan , et. al., “A 1-V Transformer-Feedback Low-Noise Amplifier for 5-GHz Wireless LAN in 0.18 m CMOS” IEEE J. Solid-State Circuits, vol. SC-23 pp 427-435, Mar. 2003 H.-S. Lee & M.H. Perrott MIT OCW Differential Output LNA I-IF-out BIAS LO-IM RF_in LO-IP LO-IM MIXER_I LNA Blasing not shown MIXER_Q Q-IF-out Provides differential output to drive balanced mixers See D. Sahu et. al. “A 90nm CMOS Single-Chip GPS Receiver with 5dBm Out-of-Band IIP3 2.0dB NF”, 2005 ISSCC Digest of Technical Papers, pp308-309 H.-S. Lee & M.H. Perrott Figure by MIT OCW. MIT OCW Adjustable Gain LNA VDD G2 G2 ... G2 ... G2 VDD ... ... Current Steering Gain Control VB LNAIN VB On-Chip Transformer Figure by MIT OCW. Gain is adjusted by diverting output current in the cascode stage See H. Darabi, et. al, "A Fully Integrated SoC for 802.11b in 0.18µm CMOS”, 2005 ISSCC Digest of Technical Papers, pp 96-97. H.-S. Lee & M.H. Perrott MIT OCW
