6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers
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6.776 High Speed Communication Circuits Lecture 7 High Freqeuncy, Broadband Amplifiers Massachusetts Institute of Technology February 24, 2005 Copyright © 2005 by Hae-Seung Lee and Michael H. Perrott High Frequency, Broadband Amplifiers The first thing that you typically do to the input signal package is amplify it Connector Adjoining pins die Controlled Impedance PCB trace Driving Source Z1 Vin On-Chip L1 Delay = x Characteristic Impedance = Zo Transmission Line Function Key performance parameters Amp C1 C2 RL Vout VL - Boosts signal levels to acceptable values - Provides reverse isolation - Gain, bandwidth, noise, linearity H.-S. Lee & M.H. Perrott MIT OCW Gain-bandwidth Trade-off Common-source amplifier example Vdd RL vo vin Vbias + + - Ctot Ctot: total capacitance at output node DC gain 3 dBbandwidth Gain-bandwidth H.-S. Lee & M.H. Perrott MIT OCW Gain-bandwidth Trade-off Common-source amplifier example RL=RL1 RL=RL3 RL=RL3 Given the ‘origin pole’ gm/Ctot, higher bandwidth is achieved only at the expense of gain The origin pole gm/Ctot must be improved for better GB H.-S. Lee & M.H. Perrott MIT OCW Gain-bandwidth Improvement How do we improve gm/Ctot? Assume that amplifier is loaded by an identical amplifier and fixed wiring capacitance is negligible Since and To achieve maximum GB in a given technology, use minimum gate length, bias the transistor at maximum When velocity saturation is reached, higher not give higher gm In case fixed wiring capacitance is large, power consumption must be also considered H.-S. Lee & M.H. Perrott does MIT OCW Gain-bandwidth Observations Constant gain-bandwidth is simply the result of singlepole role off – it’s not fundamental! It implies a single-pole frequency response may not be the best for obtaining gain and bandwidth simultaneously Single-pole role off is necessary for some circuits, e.g. for stability, but not for broad-band amplifiers H.-S. Lee & M.H. Perrott MIT OCW Assumptions (for now) for Bandwidth Analysis Assume for now that amplifier is loaded by an identical amplifier and by fixed wiring capacitance Assume amplifier is driven by an ideal voltage source for now Ctot = Cout+Cin+Cfixed Cin Cout Cin Amp Amp Cfixed Intrinsic performance Defined as the bandwidth achieved for a given gain when Cfixed is negligible Amplifier approaches intrinsic performance as its device sizes (and current) are increased In practice, point of diminishing return for bandwidth vs. size (and power) of amplifier is roughly where Cin+Cout = Cfixed - H.-S. Lee & M.H. Perrott MIT OCW The Miller Effect Concerns impedances that connect from input to output of an amplifier Zin Vin Zf Av Amp Input impedance: Output impedance: H.-S. Lee & M.H. Perrott Zout Vout ZL MIT OCW Example: Miller Capacitance Consider Cgd in the MOS device as Cf - Assume gain is negative Cf Zin Vin Zout Av Amp Vout ZL Input capacitance: Looks like much larger capacitance by |Av| H.-S. Lee & M.H. Perrott MIT OCW Example: Miller Capacitance Cf Zin Vin Zout Av Amp Vout ZL Output impedance: This makes sense because the input of the amplifier is ‘virtual ground’ if gain is large H.-S. Lee & M.H. Perrott MIT OCW Amplifier Example – CMOS Inverter The Miller effect gives a quick way to estimate the bandwidth of an amplifer without solving node equations: intuition! Assume that we set Vbias the amplifier nominal output is such that NMOS and PMOS transistors are all in saturation - Note: this topology VERY sensitive to V biasing would be required (6.301) bias : some feedback M4 M2 vout vin M1 Cfixed M3 Vbias Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + Cfixed (+Cov1+Cov2) H.-S. Lee & M.H. Perrott Miller multiplication factor MIT OCW Transfer Function of CMOS Inverter vout vin (gm1+gm2)(ro1||ro2) Low Bandwidth! slope = -20 dB/dec f 1 1 2πCtot(ro1||ro2) gm1+gm2 2πCtot M4 M2 vout vin M1 Cfixed M3 Vbias Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + Cfixed (+Cov1+Cov2) H.-S. Lee & M.H. Perrott Miller multiplication factor MIT OCW Add Resistive Feedback? vout vin Bandwidth extended and less sensitivity to bias offset (does not improve GB, though) (gm1+gm2)(ro1||ro2) slope = -20 dB/dec (gm1+gm2)Rf f 1 1 2πCtot(ro1||ro2) gm1+gm2 2πCtot 1 2πCtotRf vin M4 M2 vout Rf M1 Cfixed M3 Vbias Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + CRf /2 + Cfixed (+Cov1+Cov2) H.-S. Lee & M.H. Perrott Miller multiplication factor MIT OCW We Can Still Do Better We are fundamentally looking for high gm to capacitance ratio to get the highest bandwidth PMOS degrades this ratio Gate bias voltage is constrained However, when Cfixed is dominant and power consumption is important, the PMOS increases gm without additional power On the other hand, below velocity saturation, higher gm can be achieved by biasing the gate of M1 close to Vdd instead of using PMOS - M4 M2 vout Rf vin M1 Cfixed M3 Vbias Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + CRf /2 + Cfixed (+Cov1+Cov2) H.-S. Lee & M.H. Perrott Miller multiplication factor MIT OCW Take PMOS Out of the Signal Path Vbias2 Ibias vout Rf vin M1 Vbias M2 vout Rf vin CL M1 CL Vbias Advantages - PMOS gate no longer loads the signal - NMOS device can be biased at a higher voltage (higher g m up to velocity sat. limit) Issue - PMOS is not an efficient current provider (I /drain cap C +C Drain cap close in value to C - Signal path is loaded by cap of R and drain cap of PMOS d gd db) gs f H.-S. Lee & M.H. Perrott MIT OCW Shunt-Series Amplifier Rin Rs vout Rf vin Rin Rout Ibias RL M1 Rs Rout vin M1 R1 R1 vout Vbias Vbias RL Rf Use resistors to control the bias, gain, and input/output impedances - Improves accuracy over process and temp variations Issues - Degeneration of M lowers slew rate for large signal applications (such as limit amps) - There are better high speed approaches – the advantage 1 of this one is simply accuracy H.-S. Lee & M.H. Perrott MIT OCW Shunt-Series Amplifier – Analysis Snapshot From Chapter 9 (8) of Tom Lee’s book: Rin - Gain Rs vin Rout RL Rf vx vout M1 Vbias R1 - Input resistance - Output resistance H.-S. Lee & M.H. Perrott Same for Rs = RL! MIT OCW NMOS Load Amplifier Vdd vout vin M2 vin 1 gm2 Id Vbias M1 gm1 gm2 vout Cfixed M3 slope = -20 dB/dec f 1 gm2 Ctot = Cdb1+Csb2+Cgs2 + Cgs3+KCov3 + Cfixed (+Cov1) Miller multiplication factor gm1 2πCtot 2πCtot Gain set by the relative sizing of M1 and M2 H.-S. Lee & M.H. Perrott MIT OCW Design of NMOS Load Amplifier Vdd Ctot = Cdb1+Csb2+Cgs2 + Cgs3+KCov3 + Cfixed M2 vin Vbias 1 gm2 Id M1 (+Cov1) Miller multiplication factor vout Cfixed M3 Size transistors for gain and speed - Choose minimum L for maximum speed - Choose ratio of W to W to achieve appropriate gain 1 H.-S. Lee & M.H. Perrott 2 MIT OCW Advantage/Disadvantages of NMOS Load Amplifier Gain is well controlled despite process variations NMOS is not a low parasitic load -C gs of M2 loads the output Biasing Problem: VT of M2 lowers the gate bias voltage of the next stage (thus lowering its achievable ft) - Severely hampers performance when amplifier is cascaded - One paper addressed this issue by increasing V of NMOS dd load (see Sackinger et. al., “A 3-GHz 32-dB CMOS Limiting Amplifier for SONET OC-48 receivers”, JSSC, Dec 2000) H.-S. Lee & M.H. Perrott MIT OCW Resistor Loaded Amplifier (Unsilicided Poly) vout vin Vdd RL Id vin Vbias M1 vout Cfixed gm1RL M2 1 Ctot = Cdb1+CRL/2 + Cgs2+KCov2 + Cfixed (+Cov1) slope = -20 dB/dec f gm1 2πCtot 1 2πRLCtot Miller multiplication factor This is the fastest non-enhanced amplifier topology - Unsilicided poly is a low parasitic load (i..e, has a good current to capacitance ratio) - Output can go near V dd Allows following stage to achieve high ft , but at the cost of gain (max gain ∝ VR ) L - Linear settling behavior (in contrast to NMOS load) H.-S. Lee & M.H. Perrott MIT OCW Gain Limitations in Resistor Loaded Amplifier Want high for high bandwidth, but this reduces gain. With low Vdd gain is very limited. H.-S. Lee & M.H. Perrott MIT OCW Implementation of Resistor Loaded Amplifier Typically implement using differential pairs Vdd R1 R2 Vo- αIbias Vin+ Ibias/2 M1 M2 Vo+ Vin- Cfixed Cfixed M3 M4 Ibias M5 Benefits Negative M6 M7 - Bias stability without feedback - Common-mode rejection - More power than single-ended version H.-S. Lee & M.H. Perrott MIT OCW Open-Circuit Time Constants The Miller capacitance analysis is a reasonably good method, but is somewhat limited in applicable topologies the OCT method is more general and often gives more insights Systematic, intuitive method to determine bandwidth of amplifiers Often gives fairly accurate estimates of bandwidth if there is a dominant pole Points to the bandwidth bottleneck: this is the real value of the OCT method! Limitation: fails in RF circuits with zero enhancements or inductors In typical broadband amplifiers, the OCT estimate is too pessimistic due to multiple poles at around similar frequencies H.-S. Lee & M.H. Perrott MIT OCW Open Circuit Time Constant Method Assumptions: No zero near or ωh Zero well below wh is handled by treating corresponding capacitor as sort circuit Negative real poles only (complex conjugate poles with low Q reduces accuracy of estimation only moderately) No inductors A( s ) = = Vo a0 = Vi (1 + τ1s )(1 + τ 2 s ) ⋅ ⋅ ⋅ (1 + τ n s ) a0 1 + (τ1 + τ 2 + ⋅ ⋅ ⋅ + τ n )s ⋅ ⋅ ⋅ τ1τ 2 ⋅ ⋅ ⋅ τ n s n If we ignore the higher order terms 1 ω h = 2πf h ≈ = n1 τ1 + τ 2 + ⋅ ⋅ ⋅ + τ n ∑τ i i =1 H.-S. Lee & M.H. Perrott MIT OCW OCT Method, Continued It can be shown n n i =1 j =1 ∑ τ i = ∑ τ jo Thus ω h ≈ 1 n ∑τ jo j =1 where τ jo = R joC j :open-circuit time constants The open-circuit time constants can be found without node equations, often by inspection H.-S. Lee & M.H. Perrott MIT OCW OCR Calculation Let’s consider an arbitrary circuit with resistors, dependent sources, and n capacitors (no inductors!). Redraw the circuit to pull capacitors out around the perimeter. R2o C2 C1 R1o + - Cn H.-S. Lee & M.H. Perrott + - Rno MIT OCW OCT’s for CS Amplifier R2o RL vo Cgd CL R3o RS R1o Cgs By inspection: It takes some work to figure H.-S. Lee & M.H. Perrott MIT OCW OCT’s for CS Amplifier RL it + RS + vgs vo vt gmvgs - H.-S. Lee & M.H. Perrott MIT OCW OCT’s for CS Amplifier If RS=0, then τ1o=0,τ2o=CgdRL, and τ3o=CLRL so RL determines the bandwidth Having individual OCT values identifies the bandwidth bottleneck and suggests a game plan Note:for cascased amplifiers, CL does not include Miller cap of the next stage. Instead, τ2o corresponding to the next stage Miller cap is separately calculated H.-S. Lee & M.H. Perrott MIT OCW Cascode to Improve Bandwidth Midband gain: by inspection av = − g m1RL VCC RL R1o = RS R ⎛ R2o = R1o ⎜⎜1 + g m1RL ,eff + L ,eff RS ⎝ = RS + (1 + g m1RS )RL , eff vo RS ,eff = ro1 M2 RS vi RL ,eff = M1 1 g m 2, eff = = RS + 1 g m 2 + g mb 2 R3o ≈ RS , eff R4o H.-S. Lee & M.H. Perrott ⎞ ⎟⎟ ⎠ 1 + g m1RS g m 2 + g mb 2 1 g m 2, eff ≈ 1 g m 2 + g mb 2 ⎛ ⎜ RL = rb ⎜1 + ⎜ 1 + RS ,eff ⎜ g m , eff ⎝ ⎞ ⎟ ⎟+R ≈ R L L ⎟ ⎟ ⎠ MIT OCW Cascode Improves bandwidth in a single-stage amplifier Problem in cascading: - Bias point: Reduces ω of the next stage. PMOS SF is a t possibility but low gm/C ratio is a drawback. H.-S. Lee & M.H. Perrott MIT OCW
