6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, Gain-
advertisement
6.776 High Speed Communication Circuits Lecture 6 MOS Transistors, Passive Components, GainBandwidth Issue for Broadband Amplifiers Massachusetts Institute of Technology February 17, 2005 Copyright © 2005 by Hae-Seung Lee and Michael H. Perrott Basics of MOS Large Signal Behavior (Qualitative) Triode ID VGS G S Overall I-V Characteristic VDS=0 D Cchannel = Cox(VGS-VT) Pinch-off ID ID Pinch-off Saturation VGS G S VD=∆V D Saturation Triode ∆V ID VDS VGS G S H.-S. Lee & M.H. Perrott VD>∆V D MIT OCW Basics of MOS Large Signal Behavior (Quantitative) Triode ID VGS G S VDS=0 ID = µnCox W (VGS - VT - VDS/2)VDS L for VDS << VGS - VT D ID Cchannel = Cox(VGS-VT) Pinch-off µnCox W (VGS - VT)VDS L ID ∆V = VGS-VT VGS G S VD=∆V ∆V = D Saturation G H.-S. Lee & M.H. Perrott µnCoxW ID VGS S 2IDL VD>∆V D ID = 1 µ C W (VGS-VT)2(1+λVDS) n ox 2 L (where λ corresponds to channel length modulation) MIT OCW Analysis of Amplifier Behavior Typically focus on small signal behavior To do small signal analysis: - Work with a linearized model such as hybrid-π Small Signal Analysis Steps ID RD 1) Solve for bias current Id RG vout vin Vbias H.-S. Lee & M.H. Perrott RS 2) Calculate small signal parameters (such as gm, ro) 3) Solve for small signal response using transistor hybrid-π small signal model MIT OCW MOS DC Small Signal Model Assume transistor in saturation: ID RD RD RG RG vgs gmvgs ro -gmbvs RS vs RS gm = µnCox(W/L)(VGS - VT)(1 + λVDS) = 2µnCox(W/L)ID (assuming λVDS << 1) gmb = γg m 2 2|Φp| + VSB where γ = 2qεsNA Cox In practice: gmb = gm/5 to gm/3 ro = H.-S. Lee & M.H. Perrott 1 λID MIT OCW Capacitors For MOS Device In Saturation Top View Side View ID E VGS G Cov S D Cov Cgc Ccb S W Cjsb LD B E VD>∆V D Cjdb LD L E junction bottom wall cap (per area) L source to bulk cap: Cjsb = drain to bulk cap: Cjdb = Cj(0) ΦB 1 + VSB Cj(0) 1 + VDB ΦB overlap cap: Cov = WLDCox + WCfringe WE + junction sidewall cap (per length) Cjsw(0) ΦB 1 + VSB WE + Cjsw(0) 1 + VDB ΦB (W + 2E) (make 2W for "4 sided" perimeter in some cases) (W + 2E) gate to channel cap: Cgc = 2 C W(L-2LD) 3 ox channel to bulk cap: Ccb - ignore in this class H.-S. Lee & M.H. Perrott MIT OCW MOS AC Small Signal Model (Device in Saturation) RD RG ID RD Cgd vgs RG Cgs gmvgs -gmbvs ro Cdb Csb RS vs Cgs = Cgc + Cov = RS 2 C W(L-2LD) + Cov 3 ox Cgd = Cov Csb = Cjsb (area + perimeter junction capacitance) Cdb = Cjdb (area + perimeter junction capacitance) H.-S. Lee & M.H. Perrott MIT OCW Wiring Parasitics Capacitance - Gate: cap from poly to substrate and metal layers - Drain and source: cap from metal routing path to substrate and other metal layers Resistance - Gate: poly gate has resistance (reduce by silicide) long metal lines can add resistance - Drain and source: some resistance in diffusion region (reduce by silicide), and from routing long metal lines Inductance - Gate: poly gate has negligible inductance, but long wires can add inductance - Drain and source: becomes an issue for long wires Extract these parasitics from circuit layout H.-S. Lee & M.H. Perrott MIT OCW Frequency Performance of a CMOS Device Two figures of merit in common use - f : frequency for which current gain is unity - f : frequency for which power gain is unity t max Common intuition about ft - Gain, bandwidth product is conserved - We will see that MOS devices have an f that is a t function of bias This effect strongly impacts high frequency amplifier topology selection H.-S. Lee & M.H. Perrott MIT OCW Derivation of ft for MOS Device in Saturation id ID+id RLARGE Vbias Cgd iin vgs Cgs gmvgs -gmbvs Cdb ro iin Csb Assumption is that input is current, output of device is short circuited to a supply voltage - Note that voltage bias is required at gate The calculated value of ft is a function of this bias voltage H.-S. Lee & M.H. Perrott MIT OCW Derivation of ft for MOS Device in Saturation id ID+id RLARGE Vbias Cgd iin vgs Cgs gmvgs -gmbvs ro Cdb iin Csb H.-S. Lee & M.H. Perrott MIT OCW Derivation of ft for MOS Device in Saturation id iin slope = -20 dB/dec 1 H.-S. Lee & M.H. Perrott ft f MIT OCW Why is ft a Function of Voltage Bias? ft is a ratio of gm to gate capacitance -g is a function of gate bias, while gate cap is not (in strong inversion) m First order relationship between gm and gate bias: - The larger the gate bias, the higher the value for f t Alternately, ft is a function of current density - So f maximized at max current density (and minimum L) t H.-S. Lee & M.H. Perrott MIT OCW Unity Power Gain Frequency fmax From pages 176-178 (2nd ed.) 70-72 (1st ed.) of text book for derivation on fmax rg is the series parasitic gate resistance fmax can be much higher than fT: make gate resistance small (by careful layout) Output capacitance has no effect (can be tuned out by inductor) H.-S. Lee & M.H. Perrott MIT OCW Speed of NMOS Versus PMOS Devices NMOS devices have much higher mobility than PMOS devices (in typical bulk CMOS processes) - NMOS devices provide approximately 2.5 x g for a given amount of capacitance and gate bias voltage - Also, NMOS devices provide approximately 2.5 x I for a m d given amount of capacitance and gate bias voltage H.-S. Lee & M.H. Perrott MIT OCW Integrated Passive Components for RF Circuits We will only consider passive components appropriate for RF use High Q, low parasitics, and good linearity are generally desired (bias circuit is an exception) Well resistors, diffused resistors, poly-n+ capacitors even poly-poly capacitors do not perform very well in these regards H.-S. Lee & M.H. Perrott MIT OCW Polysilicon Resistors Use unsilicided polysilicon to create resistor A Rpoly A B B Key parameters - Resistance (usually 100- 200 Ohms per square) - Parasitic capacitance (usually small) Appropriate for high speed amplifiers - Linearity (excellent) - Accuracy (usually can be set within ± 15%) H.-S. Lee & M.H. Perrott MIT OCW MOS Resistors Bias a MOS device in its triode region Rds A W/L B A B High resistance values can be achieved in a small area (MegaOhms within tens of square microns) Parasitic capacitance is large (gate capacitance!) Resistance is quite nonlinear - Appropriate for small swing circuits or DC (bias) circuits H.-S. Lee & M.H. Perrott MIT OCW High Density Capacitors (Biasing, Decoupling) MOS devices offer the highest capacitance per unit area - Voltage must be high enough to invert the channel A A C1=CoxWL W/L Key parameters - Capacitance value - Raw cap value from MOS device is about 8-8.5 fF/µ2 for 0.18u CMOS Q (i.e., amount of series resistance) Maximized with minimum L (tradeoff with area efficiency) H.-S. Lee & M.H. Perrott MIT OCW MOS Capacitors, Cnt’d Putting NMOS capacitor in NWell allows operation at lower voltage + C COX V NMOS in N-well COV poly n+ VT - NMOS on substrate V Nwell n+ The non-linearity is often exploited in VCO designs as varactors H.-S. Lee & M.H. Perrott MIT OCW High Q Capacitors (Signal Path) Lateral metal capacitors offer high Q and reasonably large capacitance per unit area - Stack many levels of metal on top of each other (best layers are the top ones), via them at maximum density A A C1 B - Accuracy often better than ±10% - Parasitic cap is symmetric, typically less than 10% of cap B value H.-S. Lee & M.H. Perrott MIT OCW Stacked Lateral Flux Capacitor Example: CT = 1.5 fF/µm2 for 0.24µm process with 7 metals, Lmin = Wmin = 0.24µm, tmetal = 0.53µm -See “Capacity Limits and Matching Properties of Integrated Capacitors”, Aparicio et. al., JSSC, Mar 2002 H.-S. Lee & M.H. Perrott MIT OCW Fractal Capacitor Figure by MIT OCW. Maximizes perimeter area: up to 10x increase in unit capacitance Limited by lithography See A. Shanhani et. al., “A 12 mW, Wdie Dynamic Range CMOS Fron-End Circuit for Portable GPS Receiver,” Digest of Technical Papers, ISSCC 1997 H.-S. Lee & M.H. Perrott MIT OCW Spiral Inductors Create integrated inductor using spiral shape on top level metals (may also want a patterned ground shield) A A Lm B B - Key parameters are Q (< 10), L (1-10 nH), self resonant freq. - Usually implemented in top metal layers to minimize series resistance, coupling to substrate - See using Mohan et. al, “Simple, Accurate Expressions for Planar Spiral Inductances, JSSC, Oct, 1999, pp 1419-1424 - Verify inductor parameters (L, Q, etc.) using ASITIC http://formosa.eecs.berkeley.edu/~niknejad/asitic.html H.-S. Lee & M.H. Perrott MIT OCW Bondwire Inductors Used to bond from the package to die - Can be used to advantage package Adjoining pins From board die Lbondwire Cpin To chip circuits Cbonding_pad Properties - Inductance ( ≈ 1 nH/mm – usually achieve 1-5 nH) - Inductance value is difficult to control (chip-package alignment, bondwire height, etc.) - Q (much higher than spiral inductors – typically > 40) H.-S. Lee & M.H. Perrott MIT OCW Integrated Transformers Utilize magnetic coupling between adjoining wires A B Cpar1 k L1 L2 C Cpar2 C D Key parameters - L (self inductance for primary and secondary windings) - k (coupling coefficient between primary and secondary) A D B Design – ASITIC, other CAD packages H.-S. Lee & M.H. Perrott MIT OCW High Speed Transformer Example – A T-Coil Network A T-coil consists of a center-tapped inductor with mutual coupling between each inductor half B L2 CB X k L1 X A A B Used for bandwidth enhancement - See S. Galal, B. Ravazi, “10 Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18u CMOS”, ISSCC 2003, pp 188-189 and “Broadband ESD Protection …”, pp. 182-183 H.-S. Lee & M.H. Perrott MIT OCW Broadband Amplifiers H.-S. Lee & M.H. Perrott MIT OCW High Frequency, Broadband Amplifiers The first thing that you typically do to the input signal package is amplify it Connector Adjoining pins die Controlled Impedance PCB trace Driving Source Z1 Vin On-Chip L1 Delay = x Characteristic Impedance = Zo Transmission Line Function Key performance parameters Amp C1 C2 RL Vout VL - Boosts signal levels to acceptable values - Provides reverse isolation - Gain, bandwidth, noise, linearity H.-S. Lee & M.H. Perrott MIT OCW Gain-bandwidth Trade-off Common-source amplifier example Vdd RL vo vin Vbias + + - Ctot Ctot: total capacitance at output node DC gain 3 dBbandwidth Gain-bandwidth H.-S. Lee & M.H. Perrott MIT OCW Gain-bandwidth Trade-off Common-source amplifier example RL=RL1 RL=RL3 RL=RL3 Given the ‘origin pole’ gm/Ctot, higher bandwidth is achieved only at the expense of gain The ‘origin pole’ gm/Ctot must be improved for better GB H.-S. Lee & M.H. Perrott MIT OCW Gain-bandwidth Improvement How do we improve gm/Ctot? Assume that amplifier is loaded by an identical amplifier and fixed wiring capacitance is negligible Since and To achieve maximum GB in a given technology, use minimum gate length, bias the transistor at maximum When velocity saturation is reached, higher not yield higher gm In case fixed wiring capacitance is large, power consumption must be also considered H.-S. Lee & M.H. Perrott does MIT OCW Gain-bandwidth Observations Constant gain-bandwidth is simply the result of singlepole role off – it’s not fundamental! It implies a single-pole frequency response may not be the best for obtaining gain and bandwidth simultaneously Single-pole role off is necessary for some circuits, e.g. for stability, but not for broad-band amplifiers H.-S. Lee & M.H. Perrott MIT OCW
