Pulsar Design Mircea Bogdan Level 2 Pulsar - Production Readiness Review

Pulsar Design
Mircea Bogdan
Level 2 Pulsar - Production Readiness Review
Friday, Nov.7, 2003
Level 2 Pulsar – Hardware Requirements
Hotlink IO
Taxi IO
Level 1
Pulser And Recorder
to PCI
to PCI
Double width, 9U VME board inside L2 crate;
All the data interfaces that L2 decision crate has;
Data source for all trigger inputs;
Can record, reformat and retransmit data from upstream.
Can use S-LINK Mezzanine Cards for communication to remote PC.
Level 2 Pulsar - Design Issues
Factors considered: Price, existence of simulation models, functionality;
- FPGA for VME: EPM7128SOC160-7 - reuse from CDF Projects - $37.
- FPGAs for Data I/O and Control: EP20K400BC652-1XV - $1,000.
uses +3.3V for I/O, +5V tolerant, hand assigned pins,
- FIFO 4Kx18 : CY7C4245-10ASC – reuse from SVT Projects - $8.40;
- SRAM 128Kx36: CY7C1350-100AC - $40.45.
- we estimated +5V/13A;
- uses (+5V): 2.7A with no MC, 3.7A with 1 MC and ~7A with 4 MC;
- generates: +2.5V/3A Max with LM1085IT-Adj.;
- generates: +3.3V/15A Max with DATEL UNR-3.3/20 DC/DC;
Configuration Options:
- each FPGA has it’s own JTAG Chain with 3xEPC2LC20
and 10pin connector inside board;
- one big chain with all 3xFPGAs and 9xEPC2s and 10 pin
front panel connector.
Level 2 Pulsar – Mezzanine Cards
The board accepts 4 Mezzanine Cards, 2 for each Data I/O chip.
Each Mezzanine Card connected with Data(45:0) Bus and Ctrl(32:0) Bus
that go directly to the FPGA;
Connections are bi-directional for flexibility;
CARD_ID(3:0) for identity check at power-up; prevents signal contention
by keeping the I/Os in High Z;
Each MC is provided with +5V, +3.3V and +2.5V;
Design compatible with the Common Mezzanine Card Family Standard (CMC);
Two 64-pin surface-mount CMC connectors;
Mezzanine Cards: - Hotlink I/O 4xCypressRx/Tx or 2xRx/Tx + lvds - tested;
- Taxi I/O 4xAMD AM7968/9-175JC TAXI chips –tested;
- ODIN S-LINK interface – commercially available
32-bit data with/40MHzCLK/160MBytes/s max transfer rate;
Level 2 Pulsar – Aux Card
9U VME Aux Card
P3 connections: 2x S-Link I/O[45:0] + 1x Spare Bus[24:0]
FP connections: - 2x52 pin SVT/XTRP I/O Connectors;
- 2x68 pin TS I/O Connectors;
- 2x S-Link Card Connectors.
Power options:
•5V Aux card ~2A max (0.9A with 1 SLINK)
•3.3V Aux card ~2A(5V) max(0.7A with 1 SLINK)
The card generates +3.3V from +5V, using UNR-3.3/15-D5.
Level 2 Pulsar - Board Specifications
Level 2 Pulsar - Trace Analysis
We performed signal integrity test on some 80 nets on the board using the
Interconnect Synthesis Tool by Mentor Graphics.
Most of the IBIS (I/O Buffer Information Specification) models are vendor supplied.
For the FPGAs we used QuartusII generated IBIS models.
With no termination
With 33Ohm Series Termination on the Source.
Level 2 Pulsar – Multi Board signal integrity
We performed signal integrity tests for some nets on the Pulsar Board together with
HotLink Rx and Tx mezzanine cards using the IS_Multi Board tool by Mentor Graphics.
For the 1mm FH Mezzanine (IEEE 1386), BTB, Surface Mount connectors
we used vendor supplied Lumped Constant Model.
Level 2 Pulsar – Crosstalk
For this board's stackup and considering 1ns rising edge, we have -21.02 dB calculated cross
talk coefficient on micro strip traces running 10 mils apart for 4 inches and -18.81 dB on
stripline traces.
We performed cross talk tests for some nets on the board, using the Interconnect Synthesis tool
by Mentor Graphics.
Level 2 Pulsar - Functional Simulation
•Multi-board simulation:
-instantiate Pulsar along with MCs in a top level schematic with DA;
-run QSII with all the boards working together: 4xTx HotLink + 4xRx HotLink + Pulsar.
Level 2 Pulsar - Layout Top
Level 2 Pulsar - Layout Award
Level 2 Pulsar – Status –Nov.7, 2003
• We tested the two “First Item” boards from Promex;
• Will make 8 more boards in this production batch;
For new production batches with more that 20 boards we estimate:
$150/board – Assembly;
$1,300/board – Parts(No Altera) + PCB;
$3,250/board – Altera parts.
--------------------~$4,700/board - Total
All the required documents are on the web: