PWM System
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
1
Pulse Width Modulation (PWM)
• Pulses are continuously generated which have different widths but the
same period between leading edges
• Duty cycle (% high) controls the average analog voltage of the output
signal
• Uses: DC motor control, positional servo control, audio communication
(cellular phones), low cost digital to analog conversion for such things as
telephone tone generation
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
2
Software Approach
• Assume
– PER is the desired period in microseconds
– DUTY is the desired duty cycle (%)
• Then calculate
– PWIDTH = DUTY * PER
– OFFTIME = PER – PWIDTH
PER
PWIDTH OFFTIME
• Algorithm:
Disadvantages:
Repeat forever:
Turn on output pin
Delay for PWDITH microseconds
Turn off output pin
Delay for OFFTIME microseconds
Microcomputer Architecture and Interfacing
Colorado School of Mines
• Wastes a lot of CPU time
doing delay loops
• CPU can only do one
thing
Professor William Hoff
3
Hardware Approach
• We can automatically generate a PWM signal using simple
digital hardware elements
–
–
–
–
T flip flop
Register
Comparator
Counter
• T flip flop
– Toggles its state if the T input = 1
T
Q
Res /Q
T
Qt + 1
0
Qt 
1
Qt 
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
4
Register
• A collection of D flip-flops
8-bit register
D0
D
Q
Q0
pre
D[7..0]
D1
D
Q
Q1
Q[7..0]
Clk
clr
Dn-1
D
Q
Qn-1
Parallel load,
parallel access
Clk
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
5
Comparator
• A combinational circuit that just compares
two N-bit numbers
8
8
Comparator
Eq
– When they are equal it outputs a “1”
• XOR is a 1-bit comparator
a
a
DIFF = a $ b
b
EQ = (a $ b)’
b
• To compare two N-bit numbers for equality
a0
b0
a1
EQ
b1
:
an-1
bn-1
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
6
Counter
1
T
Q
Q0
Q0
T
Q
Q1
Q0
Q1
T
Q
Q2
Q0
Q1
Q2
T
Q
Q3
• A sequential circuit that automatically
counts up by 1 every clock tick
– When reset is asserted, or count reaches a
maximum, goes to 0
Clock
n-bit
counter
8
Reset
• An n-bit counter can be constructed
by chaining together n flip-flops (T or
D)
– In a synchronous counter, all the f/f’s
change state simultaneously with the clock
Microcomputer Architecture and Interfacing
Clk
Colorado School of Mines
Professor William Hoff
7
PWM generation - hardware approach
This comparator fires when count reaches PWMDTY...
it then causes T to toggle (Q goes to 1 and /Q to 0)
PWMPER
T flip flop
Clk
8-bit
counter
T
Comparator
Q
PWMDTY
Clk
Reset
8-bit register
(PWMDTY)
Res
This comparator fires when
count reaches PWMPER... it
then resets the counter and
forces Q to 0 (and /Q to 1)
Comparator
8-bit register
(PWMPER)
•
•
Microcomputer Architecture and Interfacing
Colorado School of Mines
/Q
Just load registers PWMDTY,
PWMPER in units of clock ticks
No further action needed!
Professor William Hoff
8
PWM generation - hardware approach
• We have a free running counter (incremented by system clock)
• We have one register for the pulse width and the other for the period
– At the start of the period, the counter is zero and the output is high
– When the value in the counter equals the value in the first register, the output goes low
– When the value in the counter equals the value in the 2nd register, the output goes high
and the counter resets to zero
counter starts
counting from 0
count
matches 1st
register
count
matches 2nd
register
• We have a
choice of
polarity: pulse
high or pulse
low
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
9
Clock signal and PWM
period = # clock
ticks in this interval
one
clock
tick
duty = # clock ticks
in this interval
clk
PWM
out
start of
period
end of
duty
end of
period
The duration of one clock tick is the resolution
by which we can set duty and period time
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
10
Free running
counter
8-bit counter
GATE
(clock edge sync)
PWMCNTx
up/
down
1. When count
reaches PWMDTY,
force output low
reset
clock
source
This is the E-clock (or a
scaled version of it)
8-bit compare=
PWMDTYx
T
R
8-bit compare=
From port PTP
data register
Q M
U
Q X
M
U
X
to pin
driver
PPOLx
PWMPERx
2. When count
reaches PWMPER,
force output high
PWMEx
Q
T
Q
R
CAEx
Figure 8.44 PWM channel block diagram
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
11
Clock for PWM
• The E-clock is really fast!
– At 24 MHz, one clock tick is 0.042 us (microseconds)
• If we let the counter count at that frequency, we could only
have very short periods
– Maximum period would be 256 ticks, or 10.7 us
• To allow longer periods, we scale (reduce the frequency) of
the E-clock
• There are two clock divider stages:
– First divider divides by M, where M=1,2,4,8, …, 128
– Second is an additional divide by 2*N, where N is any number, 1
through 256
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
12
PWM Clock
• You can use the clock from the first divider (Clock “A”) or from
the second divider (Clock “SA”, or “Scaled A”)
– Clock A is the system clock divided by M, where M=1,2,4,8, …, 128
– Clock SA is generated by an additional division by N*2, for N=1 through 256
First Divider
System Clock
(24 MHz)
/1, 2, 4, ..., 128
Second Divider
/N, N=1..256
/2
Clock SA
Clock A
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
13
Clock A
• Here are the choices you have for the prescalar (assuming a
24 MHz E-clock):
M
Clk A freq
one tick
256 ticks
1
2
4
8
16
32
64
128
24000000
12000000
6000000
3000000
1500000
750000
375000
187500
4.17E-08
8.33E-08
1.67E-07
3.33E-07
6.67E-07
1.33E-06
2.67E-06
5.33E-06
1.07E-05
2.13E-05
4.27E-05
8.53E-05
1.71E-04
3.41E-04
6.83E-04
1.37E-03
Clock A is the Eclock prescaled
by dividing by
M
Microcomputer Architecture and Interfacing
This is the time
for one clock A
period (is just
1/frequency)
Colorado School of Mines
This is the maximum
period you can have
with an 8-bit counter
(256 ticks)
Professor William Hoff
14
Examples of clock scaling
•
If we want a period of 10 us
– At the 24 MHz E-clock rate, each clock tick is 0.042 us
– The desired period is (10 us)/(0.042 us) = 240 ticks
– This value fits in the 8-bit PWMPER register, so no scaling is necessary (either using the
prescaler or the clock divider)
– We can use clock A with M=1
•
If we want a period of 20 us
– If we used the 24 MHz E-clock, the period would be 480 ticks, which is too big for 8 bits
– We can prescale the E-clock by a factor of 2 … this produces clock A at 12 MHz. Each clock tick
is 0.083 us.
– Then the period is (20 us)/(0.083 us) = 240 clock ticks
– We can use clock A with M=2
•
Of course, prescaling by larger values of M also works
– Example: M=4 yields a clock at 6 MHz
– Then a period of 20 us is 120 clock ticks
– But in general we want to have as much resolution as possible (ie, period close to 256 ticks)
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
15
Longer periods – e.g., 1 ms
•
At the 24 MHz E-clock rate, each clock tick is 0.042 us
– The desired period is (1 ms)/(0.042 us) = 24000 ticks … too big
– We can scale by dividing 24MHz by some number, 2*N, where N=1..256, to produce clock SA
•
Let’s try to get the period down to 240 clock SA ticks
– We can do this by dividing clock A by 100 (so N=50)
– Then clock SA is 24 MHz/100 = 240 kHz; one SA tick is 4.2 us
– Then (1 ms)/(4.2 us) = 240 ticks, so ok
•
We select clock SA and use M=1, N=50
First Divider
System Clock
(24 MHz)
/1, 2, 4, ..., 128
Second Divider
/N, N=1..256
/2
Clock SA
Clock A
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
16
Other combinations
• Actually, many possible combinations would yield a period of 1 ms
M
1
2
4
8
16
32
64
128
clock A freq 1 Clk A tick 256 ticks
24000000 4.17E-08 1.07E-05
12000000 8.33E-08 2.13E-05
6000000 1.67E-07 4.27E-05
3000000 3.33E-07 8.53E-05
1500000 6.67E-07 1.71E-04
750000 1.33E-06 3.41E-04
375000 2.67E-06 6.83E-04
187500 5.33E-06 1.37E-03
N
50
25
12
6
3
2
1
1
SA freq 1 Clk SA tick 256 ticks
240000 4.17E-06 1.07E-03
240000 4.17E-06 1.07E-03
250000 4.00E-06 1.02E-03
250000 4.00E-06 1.02E-03
250000 4.00E-06 1.02E-03
187500 5.33E-06 1.37E-03
187500 5.33E-06 1.37E-03
93750 1.07E-05 2.73E-03
These combinations of
M,N are ok
# SA ticks
in 0.001 sec
240.0
240.0
250.0
250.0
250.0
187.5
187.5
93.8
This is the period in terms
of # of Clock SA ticks
You probably don’t want a combination
with a non-integral # ticks
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
17
Example
• Find a combination of M,N that yields a 20 ms period (assuming 24 MHz
system clock)
First Divider
System Clock
(24 MHz)
/1, 2, 4, ..., 128
Second Divider
/N, N=1..256
/2
Clock SA
Clock A
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
18
Summary / Questions
• The PWM system accomplishes in hardware what
you could also do in software. What is the benefit of
doing it in hardware?
• What are the key digital logic components that make
up the PWM system?
Microcomputer Architecture and Interfacing
Colorado School of Mines
Professor William Hoff
19