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Published in IET Power Electronics
Received on 24th April 2012
Revised on 23rd October 2012
Accepted on 13th November 2012
doi: 10.1049/iet-pel.2012.0221
ISSN 1755-4535
Experimental evaluation of four-phase floating
interleaved boost converter design and control
for fuel cell applications
Mohammad Kabalo1, Damien Paire1, Benjamin Blunier1, David Bouquain1,
Marcelo Godoy Simões 2, Abdellatif Miraoui1
1
IRTES-SET, Université de Technologie de Belfort-Montbéliard, Belfort 90010, France
Colorado School of Mines – Engineering Division, 1610 Illinois St., Golden, CO 804010-1887, USA
E-mail: kabalomohammad@gmail.com
2
Abstract: Power electronic converters are essential part of hybrid fuel cell automotive application systems. The converter needs to
provide high-voltage ratio for a wide range of input voltage. In addition, the converter should have high efficiency for a wide
range of duty cycle control range. A four-phase floating interleaved boost converter (FIBC) is analysed and a small-signal AC
model using an averaged pulse-width modulation (PWM) switch technique is used for supporting the feedback controller and
aiding a frequency response design. The small-signal AC model as well as the current controller are validated by simulation
and evaluated by experimental results. The proposed converter has competitive device ratings, the total inductance volume
and weight is decreased, current ripple is minimised and converter efficiency and reliability are improved. Proof of concept of
the proposed topology is demonstrated through an experimental prototype.
1
Introduction
In the last few years, the fuel cell (FC) technology related to
energy conversion has been showing a lot of promises for
using hydrogen as a long-term energy storage vector, by
converting its chemical energy into electrical energy, with
higher efficiency than thermodynamical cycles [1]. In
addition, FC-powered vehicles have been developed as a
possible solution for transportation needs. However, the
electrical system must use a low-voltage FC for supplying
higher-voltage systems, particularly the electric vehicle
powertrain system. Therefore it is mandatory to use a
DC–DC boost converter in order to raise the voltage to a
few hundred volts for a suitable and cost-effective vehicle
drive system [2, 3]. The key requirements of a DC–DC
converter for such application are the need of high-voltage
ratio with low-input current ripple, because high-current
ripple decreases the FC lifetime [4, 5]. Another aspect of
current ripple is that it not only affects the lifespan, but also
its capacity and fuel consumption [6]. It has been suggested
that the current ripple should be limited to less than 10% of
the nominal FC current [6]. In addition, volume, weight and
efficiency of a DC–DC converter are very important
characteristics for an overall improved system. The literature
shows previous studies where batteries are used to prevent
transient response of FCs, such as a multi-port
transformer-based topology [7]. A cascade DC–DC converter
composed of two-phase interleaved boost converter and
three-level series boost converter is proposed in [8–11]. This
solution suffers from low efficiency and poor reliability. In
IET Power Electron., pp. 1–12
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[12–14], a parallel resonant converter with a capacitor as
output filter is proposed. However, in this topology the
determination of the leakage inductance and capacitance is
very complex as well as the topology modelling. It is
possible to increase the FC output voltage without using
extra power electronic devices by using a Z-source inverter
[15, 16]. The major problem related to this topology is that it
requires an adequate control of the inverter to achieve the
desired DC-bus voltage, because the boost action happens
during modulation of the dead-time of the transistors [17,
18]. This paper proposes a four-phase floating interleaved
boost converter (FIBC) as the best solution for matching the
characteristics of an FC for an electric vehicle powertrain.
The small-signal AC model of the proposed converter is
developed using averaged PWM switch technique, and a
current controller using frequency response technique is
designed. The small-signal AC model, as well as the
current controller, is validated by simulation and
experimental results.
2
Operation principle and design
The proposed four-phase FIBC is shown in Fig. 1.
The floating output with interleaved input allows reduction
of current rating and voltage stresses for the semiconductors,
making this topology more cost-effective than the
conventional boost and interleaved boost converter [19–21].
The concept of interleaving input (parallel connexion) and
floating output (series connexion) permits the proposed
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Fig. 1 Proposed converter topology
topology to have the following benefits over DC–DC
converters [22]:
voltage-ratio and the efficiency of a standard boost
converter, taking into account common parasitics, showing
their strong dependence on non-ideal components [24].
† Increased overall converter efficiency.
† Increased converter voltage-ratio.
† Increased input and output ripple frequency without
increasing the switching frequency (saving on losses).
† Decreased input ripple current (contributing for longer FC
lifespan).
† Enhanced system reliability by paralleling phases
(advantageous over paralleling multiple devices).
† Decreased current and voltage ratings of power
electronic devices (making possible the use of
commercial-off-the-shelf components).
† Reduced size of the passive components (decreasing the
total volume and weight);
′
′
VFC − DVS − DVD DR
M (D) =
′
VFC x − rin VFC − DVS − DVD
Details and analysis concerning the reduction of the input
current ripple, plus discussions on the volume and weight
of the passive component and efficiency improvement has
been previously presented by the authors [23]. To ensure
the minimum current ripple at the converter input, the four
control signals have to be 90° out of phase. The power
source specifications, the required DC-bus voltage and the
switching frequency are listed in Table 1.
The first design step is to determine the required
voltage-ratio. Equations (1a) and (1b) show the
′
′
VFC − DVS − DVD D 2R
h=
′
VFC x − rin VFC − DVS − D VD
(1a)
where
(1b)
′
′
x = rL + rin + DrS + D rD + D 2R
The voltage-ratio and the efficiency of a four-phase FIBC are
given by (2a) and (2b), respectively.
′
′
VFC − DVS − D VD 2RD (1 + D)
M (D) =
′
VFC j − 2rin (1 + D)2 VFC − DVS − DVD
′ ′
2RD 2 VFC − DVS − DVD
h=
′
VFC j − 2rin (1 + D)2 VFC − DVS − DVD
(2a)
(2b)
Table 1 System specifications
Parameter
Value
FC-rated power, PFC
FC-rated current, IFC
input current ripple, Δiin
FC-rated voltage, VFC
DC-bus voltage, VBus
switching frequency, fs
5 kW
70 A
5A
72 V
400 V
20 kHz
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where
′
′
j = (1 + D) rL + DrS + D rD + 2rin (1 + D) + 2RD 2
′
where D is the duty-cycle, D = 1 − D, VS, VD are the switch
and the diode on-state voltage drops, rin, rL, rS, rD, R are the
internal source resistor, ESR inductor resistor, on-state switch
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resistor, on-state diode resistor and the load resistor,
respectively. It is very important to compare the
voltage-ratio and efficiency of the proposed topology with a
standard converter. Thus, Fig. 2a shows that for the same
duty cycle, a four-phase FIBC has a higher-voltage gain
than a traditional boost converter and Fig. 2b shows that the
four-phase FIBC has a very high efficiency for a wider
range of duty cycle, showing an improved performance
when compared to a traditional boost converter with lower
efficiency when increasing duty cycle.
Using (2a) and neglecting common parasitics, the required
duty-cycle can be calculated as follows
D=
VBus − VFC
= 70%
VBus + VFC
(3)
The current and voltage ratings of the power switches (S1, S2,
S3, S4) and the diodes (D1, D2, D3, D4) of the proposed
four-phase FIBC are given by
Is = I D =
IFC
2(1 + D)
Vs = |VD | =
Vbus
(1 + D)
(5)
Taking into account the system specifications presented in
Table 1, the current and voltage ratings of the power
devices of four-phase FIBC are given by
Is = ID = 20.6 A
(6)
Vs = |VD | = 235 V
(7)
The value of the semiconductor switch voltage is slightly
higher than the half of the DC-bus voltage, which permits
to reduce the switching losses and increase the power
devices utilisation factor. In addition, the cost of the
switches with high-voltage and current ratings is more than
that of the switches with low voltage and current ratings
(minimisation of total switch ratings leads to reduced loss,
and to minimisation of total silicon area required to build
the power devices of the converter).
(4)
2.1
Inductors and capacitors sizing
The multiphase structure reduces the effective (root mean
square (RMS)) current per phase, thus reducing I 2R
conduction losses, without paralleling multiple devices.
Also, the reduction in RMS current permits the inductor
volume to be reduced. The interleaving concept and the
phase shift of (360/N)° (N is the number of phases)
between the control signals permit the inductor current
ripple to be increased and consequently the inductor value
and volume have to be decreased. The reduction in passive
components and heatsink also implies potential reduction in
size and weight as well as savings in cost. The switches
gate signals, the input current, the inductors current, the
capacitors current and the output voltage for a duty cycle
(50% < D < 75%) are depicted in Fig. 3.
From Fig. 3 and during the interval (t4 < t < t5), the
following equations can be written
diL1
dt
diL3
dt
=
=
VFC diL2 VFC
=
;
L1
dt
L2
VFC diL4 VFC − VC2
=
;
L3
dt
L4
−I dvC2 Iin − 3Io
= o;
=
dt
C1
dt
4c2
dvC1
(8a)
(8b)
The input current and the DC-bus voltage dynamic are given
by
diiin diL1 diL2 diL3 diL4 dio
=
+
+
+
−
dt
dt
dt
dt
dt
dt
(9a)
Fig. 2 Voltage ratio and efficiency comparison
dvBus dvC1 dvC2 dvFC
=
+
−
dt
dt
dt
dt
(9b)
a Boost ratio against four-phase FIBC ratio
b Boost efficiency against four-phase FIBC efficiency
Using (8a), (8b), (9a) and (9b), the inductor and the capacitor
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Fig. 3 Idealised waveforms of a four-phase FIBC
value can be obtained as follows
L=
(3 − 4D)(D − 0.5)VBus
= 100 mH
(1 + D)Diin fs
(10)
(3 − 4D)(D − 0.5)VBus
2(1 − D)DvBus Rfs
(11)
C=
The inductor current ripple can be obtained by
DiL =
D(1 − D)VBus
(1 + D)Lfs
(12)
The critical value of the inductor current ripple keeping the
converter in continuous conduction mode (CCM) can be
calculated as follows
DiLcri =
IFC
1+D
(13)
The proposed converter is designed to be used in hybrid FC
electric vehicle with a DC-bus battery pack of 400 V. The
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battery will provide peak-power during the vehicle
acceleration, and the DC–DC converter between the FCand the DC-bus will force this later to work in its optimal
zone (it is the zone where the FC current varies between
(50 A < IFC < 70 A)). As the FC output characteristic is
non-linear, its voltage in the optimal zone vary between
(72 V < VFC < 87 V). By using (3), one can see that the duty
cycle varies between (64% < D < 70%).
The inductor current ripple for (D = 64%) can be calculated
from (12)
DiL = 28 A
The critical value of the inductor current ripple keeping the
converter in CCM can be calculated by using (13)
DiLcri = 30.48 A
The inductor current ripple for (D = 70%) is
DiL = 24.7 A
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quantities could be given by (16) and (17).
The critical value of the inductor current ripple is
DiLcri = 41.17 A
v1 (t) =
Therefore the selected inductor value guarantees the CCM of
the proposed converter for the previous variation of the duty
cycle (under steady-state conditions).
For stability reasons the capacitor value has been chosen to
be (C = 1 mF). The RMS capacitor current of the proposed
converter and the standard boost converter can be obtained
from (14) and (15), respectively.
i1 (t) =
IRMSC1,C2
4D − 4D2 − 0.5
= IFC
= 12 A
4(1 + D)2
IRMSC = IFC D(1 − D) = 27 A
′
0,
v′ 1 (t),
0 ≤ t ≤ dTs
dTs ≤ t ≤ Ts
(16)
0,
i1 (t),
0 ≤ t ≤ dTs
dTs ≤ t ≤ Ts
(17)
where Ts is the switching period and d is the duty cycle.
′
The averaged dependent generators kv1 (t)lTs and ki 1 (t)lTs
are expressed as functions of the independent switch
′
waveforms ki1 (t)lTs , kv1 (t)lTs and the control input d(t).
′
′
kv1 (t)lTs = d (t)kv 1 (t)lTs
(14)
′
ki′1 (t)lTs = d (t)ki1 (t)lTs
(19)
′
(15)
The proposed topology has more important reduction in RMS
capacitor current when compared to the classic boost
converter, which reduces the electrical stress in the output
capacitor and improve the converter reliability and lifespan.
3 Development of a four-phase FIBC
small-signal AC model
The PWM-switch methodology can be used for finding the
small-signal AC model of the four-phase FIBC leading to
an equivalent model with time-invariant voltages and
currents sources [25–28]. The waveforms of the voltage and
current generators must be as the switches waveforms of the
original converter. After the time-invariant circuit network
is obtained, the converter waveforms are averaged over one
switching period in order to remove the harmonics.
Fig. 4 defines the switches networks and their terminals of
the two non-floating versions of the four-phase FIBC.
The terminal
quantities of the first switch
network are v1(t),
′
′
i1(t), v′ 1 (t), i1 (t) and i1(t), i2(t), v′ 2 (t), i 2 (t) for the second
switch network. Two terminal quantities of each switch
network can be treated as independent inputs to the switch
network and the remaining two terminal quantities are
viewed as dependent signals, that is, as functions of the
independent terminal inputs and the control input. By
choosing
i1(t) and v′ 1 (t) as the independent inputs and v1(t)
′
and i1 (t) as dependent sources, the instantaneous terminal
where d (t) = 1 − d(t). The average value is found by
evaluation of
1
kx(t)lTs =
Ts
t+Ts
x(t) dt
L1
dĩL1 (t)
dt
= ṽFC (t) − rL1 ĩL1 (t) + d̃ 1 (t)VC1
′
′
− D1 ṽC1 (t) − D1 rC1 C1
dĩL2 (t)
dt
′
L3
dĩL3 (t)
dt
dṽC1 (t)
dt
= ṽFC (t) − rL2 ĩL2 (t) + d̃ 1 (t)VC1
′
− D1 ṽC1 (t) − D1 rC1 C1
Fig. 4 Switch networks and their terminals of the two non-floating
versions of the four-phase FIBC
(20)
t
A similar approach is considered for the second switch
network, as well as for the remaining two switches
networks of the floating versions. By replacing the
converter switches networks with their dependent voltages
and current sources, the time-invariant circuit of the
four-phase FIBC is illustrated in Fig. 5.
The instantaneous duty-cycle d1(t) and d2(t) are sent to the
floating and non-floating sub-systems of the four-phase FIBC.
The averaged dependent voltages and current waveforms is
valid for small signal and the model is non-linear because
of the cross-multiplication of time-varying quantity d1(t)
with other time-varying quantities such as ĩL1 (t) and ṽC1 (t).
If the small AC variations are negligible when compared to
their quiescent values, the linear small-signal AC model of
the four-phase FIBC can be approximated, as shown in Fig. 6.
The transfer functions relating the duty-cycle to output
voltage Gdvo (s) and the duty-cycle to the inductor current
Gid(s) are obtained from the linearised differential
equations, developed from the small-signal AC circuit
model. These equations are defined as follows
L2
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(18)
dṽC1 (t)
dt
= ṽFC (t) − rL3 ĩL3 (t) + d̃ 2 (t)VC2
′
′
− D2 ṽC2 (t) − D2 rC2 C2
dṽC2 (t)
dt
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Fig. 5 Time-invariant circuit of the four-phase FIBC
Fig. 6
Small-signal AC circuit model of the four-phase FIBC
L4
dĩL4 (t)
dt
′
′
− D2 ṽC2 (t) − D2 rC2 C2
C1
The duty-cycle to output voltage and the duty-cycle to
inductor current small-signal transfer functions of a
four-phase FIBC converter with resistive load are given by
= ṽFC (t) − rL4 ĩL4 (t) + d̃ 2 (t)VC2
dṽC2 (t)
dt
Gdvo (s) =
dṽC1 (t)
′
′
= D1 ĩL1 (t) + D1 ĩL2 (t) − d̃ 1 (t)IL1
dt
1 − (s/wzr ) 1 + (s/wzl )
ṽo (s)
= Kv
1 + (s/(wo Q)) + s2 /w2o
d̃(s)
(22)
1 + (s/wzi )
ĩL (s)
= Ki
1 + (s/wo Q) + (s2 /w2o )
d̃(s)
(23)
GdiL (s) =
− d̃ 1 (t)IL2 − ĩo (t)
where
C2
dṽC2 (t)
dt
′
′
= D2 ĩL3 (t) + D2 ĩL4 (t) − d̃ 2 (t)IL3
− d̃ 2 (t)IL4 − ĩo (t)
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(21)
Kv =
Vin 2R(1 − D)2 − rL (1 + D)
(1 − D)2 R(1 − D)2 + rL
(24a)
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wzr =
2R(1 − D)2 − rL (1 + D)
L(1 + D)
(24b)
1
rC C
(24c)
wzl =
Ki =
VFC (D + 3)
2(1 − D) R(1 − D)2 + rL
1
RC/(D + 3) + rC C
1
2R(1 − D)2 + 2rL
wo = √
R + 2rC
LC
wzi =
Q=
wo (R + 2rC )LC
RC rL + 2rC (1 − D)2 + 2(L + rC rL C)
(24d)
(24e)
(24f)
(24g)
The transfer functions (22) and (23) are second-order systems
with a double pole with corner frequency given by (25a),
RHP zero (24a) and ESR zero (24a). The corner frequency
and the right half plane zero are functions of nominal duty
cycle D. In a closed-loop system, the system elements will
change as the duty-cycle changes, which means that the
transfer function changes accordingly. This makes
controller design for the four-phase FIBC much more
challenging from the stability and bandwidth point of view.
4
Fig. 8 shows the bode diagram of the uncompensated and
compensated current loop gain.
Fig. 8 shows a good system performance as regarding
ringing and overshoot due to the good phase margin (PM =
90°) [30, 31]. But the system may have steady-state error
due to a very low gain at low frequency (∼0 dB) and a
lag-controller must be used for compensation. The
uncompensated closed-loop gain has a crossover frequency
of wcross = 17.2 × 103 rad/s (this is the frequency at which
the magnitude falls to 1.0 (0 dB)). This crossover frequency
should be as high as possible (approximately an order of
magnitude below the switching frequency) to allow the
system to have good transient response. The crossover
frequency of the compensated closed-loop gain has been
chosen to be fc = 800 Hz. The transfer function of the
lag-controller is given by
Glag (s) = Klag 1 + wi /s
fi =
A(s) =
Gc (s)Gp (s)GdiL (s)
ĩL (s)
=
ĩLref (s) 1 + Gc (s)Gp (s)Gid (s)Hf (s)
Klag = 2 × 10−3
(28a)
fc
= 400 Hz
2
(28b)
Kf
1 + Tf s
Fig. 7 Proposed current control loop
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fi =
The system sensitivity, S(s) of A(s) for variation in GdiL (s) is
given by (30).
S(s) =
dA/A
1
=
dGid /Gid 1 + Gc (s)Gp (s)Gid (s)Hf (s)
(29)
(25)
where Gc(s) is the current controller transfer function, Gp(s) is
the transfer function of the pulse-width modulator, which can
initially be considered to be 1 (for peak-to-peak sawtooth
magnitude equal to 1) and disregarding any transport time
delay (it can be modified if such effects should be
considered) and Hf(s) is the inductor current measurement
filter transfer function
Hf (s) =
(27b)
In order to increase the low-frequency gain of the system and
to obtain a PM of 68° keeping the same crossover frequency,
the lag-controller gain Klag and the inverted zero fi are found
to be
Controller design
In order to achieve instantaneous power sharing between the
phases of the four-phase FIBC and a good power
management of the system, each converter phase has its
own decoupled current control loop [29]. A current control
loop for the floating and non-floating circuits for the
four-phase FIBC is shown in Fig. 7. The current control
closed-loop transfer function is expressed as follows
wi
f
= c
2p K fi
(27a)
Fig. 9 shows the system sensitivity and the current loop gain,
where very small low-frequency sensitivity (about –60 dB)
indicates that A(s) is not impacted by variations in GdiL (s)
and the high gain at low frequency (about 60 dB) of the
(26)
Fig. 8 Frequency response of compensated current loop gain
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Fig. 9 Compensated system response and system sensitivity
Table 2 Current control loop parameters
Parameters
Value
1
22 μs
2 × 10 − 3
2
400 Hz
Kf
Kf
Klag
Kfi
fi
compensated system response indicates that the system has no
steady-state error, as specified.
Table 2 summarises the current control loop parameters.
The dynamic response of the proposed current controller
for an inductor current step from 15 to 30 A is shown in
Fig. 10. It can be observed that the proposed current
regulator has very high performance and improved time
response with low overshoot.
5
5.1
Experimental validation
Experimental set-up
An experimental set-up for the four-phase FIBC is depicted in
Fig. 11. Each inductor current has a zero-flux Hall-effect
current sensor for feedback control where the inductor
current reference iLref is generated by a real-time board
dSPACE DS1104 where the Matlab–Simulink control
system has been transferred through the ControlDesk
software. Experimental results have been obtained by an FC
power emulator [32, 33]. The benefits of interleaving the
input current ripple make the control signals of the main
switches to be shifted 90° from each other. In the
experimental evaluation implemented for this project, the
control signals are shifted by means of an FPGA control
card. It has to be noted that the value of the sampling and
the switching frequencies are 15 and 20 kHz, respectively.
The specification of the implemented four-phase FIBC are
detailed in Table 3.
5.2
Experimental results
Figs. 12 and 13 show the system dynamic response for
step-up from 15 to 30 A and then step-down to 15 A, and
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Fig. 10 Reference step-up from 15 to 30 A for input voltage of
72 V
a
b
c
d
e
Inductor current reference (ILref )
L1 current (IL1 )
L2 current (IL2 )
L3 current (IL3 )
L4 current (IL4 )
for step-down from 20 to 10 A and then step-up to 20 A for
input voltage of 72 V. The currents follow their reference
perfectly, without any noticeable ringing or overshoot.
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Fig. 11 Experimental set-up for the four-phase FIBC
a Implemented four-phase FIBC converter
b Four-phase FIBC prototype
c Test bench
Fig. 14 shows the steady-state FC current, the current at the
input of the converter and the inductors current for an
inductor current reference of 18 A. It indicates that the
proposed current control loop has excellent steady-state
performance with negligible steady-state error ∼18 A.
Table 3 Four-phase FIBC specification
Device
power IGBT: S1 to S4
diodes: D1 to D4
diodes: D0
inductors: L1 to L4
filter inductor: Lf
capacitors: C1, C2
filter capacitor: Cf
Specification
4 × CM100DUS-12F
anti-parallel diodes of CM100DUS-12F
MEK 75–12 DA
4 × (100 μH Cefem)
4 μH Cefem
2 × 2200 μF electrolytic
37 μF electrolytic
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A second-order low-pass filter (Lf, Cf ) is used to filter the
HF current ripple generated at the converter input. The FC
current ripple becomes nearly negligible, which contributes
for the FC lifespan to be increased and the fuel consumption
to be decreased. An active method can be used to filter
the HF current ripples generated by current-fed DC–DC
converter as proposed in [34]. However, such a solution
increases the system components and complexity.
The FC current waveforms underline the great benefit of
the four-phase FIBC from the current ripple reduction point
of view. One can go from 22 A current ripple in the
inductors to nearly zero current ripple of the FC current.
The implemented converter has an efficiency of 94.7% at
power demand of 5 kW (operating point). Such efficiency is
very good for intensive current low voltage power source
and much higher than an equivalent traditional DC–DC
boost converter for the same application.
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Fig. 12 Reference step-up from 15 to 30 A and then step-down to
15 A for input voltage of 72 V
a
b
c
d
e
Inductor current reference (ILref )
L1 current (IL1 )
L2 current (IL2 )
L3 current (IL3 )
L4 current (IL4 )
6
Conclusion
A floating interleaved DC–DC boost converter was designed
and implemented for FC-powered vehicle systems. The
proposed topology provides a strong mitigation of the input
10
& The Institution of Engineering and Technology 2013
Fig. 13 Reference step-down from 20 to 10 A and then step-up to
20 A for input voltage of 72 V
a
b
c
d
e
Inductor current reference (ILref )
L1 current (IL1 )
L2 current (IL2 )
L3 current (IL3 )
L4 current (IL4 )
current ripple, and allows current sharing between the
phases for decreased semiconductor stresses, improving the
converter efficiency and reliability. A four-phase FIBC
converter was presented, analysed, simulated, implemented
and compared to traditional boost converters, and system
IET Power Electron., pp. 1–12
doi: 10.1049/iet-pel.2012.0221
www.ietdl.org
Fig. 14 Current control loop steady-state response for inductors current reference of 18 A at input voltage of 72 V
a FC current
b Input current
c Inductors current
parameters such as voltage ratio, efficiency and input current
ripple were improved by the proposed design. A small-signal
AC -model was proposed using an averaged PWM switch
method in order to support the design of the current
feedback control using frequency response and a validation
using Simulink–Simplorer co-simulation aided the final
implementation.
The
prototype
was
evaluated
experimentally and the theoretical methodology was fully
validated for this design, and it is expected that it can easily
retrofit any FC-powered electric vehicle system.
7
Dedication
The authors dedicate this paper to the memory of their friend
and co-author, Dr. B. Blunier, formerly an Associate
Professor with the Université de Technologie de Belfort –
Montbéliard, who passed away on February 23, 2012.
8
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