International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 4, Issue 2, February 2015
ISSN 2319 - 4847
Signal Integrity Analysis of MLGNR
interconnects with FinFET driver for
technology beyond 16nm
Vangmayee Sharda1* and R. P. Agarwal2
1
Assistant Professor, AITEM, Amity University, Sec-125, Noida, Uttar Pradesh, India
2
Vice Chancellor, Shobhit University, Meerut, Uttar Pradesh, India
ABSTRACT
Multi- layer graphene nanoribbon is evolving as a prospective contender for deep-nanometer regime interconnects due to its
superior conductivity and current carrying capabilities. MLGNR proved to be a superior performer over SLGNR for global
interconnects. At device level, multi-gate devices such as FinFETs are the most favorable building blocks in sub-micron
technology. In this research paper these two recent technologies of interconnects and devices are combined and analysis of
signal transmission is done employing the driver-interconnect- load (DIL) system engaging FinFET driver with MLGNR
interconnect. Two-coupled line bus architecture is used for analyzing the crosstalk effects. The in-phase crosstalk delay is
improved by 54% for MLGNR using FinFET driver with higher number of fins and higher number of layers as compared to
less number of fins and less number of MLGNR layers.
Keywords: crosstalk, FinFET, Graphene nanoribbon interconnect, deep sub-micron, Multi-Layer GNR (MLGNR).
1. INTRODUCTION
A quick glance, at the ITRS’12 shows that the continued down-scaling of the dimensions on semiconductor chips is
expected to reach 7 nm by 2024 [1]. This exponential decrease in the dimension of integrated circuits in sub-micron
regime has set a requirement of research in field of semiconductor technology, both at device as well as interconnects
level [2].
At nano level device dimensions, the performance of Cu interconnects are negatively affected by grain boundaries and
sidewall scatterings [3]. So, the researchers are forced to find another feasible solution for global VLSI interconnects.
Graphene is most promising interconnects material due to its peerless physical properties that includes thermal
conductivity, long mean free path and higher current density [4]. The suitability of graphene for interconnects and
switching transistors is due to ballistic transport phenomenon in graphene.
There are adequate number of strong candidates at device level now-a-days but all are facing limitations levied by
interconnect technology. Any new technology that is beneficial in terms of power dissipation, delay or crosstalk will
have to be coordinated with an interconnect technology that provides analogous performance parameters to avoid the
inconsistency issues due to interconnects [5].
When we discuss about signal transmission in VLSI circuits, the crosstalk plays a very important role as it comes from
the undesired parasitic coupling capacitances. Due to the introduction of this crosstalk, signals got delayed or can speed
up or can get glitches due to which the whole data can change if the effects of crosstalk are not taken care of. Further
this crosstalk can be categorized as functional and dynamic crosstalk. In a coupled line structure, when victim line is
not switching then it is called functional crosstalk but when both aggressor and victim lines are switching then it is
called dynamic crosstalk.
In this research paper, dynamic crosstalk of MLGNR interconnects with FinFET driver has been analyzed. The results
are studied for various interconnect lengths, widths, number of layers as well as for different number of fins of driver
and load. The organization of the paper is as follows. Section 2 gives the brief overview of Graphene nanoribbon and
FinFET technologies that are used in the study. Section 3 elaborates the RLC model of GNR as sub-micron VLSI
interconnect. Section 4 explains the simulation setup and results are discussed in section 5. Then the paper is concluded
in section 6.
2. TECHNOLOGIES USED
2.1 Interconnect Technology: GNR
A sheet of graphite, firmly packed into a 2D honeycomb matrix structure and one-atom thick building block of carbon
allotropes called graphene, has emerged as an outstanding material of the sub-micron CMOS designing era [6]. When
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Volume 4, Issue 2, February 2015
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carbon nanotubes are unzipped, they form a ribbon like structure resulting in Graphene nanoribbons. It is done because
due to graphene’s zero bandgap, it cannot be used directly to make transistor devices, so the logic applications [7].
So, a further limitation of the electrons of graphene in one of the in-plane directions is required and it results in
graphene nanoribbons. GNRs own properties similar to CNTs because these are produced from CNTs. It is a
semiconductor with zero bandgap, very high carrier mobility of 106 cm2/V-sec at room temperature, ambipolar charge
transport, linear energy dispersion, and phonon like 2D confined properties [8], [9]. In a high quality graphene sheet,
the mean free path (MFP) is ranging from 1-5 µm [10]. GNR are classified as armchair and zigzag GNRs depending
upon their termination style.
The number of hexagonal carbon rings (Na) decides the width of armchair GNRs and number of zig-zag chains (Nz)
decides the width of zig-zag GNRs [11]. The ac-GNRs can be further categorized as metallic and semiconducting based
on number of hexagonal rings (Na) while zz-GNRs are always metallic [12]. Another classification of GNR
interconnects can be done as single layer GNR (SLGNR) and multilayer GNR (MLGNR) depending upon the number
of layers [13]. SLGNRs are not suitable for the interconnect applications because they have higher resistance whereas
MLGNRs have multiple parallel conduction paths so their resistance decreases by the concept of parallel resistances
and thus they are appropriate for interconnect applications in sub-micron VLSI circuits [14].
2.2 Driver and Load Technology: FinFET
FinFET has its technology roots in 1990s. It is a transistor with multiple gates having non-planar architecture built on
SOI substrate. The distinctive characteristic of this device is that its conducting channel is enfolded under a thin silicon
“fin” which forms the body of device. This FET structure would control short-channel effects and reduce leakage by
keeping the gate capacitance in closer proximity to the whole of the channel [15].
In 2012, Intel started using FinFETs for its future commercial devices. This Intel's FinFET is triangular in shape
instead of rectangular because a triangle has a higher structural strength and can be more reliably manufactured or
because a triangular prism has a higher area to volume ratio than a rectangular prism thus increasing switching
performance [15].
Figure 1 Structure of FinFET [15].
FinFETs are analyzed up to 37% faster, the dynamic power consumption is less than half and static leakage current is
reduced by 90% as compared to conventional CMOS. So, the researchers can enhance the performance of circuits in
terms of speed by using same or less amount of power. By this new device technology, the needs of nanometer era
applications can be matched and the performance of circuits can be enhanced [16].
3. MODEL AND GEOMETRY
OF GNR INTERCONNECT
The distributed RLC model for MLGNRs is shown in Figure 2. This model comprises of distributed capacitance of
GNR (which includes electrostatic and quantum capacitances), the distributed inductance (which comprises of the
magnetic and kinetic inductances). These components are same as in CNTs [17].
Equations 1 to 5 express the value of quantum contact resistance RQ, quantum and electrostatic capacitances CQ and CE
respectively and kinetic and magnetic inductances lK and lM [10], [18], [19].
Figure 2 Distributed RLC model of MLGNR interconnect [17].
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Volume 4, Issue 2, February 2015
RQ 
 h / 2q  / N
2
ch
ISSN 2319 - 4847
N layer  12.94 K  / N ch N layer
(1)
CQ  ( N layer N ch 4q 2 / hv f )  (N layer N ch * 193.18) aF /  m
(2)
CE  ( 0 * w / d ) aF /  m
(3)
lK 
 h / 4q v  / N
2
f
layer
8.0884 / N
N ch 
layer
N ch  nH /  m
(4)
lM  0 *  d / w  nH /  m
(5)
N ch  N ch , electron  N ch , hole N ch
  1  exp(( En , electron – EF ) / k BT )]1   1  exp ( EF  En , hole  / k BT )]1
(6)
where
Nch= number of conducting channels in one layer,
Nlayer= number of GNR layers,
h = Plank’s constant =6.626×10-34 J.s, and
q = electronic charge =1.6×10-19 C.
vf= Fermi velocity = 8* 105 m/s for GNR
En,electron (En,hole) = minimum (maximum) energy of the nth conduction (valence) sub-band.
Due to electron tunnel transport concept, mutual capacitance and mutual inductance also comes into picture for
MLGNRs. It is given by [20].
lmlayer ( j 1, j )  0 *   / w  nH /  m
(7)
Cmlayer ( j 1, j )   0 *  w /   aF /  m
(8)
where d express the distance of GNR interconnect from ground plane, w is the width of MLGNR, ∂ is distance between
two adjacent layers, μ0 and ε0 are the magnetic permeability and electrostatic permittivity of free space respectively.
Figure 3 shows the geometry of MLGNR interconnect.
Figure 3 Geometry of Multilayer GNR interconnects [20].
4. SIMULATION SETUP
In this paper, we have analyzed crosstalk delay of MLGNR interconnects with DIL system of FinFET driver and load.
For simulation of crosstalk delay, two-coupled bus architecture is used. One line is called aggressor and another is
called victim line. There is a coupling capacitance CCM generated between these two lines which is dependent on the
spacing between the two coupled lines that are aggressor and victim. CCM is given by [21]
CCM   0.5 / {1   s /

 0.87 / {1 

2
 d  t   } C[ BCP ]  t /  s / 2  ,
 s / 2 /  d  t 
2
2d /  s / 2  
(9)
} C[CP ]  w / s 

where CBCP shows the capacitance to ground of the bottom layer and CCP shows the coupling capacitance in-between
two coplanar plates [21].
In this work the number of layers of MLGNR are varied from 10 to 100 at the global interconnect lengths (100μm to
1000μm). Number of fins is varied from 3 to 5 with width variation from 10 nm to 100 nm. The setup is using FinFET
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International Journal of Application or Innovation in Engineering & Management (IJAIEM)
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Volume 4, Issue 2, February 2015
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driver and crosstalk delay is measured for in-phase as well as out-phase cases at 16nm and 7nm node. Predictive
technology models of BSIM-CMG by BSIM group at University of California, Berkeley are used [22]. The RLC model
of MLGNR are used for the parasitic values extraction of GNR interconnect. The power supply used for simulation is
VDD = 0.7 V.
Figure 4 Two Coupled line bus architecture of MLGNR interconnect.
5. RESULTS AND DISCUSSIONS
Dynamic crosstalk delay for both phases, in-phase as well as out-phase is observed using setup shown in Figure 4. All
simulations are done in TSPICE for number of layers variation of 10, 30, 50, 70, 90 and 100. FinFET is taken with
number of fins M=3 and M=5. Width variation is 10nm, 50nm and 100nm. Length of interconnect is varied from 100
um to 1000ums. Figure 5 to figure 10 shows the variation of in phase crosstalk delay for different number of layers.
Figure 5 Propagation delay variation of MLGNR interconnect with varying lengths, widths,
and M=3 and M=5 for Nlayer =10
Figure 6 Propagation delay variation of MLGNR interconnect with varying length, widths,
and M=3 and M=5 for Nlayer =30
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Figure 7 Propagation delay variation of MLGNR interconnect with varying lengths, widths,
and M=3 and M=5 for Nlayer =50
The delay is plotted against the length variation of interconnect. These graphs from Figure 5 to Figure 10 clearly shows
that the delay increases with increase in length for less number of layers but for higher number of layers delay is
decreased. Also these graphs demonstrates the delay variation for both number of fins M=3 and M=5. It can be clearly
concluded that for higher number of layers the delay with more number of driver fins is less than the delay with less
number of driver fins. So it can be concluded that less crosstalk delays can be obtained with higher number of layers
and more number of driver fins.
Figure 8 Propagation delay variation of MLGNR interconnect with varying lengths, widths,
and M=3 and M=5 for Nlayer =70
Figure 9 Propagation delay variation of MLGNR interconnect with varying lengths, widths,
and M=3 and M=5 for Nlayer =90
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Figure 10 Propagation delay variation of MLGNR interconnect with varying lengths, widths,
and M=3 and M=5 for Nlayer =100
Table I shows the improvement in delay for large number of fins in comparison to less number of fins for different
widths and lengths of MLGNR interconnect. This comparison clearly shows that using more number of fins at higher
number of layers will be beneficial in terms of crosstalk delay. This delay improvement is more at longer lengths so it
can be concluded that at global interconnect level this FinFET device and GNR interconnect combination will be very
efficient in crosstalk perspective.
Table 1 Percentage Improvement in Crosstalk Delay for M=5 w.r.t M=3 at various widths and lengths of
MLGNR Interconnect
MLGNR
Interconnect
length (µm)
100
200
400
600
800
1000
% improvement in in-phase delay for
number of fins (M =5) w.r.t number of
fins (M =3) for widths
W= 10nm
W= 50nm W= 100nm
2.02
1.4
1.7
3.27
3.21
2.91
7.62
7.72
7.82
14.7
14.54
14.8
31.62
31.84
32.01
54.61
54.63
53.69
6. CONCLUSIONS
This research paper shows the signal transmission analysis of MLGNR interconnect with FinFET driver and load
system. From the simulations it can be concluded that propagation delay of two coupled line bus architecture reduces
with increasing length of MLGNR when there are more number of fins and more number of MLGNR layers. For small
number of layers this delay reduces up-to some length and again start increasing. So this MLGNR interconnect and
FinFET driver combination will be useful in today’s scenario because it is already proved that MLGNR is better than
SLGNR at global interconnect lengths and when it is combined with FinFET driver than it will be more beneficial in
minimizing crosstalk induced delays. Therefore this combination will be very rewarding for future high speed and deep
sub- micron VLSI technology.
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AUTHORS
Vangmayee Sharda has done M.Sc. (electronics) in 2006 from Banasthali Vidyapith, Rajasthan,
M.Tech. (VLSI) in 2011 from Shobhit University, Meerut. She has worked with BARC for 2 years
(2006-2008) in field of ASIC Designing. She taught in Banasthali University as lecture in 2008-09.
She is currently working at Amity University, Noida, as Assistant Professor since 2009. Her research
interests are interconnects, ASIC designing and sub-micron VLSI. She is pursuing Ph.D. in GNR
interconnects from Shobhit University, Meerut (U.P.).
Dr. R. P. Agarwal is currently working as Vice Chancellor at Shobhit University, Meerut. He was
former Vice Chancellor of Bundelkhand University, Jhansi. Prof. Agarwal has rich varied experience
of teaching, research, development and administration. He has 41 years of teaching experience and
has published more than 100 research papers in referred International and National Journals.
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